Kenwood DP-3010 Service Manual page 43

DP-3010
CIRCUIT DESCRIPTION
The above mentions were the steps in transfering of the
Subcode Q Data to the CPU.
Also, the internal RAM divides the 80 bits into two blocks,
A and B. This is to make it possibile to write the Sub-code
Q Data from TC9200BF and to read this to the CPU at the
same time, individually. In other words, writing to A block
while reading B block and visa versa is switched internally.
The QDRE Signal "L" level interval (Read Enable) is about
80 frames (about 10ms). Also when the SQRD command
is input, 20 words of Q data are read while QDRE becomes
"H" level. While Tracking Search is in operation, the QDRE
Signal will not be set {to "L" Jevel).
DP-3010
CIRCUIT DESCRIPTION
@ Data Processor Interface Circuit
1) Control Data (SCDA) Output Circuit
SQRD Command Input
DA/CO
BUS3 R
BUS2 i)
BUSI 0
BUSO ie)
1¢K 2 3 20CK
BUCK Y \ | \ |
More than 4 ys More than 4 us 1
|
!
Sub-Code OQ, Data Read interval |
'
|
DA/CO ACK
BUS2
BUS3 i Q Da Higher Value Side
eee
or [os oe or] ape
|
|
puso a
Se
avd
|
Sub-codeanate | fstWord | [2 [3 [20] Nemes
1 2 19
QDR
{internal Read Clock)
1 igh oat Sas
\ Read Disenabie
QDRE Read Enable
Q Data 20 Word Read Operation Complete
Note: D,,: MSB (Highest Value} bit
Diagram 7-35 Sub-code O Data Read Process Timing
Chart
80
TC9201BF. Each information is selected with the input of Control of MUT ON/OFF is possible
ence with the trailing edge of COFS. the Revison Mode HOSTP: Correction Operation Stop Commard ("L""
for Correction Operation STOP)
Control of MUTC and HOSTP is gessible
with the SERTO command.
ESGM, ESGL, WSEG: Control of the Se'sction S:3nal of
the Frame Synchronizing Signal Comoensa-
tion Circuit Correlation is cassible wth the
SETR1 command.
Frame Synchronizing Signal.is continuously being trans-
fered to TC9200BF.
Control Data Details
ATT: —12 dB attenuation command ("L" for At-
tenuation ON)
Control is possibie of the ATT ON/OFF with
the SETRO command (ATTC)
COFS
soon Ed Ged es
Diagram 7-36 Control Data Output Timing
2) Processer Status Data (SPDA) Input Circuit
Required information is serial input from the SPDA pin for Processer Status Data Details
the TC9200BF Status Data. FSPS: Synchronized Status Flag ("L" for synchro-
Each data input, in reference with the trailing edge of nized condition)
COFS, the Revison Mode Frame Synchronizing Signal, is DIV+, DIV—: Disc Motor Control Signal
continuously being transfered from TC9200BF. Note: For other data, see TC9200BF Technicai Infor-
Only three of the internal data of TC9201BF, FSPS, DIV+ mation of Page 40.
and DIV— are used.
COFS | | |
cron [Fave] Fars [wore] cami [ can [over [cise [our [auri [eure] ons [ow]
Diagram 7-37 Processer Status Data Input Timing
81