Kenwood DP-3010 Service Manual page 19

The Decision/Result is output one block prior to the 80-bit Q Data being output
fe}
25 SUBQ ie) i Sub-code Signal Q Output Pin. PFCK fal! edge synchronized before Q Data 1s output.
0 T Sub-code Sink SO and $1 Pin. When Sub-code Sink is detected in SO or $1, "H" level is output for that frame
LC.
, During PLL Phase Clock: 4.32 MHz 'Duty Cycle = 50%}
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340 COFS i oO Revision Mode Frame Synchronized Output Pin. f = 7.35 kHz ((X'tal divided)
a 8 ha
35
: WOCK : Oj Word Clock Output Pin. Clock divided 16 times from BCK. (Duty Cycle = 50%) f = 88.2 kHz.
Diagram 6-1
Input Signal Timing Chart
36 } EMPH
ig Specified Emphasis ON/OFF Signa! Output Pin. Confirmation of existence of Emphasis for the Q Data Control Bit
| | {When "H", Emphasis ON) When the CRC Decision/Result is confirmed as OK twice, Emphasis is confirmed
a7: HOF | O
Output Data Correction Flag Output Pin. Flag added every 8 bits, at the same time as data output, LSB and MSB
: l side are synchronized with the SYCK fall in Flag order
i | Channel Clock Output Pin. This is the WDCK ctock signai divided twice, when "L" level Lcx and when "H" evel
pe SHOK 2 Rev data is output. f = 44.1 kHz (Duty cycle = 50%)
! put. f = 4 4 . ty cycle = 5 0 % !
39°C; BCK fe} Bit Clock Output Pin. f = 1.4112 kHz (Duty Cycle = 50%}
r
40
Dour le) Data Output Pin. The BCK fail is edge synchronized from the MSB side to be serial output.
4) | SYCK i oO
Symbol Clock Output Pin. This is the clock divided eight times from BCK. f = 176.4 kHz (Duty cycle = 50%)
42 | ARTR fe) Rew Data Aperture Signal Output
43 : APTL ie) dl Lc Data Aperture Signat Output
le 44 CK8M ne) 8M Ciock Output Pin, (Xtal 16.9344 MHz clock divided twice}
i
b 45 : 17MO ie) 17M Clock Output Pin. (x'tal 16.9344 MHz Buffer Output)
46 NC io | No connection
47 i x0
| O Crystal Resonator Connection Pin. The Crystai Resonator provides the System with the desired Clock Frequency
_ | (Xtal 16.9344 MH2)
48 :
a | ; Crystal Resonator Connection Pin. The Crystal Resonator provides the System with the desired Clock Frequency
i L {X'tal 16.9344 MHz)
49
| CKSE : \ Clock Selection Pin. When the X-I Input Clock is "H" or OPEN then 16.9344 MHz, when "L" then 8.4672 MHz is
ae : " selected
50~52. TES! ~TES3 | I Test Pin. Normally used in "HH" or OPEN
53 Vo0 > — | Power (+5 Vv)
54 Vss "= | GNDPin
55 TESO 11 Test Pin. Normaily used in "H" or OPEN
86 ~59 | ADO —AD2 ' 0 | External AAM Address Signa! Gutput Pin
at TES? \ 44 Test Pin, Normally used in "H" or OPEN