Kenwood DP-3010 Service Manual page 20

DP-3010
36
CIRCUIT DESCRIPTION
2) Synchronizing Signal Correction/Interpolarity Circuit
The Frame Synchronizing Signal shown in Diagram 6-1 is
used in the internal Demodulation Circuit for synchroniz-
ing but there is a possibility of miss detection due the to
quality of the input signa! if the Synchronized Signal is
used as it is.
Therefore the following powerful Synchronizing Signal
Correction Circuit is needed.
The Synchronizing Signal Detachment Circuit is shown in
Diagram 6-2.
As shown in this Diagram, the whole circuit is constructed
of a 1/588 Division Curcuit, a Gate Signal Producing Cir-
cuit (WIND Gen} and an Off Synchronizing Counter
(NSFC).
Normally the Gate Signal (R-WIND) produced from the IFC
output used for correction of the Proper Frame Synchroniz-
ing Signal (Only the Synchronizing Signal input to
R-WIND is used for synchronizing the Demodulation Cir-
cuit).
When a non-synchronized condition continues, such as
during POWER ON, when a Bust Error occurs or when the
PLL circuit is instable, P-WIND from the WIND Gen.
Output and Off Synchronizing Frame Counter (NSFC) are
put into operation to effortlessly synchronize the condi-
tion,
See the following simple explanation for the steps taken in
synchronizing.
1 The setting of the number of times of Off Synchronized
Detection, N, is done by selecting one of the 2-bit N =
2,4,8,12 in ESGL and ESGM.
EFMI
oe Frame Synchronizing
Pattern Detection Circuit
2 When a condition where the Frame Synchronizing
Signal does not enter R-WIND continues and NSFC
output become N, the NSFC operation stops. At the
same time the FSPS Ouput Level changes from "L" to
"H" turning on each Correction Circuit.
3 When the FSPS Level changes to "H". P-WIND starts
the SET RESET and the Frame Synchronizing Signal is
synchronized with IFC.
4 When the Frame Synchronizing Signal is input to
R-WIND, it is judged as the Proper Synchronizing
Signal and the synchronized NSFS of IFC is cleared
At this time, the FSPS Level! changes to "L" and the Input
Synchronized Pattern from the interna! system completes
synchronizing.
Also, besides the FSPS there is the FSLO Status Flag
where FSLO and FSPS are output through the SCDA pin.
ESGM and ESGL are input to the SCDA pin from
TS9201BF.
WSEG details are available on Page 40
| wsEG | R-WIND Width
+7 PLCK
fo | s3Pick |
ht is possible to change the
R-WIND Width with WSEG.
Diagram 6-1
ESGL ESGM FSPS
OFF Synchronizing NSEC
Frame Counter
WIND Gen.
Gate siti
WSEG
Diagram 6-2 Synchronizing Signal Detachment Circuit Construction
DP-3010
CIRCUIT DESCRIPTION
e EFM Signal Demodulation Circuit
The EFM Signa! Demodulation Circuit, with reference to
the Main Frame Counter (IFC) of the Synchronizing
Detachment Circuit, consecutively demodulates the Sub-
Code Signa! within each frame and the 32 Symbol! Data
(Restored to digital signal from EFMl) from 14 bits to 8 bits.
AD 10
Connection to
External RAM
The demoduiated data is set to the internal latch. and writ-
ten into the external RAM by using Address AO — A10
from the RAM Address Control Circuit, the Write Signal
(RW = L). and Chip Enabie Signal (CE = L) in one symbol
{8 bit) units through IO 0 — 7.
TC9200BF
S-RAM
Diagram 6-3
© Sub-Code Signal Demodulation Circuit
The 8-bit data in each frame for control and dipiay in sub-
code P, Q, R, S, T, U, V, W. is set to the internal resister
before the leading edge of PFCK (pin 27). This is synchro-
SUBD
OUTPUT |
SO, S1 OUTPUT TIMING
nized with the trailing edge of the read clock input from
the EXCK pin. This is emitted in serial from the SUBD pin.
Each condition for the output data is as foliows.
NORMAL TIMING
; When SO output. "H
i When S1 output, "L"
+
Sub-code P Data
Sub-code Q Data
| Not Fixed Sub-code R ~ W Data
Diagram 6-2 SUBD output data details
PFCK
suso XY sost XY YY XY NY \ bfixed
— ti cl Ng Ne io Ss et
EXCK 1 2 3 4
Not Fixed —|
6 7 8 9 10 11
Diagram 6-4 Timing Example (1): During $1 Detection (Only Detect SO one frame before)
PFCK l
SUBD _
EXCK 1 2 3 4
~CP OCR CSCT C tines
6 7 8
Diagram 6.5 Timing Example (2): Normally