Kenwood DP-3010 Service Manual page 21

DP-3010
338
CIRCUIT DESCRIPTION
© Sub-code Signal Q Data Demodulation Circuit
The Sub-code Signal Q Data Demodulation Circuit demod-
ulates the Q Data of the Sub-code Signal in units of 98
frames. It then does Error Detection/Judgement Process-
ing of each data before output.
In each system, the Sub-code Synchronizing Signal is
synchronized at SO and S1, so that the Error Detection/-
Judgement Processing can be done by consecutively
reading CRCC 80-bit Q Data. From the SBOK pin Error
Detection/Judgement results and from the SUBQ pin the
demodulated Q Data are synchronized with the PFCK lead-
ing edge and then output.
Block (N)
mcoae
Sub-code Q Data
suBQ
e SO,S1: The level of the Sub-code Synchronizing
Signal Output is "H" in the frame during SO
and S1 detection.
The Sub-code Q Data CRCC Check Judgement
Result Output is "H" level during No Error.
Each signal from SO $1, SUBQ, SBOK and PFCK are moved
to TC9201 BF.
The 80-bit Q Data is initially read into the internal RAM of
TA9201BF.
When needed, this data is sent from the bus line to the
MPU through the CPU Interface.
@ SBOK:
Block (N+1)
DP-3010
CIRCUIT DESCRIPTION
6-3-2 Error Detection, Delete and Correction
Processing Mode Block Operation
Information
© Timing Circuit
The Clock Signal needed for internal operation is as
shown in Diagram 6-8, where that by only connecting a
crystal and condensor is all that is necessary.
The selection of the frequency of the crystal is done by set-
ting the CKSE pin.
CKSE="L" fx'tal = 8.4672 MHz
CKSE = "H" fx'tal = 16.9344 MHz
ve
Note: Use a crystal with low Cl values for best Start-up
Characteristics
or
Diagram 6-8
|
Fe ee nee Cee (elne ae eee ae
Detection ; Detection
|
|
\
Block (N) CRCC Check Judgement Result
SBOK Block (N—1) CRCC Check Judgement Result
Diagram 6-9 Sub-code Q. Data Output Timing
© Other
In the Control Bit Information of the Sub-code Signal Q
Data, the Emphasis ON/OFF Judgement Output is output
through the EMPH pin.
When the level of the EMPH Output is "H", the Emphasis
When two biocks (two 98 frames) of Q Data CRCC Check
Judgement Results (SBOK output) are found to be con-
secutively normal, the data is valid.
@ RAM Address Control Circuit
TC9200BF reads modulated input data by use of the exter-
nal RAM (8-bit X 2 k) address controi and does deinter-
leave processing.
input Data Jitter Absorbing Capability for the memory has
a capacity of +5 frames; constant surveillance (Differen-
tial Detection) of the Input and Output Data Rates are
provided in the design for best results of the RAM Address
Control.
In response to the condition of buffer capacity, the follow-
ing DIV+ and DIV— signals are output. DIV+ and DIiV—
are used for Disc Motor CLV Servo Control and including
the motor a Field Back Loop is constructed.
Therefore, the actual Input Data Jitter Absorbing Capabili-
ty is being enhanced
Also, when the buffer capacity exceeds +5 frames. it is
taken as Buffer Over thus the BUF-OV Signal is output.
During BUF-OV, DIV+ and DIV— are reset, the Mute On
Buffer capacity is forced to become —1. BUF-OV is thus
cancelled. and the RAM Address Control is continued.
is ON.
stein Wee asl eae TIE dle agee Ie a e
|
! i
SBOK
First Block
Second Block
\
|
U — m= ey
EMPH
Not fixed
Emphasis ON
The de-emphasis of
the Output AMP is ON.
CRCCS yusgement Normat
Diagram 6-7 Emphasis ON/OFF Output Timing
Buttercapecity | —6 | -5 | 4 | -3 | 2] -1 J 4 | 2 [os [vs [os Ts |
Diagram 6-9 Control Signal DIV+, DIV—, BUF-OV Output Timing
pin. As shown in Diagram 6-3, three bits, BUF 2 — 0, are
output.
it is possible to externally monitor the Buffer Capacity by
checking the Data Status Signal Output from the SPDA
IF BUFO Buffer Capacity
eee = 1 =1 0 0 0 +1
Lo AG i 0 Fay eileen € o r O4 Ky TS +2
i e ae ik ari: Aa eer. (i Meee (iene ene
a oO 0 4 ani BO Se Oa ae ge
0 1 1 -5 tila Oe ee ge ae
Diagram 6-3 Buffer Capacity Output Data
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