Kenwood DP-3010 Service Manual page 42

DP-3010
CIRCUIT DESCRIPTION
NKIC(C400} AND NKICF(D400) Search Command Set
GUP1 Bit Data = 1
HYS1 Bit Data = 0
FGC Bit Data = 1
TGC Bit Data = 0
Hiz
SE a
DFCT2 Detection DFCT1 Detection Shock Detection © OFCT2 Detection
2CL1
ZCL2 \ / —— \ /
TESH
ON
GUPCL =1
TGUL VREr
TGUH VREF HiZ '
GUPCL =0
DFCT VREF Hi2z
FMGU VREF
Command
e ——<—<————$_ < $$
Q Tracking Field Servo ON
v4 . :
2 Diagram 7-31 Defect/Shock Detection Example 1
NKIC(CO00) AND NKICF(DO00) Search Command Set
GUP1 Bit Data = 0
HYS1 Bit Data = 1
FGC Bit Data = 0
TGC Bit Data = 0
level during hysterisis operation (HYS1 bit date = 1)
Hiz Shock Detection Period
SEL - - oe — L —-—
DFCT2 Detection DFCT1 Detection DFCT1 Detection
Shock Detection
2c1
ZCL2
«~ Hysterisis Operation
TESH
TGUL
VREF During Hysterisis operation
7 Defect Detesetion is not done
DFECT VREF Hiz tT sGuPct—Don't care
FMGU i
VREF alk
Command |
78
Note: In Normal Play Mode, the SEL pir. will become "L"
DP-3010
CIRCUIT DESCRIPTION
© Sub-code O Receiving (RAM Control) Circuit
SO, $1, SUBQ, and SBOK Signals are transfered from
TC92OOBF.
In the Sub-code Q Data Receiving Circuit, the Sub-code
Sychronizing Signal, SOQ and S1, sychronize with the
TC9201BF interna! RAM Control Circuit to receive the 80
bit Sub-code Q Data into the internal RAM (4 bits x 20
words X 2 blocks)
TC9201 BF
SuUBQ
Input from PFCK Sub-code Q Data
RAM Clock A, B
TC9201BF
és!
comes
SBOK
The CPU checks the TC9201BF internal conditions and if
Read Enable. the Read Command (STRD)} is input. In re-
sponse to this, TC9201BF sends the 4 bits with 20 words
for a total of 80 bits to the CPU through BUS 3 ~ 0. The
steps for this operation are explained in. the following in
reference to the N Block for Sub-code Q Data in the
Timing Chart of Diagram 7-32.
CD Bus
Control Clock
<> ~Te CPU
Diagram 7-33 Sub-code Q Data Receiving Circuit
Construction
1 Synchronized to the RAM Control Circuit in the N Block
SO and $1.
2 The Sub-code Q Data that has been synchronized to
the trailing edge of PECK (Play Mode 7.35 kHz), is
output through the SUBQ pin in serial bit form of 96
bits (80 bits, data + 16 bits, CRCC). Of the 96 bits, only
80 bits are written into the internal RAM.
3 Confirm that SBOK is "H" levet during (N+1) Block Data
Input and set QDRE ('Sub-Code Q Data Read Enable)
Signal to "L" levei (Read Enable}. At this time, 4 bits (1
word) of Q data is preset to the internal resistor. and
then the DA/CO line is switched to "L" level
—— N Block
SUBQ
4 The CPU confirms whether Sub-code Q is in a Read
Enable Condition. Confirmation is done by checking the
DA/CO and BUS2 (QDRE Signal Monitor Line) fines in
idle Mode, and the input of the STRD Read Command
in those not it Idle Mode and checking each BUS2
(QDRE Signal Monitor Line} lines
5 lf QDRE = "L" level then it is possible to read the Q
Data into the CPU. The Read Command SORD is input
and 20 words (1 word = 4 bits) or 80 bits will be trans-
fered to the CPU through BUS 3 ~ © with the timing
shown in Diagram 7-35.
(N+1) Block
093 J ooa ¥ pes} so ¥ si {oo J or} o2 } v3 { oa jos X oe J
$0 $1 I |
SBOK (N—1) Judgement Result
N Block CRCC Judgement Result
Diagram 7-34 Sub-code Q Data Reception Timing
Chart
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