Kenwood DP-3010 Service Manual page 33

DP-3010
CIRCUIT DESCRIPTION
1) AFCS Signal Producing Circuit
AFCS is the switch to Servo Mode. When the AFCS re-
ceives the FSPS for the SPDA pin of the TC9201BF or the
SETRO Command from the CPU is input, the Mode is
switched. Also, the FSPS Signal informs whether the
Synchronized Division Circuit is in operation thus turning
the Tracking Servo ON and if the EFM Signal has Phase
Locked, it will maintain an "L" level.
The conditions for AFCS to switch between "H" and "L"
level are shown in Chart 7-3.
[Conditions for AFCS to switch from "H" to "L""
Conditions for AFCS to switch from "'L" to "H"
| When FSPS "L" level continues for 16 frames
When FSPS "H" level continues for 64 frames
Chart 7-3 AFCS Switch Conditions
2) AFC Signal Producing Circuit
The use of either AFC1 or AFC2 Circuits is decided in Main
Servo and Pre Servo Mode. Each mode detects the Fre-
quency Control Signal (AFC) required, as a result of this de-
tection, outputs the PWM wave from the DMFC pin. This
PWM wave controls the Disc Motor speed.
The following explains the AFC1 and AFC2 Circuits coera-
tions.
1 AFC1 Circuit: (Main Servo Mode, AFCS = L. Synchro-
nized Division Circuit is in operation:
The AFC1 Circuit divides the PFCK (Play Mode 7.35 MHz}
by four, and uses this frequency content to detect the X'tal
2.1168 MHz. When the Disc Motor is correctly locked,
PFCK/4 = 1152 Clock. The system is designed to keep the
Frequency Control Range within about +5% in TC9201BF.
As shown in Diagram 7-16, in the Frequency Content De-
tection Circuit, the PFCK/4 (Disc Motor Frequency Infor-
mation) frequency content is passed to a PWM wave that
has 7-bit resolution and then output through the DMFC
pin.
Here, the DMFC pin output consists of three values, VOD2
(2VReF}, VSS(O V) and VREF (+2.2 V).
4152 0 1215
(Brake Torque applied) FAST — Motor Revolution — SLOW (Speed-up Torque applied)
Diagram 7-15 CLV Servo Frequency Control Range
DP-3010
CIRCUIT DESCRIPTION
2 AFC2 Circuit: (Pre Servo Mode, AFCS = H, Synchro-
nized Division Circuit is not in operation)
The AFC2 Circuit uses X'tal 8.4672 MHz from Tmax (Long-
est Inverse Level Value) from the EFM.
When one clock (4.3218 MHz) is equal! to 1T, during Disc
Motor Correct Revolution, the Frame Synchronizing Pat-
tern is 11T + 11T = 22T. This is Tmax (Longest Inverse
Level Value).
When Tmax is used with X'tal 8.4672 MHz to detect, 22T
AFC1 Circuit (Main Servo)
PFCK
AFC2 Circuit (Pre Servo}
EFMI
8.4672MHz
APC Signal
Producing Circuit
AFCS Signal
Producing Circuit
i 1/4 is Frequency Content |
é Division} it Detection Circuit 3
2M Clock
E Tmax < :
is equivalent to 43 Clock. When fhe Detection Result is
more than 43, "Disc Motor Revolution Speed SLOW", and
when less than 43, "Disc Revolution Speed FAST" is the in-
formation passed on.
During Pre Servo Mode, Tmax Q is directly output from
the DMPC pin while the 7-bit resolution of the PWM wave
is output from the DMFC pin at the same time. Here, the
DMFC pin output consists of three values, VD02 (2VREF),
Vss (0 V) and VREF (+2.2 V).
PWM
Modulation Circuit DMFC
16 kHz Carrier
DMPC
(CLV Servo Control Signal)
Diagram 7-16 AFC Signal Producing Circuit Block
Diagram
61