Kenwood DP-3010 Service Manual page 31

DP-3010
56
CIRCUIT DESCRIPTION
2) Digital PLL Circuit
When the SGS pin is set "L", the Digital PLL Circuit comes
into operation. With this, two frequencies are available,
16.9344 MHz and 17.2872 MHz (4.3218 MHz from the
EFM Input Signal Beat Rate x 4). The use of these two
crystal frequency modes is done either by inputing into
the B4MK 8.4672 MHz (16.9344 MHz/2} or fixing 84MK
with "L" level.
This Digital PLL Circuit has a unique construction where it
not only measures its own efficiency but also requires no
external components. Also, since the Lock Range and Cap-
ture Range are about +1%, the Disc Mode, from the CLV
Servo, Speed Range needs to be kept within +1%.
Aor B Selection Signal
(X'tal Selection Signal)
Frequency
Compensation
Circuit
Edge . Phase
cEMt Detection
Circuit
4.32MHz PLCK
Comparision
Divider
Control
Tri-modular
Divider
x-l 16.9344 MHz (A) or
17.2872 MHz (B)
Diagram 7-8 Basis Block Digital PLL Circuit
Construction
The operations of the Digital PLL Circuit are as follows:
1 Edge Detection of the EFMI input is done and passed to
Phase Comparison Circuit
2 In the Phase Comparison Circuit the phase difference
between the EFMI Edge and PLCK are detected after
being resolved with 2/4 (as shown in Diagram 7-9).
3 With the Phase Polar Difference Information detected
in the Phase Comparison Circuit, the Tri-modular divi-
sion difference is controlled thus controlling the phase
difference to the least possible.
The Tri-modular Divider is able to compare 1/4-0.5, 1/4
and 1/5-0.5 divisions. The division difference control of
the divider will be done only when the Phase Difference In-
formation is within +2 as shown in Diagram 7-9.
Since the Clock Frequency of 16.9344 MHz, input through
the X-! pin, will differ from four times the Beat Rate of the
EFMI input (4.3218 MHz x 4 = 17.2872 MHz). Frequency
Compensation is required.
Therefore, when the Edge Detection Period of EFM! is TP
SS 6T(1T = 1 PLCK) division difference control of the
divider will be done: and when Tp & 6T, then Edge Detec-
tion of EFMI and a 6T period is controlled. By doing this,
the system is stabilized.
-" fe) +e
=
Hee IR Nee
wictes Sah
eee
——7 Control Range
—1l +1
+1 Range |
i
| —2-1} +142 |
+2 Range
~4-3-2-1 +14+243 +4
Diagram 7-9 PLCK Division
DP-3010
CIRCUIT DESCRIPTION
3) Data Slice Level Correction Circuit
The Slice Level of the Data Slicer is normally takes the DC
content out of the Data Slice Output from the ELM signal
and feeds this back. The aim of the Data Slice Level Correc-
tion Circuit is to fix this Data Slice Level and make no ad-
justment needed possible.
Therefore, the Data Slice Correction Circuit takes the
phase deviation that occurs from the Memory Accurancy
of the Disc, when the Disc is Off Center and from Disc
Motor Jitter when the Slice Level is fixed and passes it
through the Phase Detection Circuit. Corrections are made
in reference to the Phase Differential Information detected.
In this case, the phase deviation usually occurs in low
range frequencies. Therefore, as shown in Diagram 7-10.
even when the Slice Level! varies vertically, the distance
between EFMI Leading Edge to Leading Edge or Trailing
Input Side
RF Signal
B
se spa ee — ea
|
e tnt
Edge to Trailing Edge does not change.
This means that when TA = Ts = TC, as shown in Dia-
gram 7-10, TA is the reference where after this the slice
level variation can be easily detected in TB and Tc. It is
then possible to reconstruct the original data in the DOUT
Correction Output Circuit with the detection results.
This means that when the Digital PLL Circuit in TC9201 BF
is used, not only will the there be no need to use the
Analog Stice Level Control but the Slice Level Response
will become extremely accurate with much less data
errors.
Note that the Slice Level Correction Range is less than
+27 (1T=1PLCK)
Slice Level
(Ta = Tg= Tec)
Diagram 7-10 Data Slicer Input/Output Waveform
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