Kenwood DP-3010 Service Manual page 25

DP-3010
CIRCUIT DESCRIPTION
Operation
Sub-code Signal Synchronizing Pattern SO and S1 Input Pin
BS Be
Sub-code Signal Q Data Input Pin. 80-bit Q Data as one block is serial input. and saved in the internal RAM.
Sub-code Signal CRC Check Judgement Result input Pin. (Normal = "H", Error = "Ud
Power (+5 V)
GND Pin
BUSO ~BUS3
L
Incoming/Outgoing Command and Data Bus Line. With the BUCK Start-up. the Command and Data is internally
released. Aiso during BUCK "H". the input data 's output on the Bus.
DA/CO
vo
4.
| Clock input Pin for the Incoming/Outgoing Command and Data. During Reception the "L" period will be more
than 9 ys, and "H" period will be more than 4 ys while less than 90 ys.4 ys after BUCK Start-up, DA/CO and
BUSO-3 will be switched.
7-3. Operation Information
© Timing Producing Circuit
needed for internal operation (Master Clock is 8 MHz). The
input conditions to the 84MK pin, as shown in Diagram
input or (X-l)/2 as the Master Clock by checking the 8M
Det
Note: Use a crystal with low Cl values for best Start-up Conditions
CO = 10 ~ SOpF
Diagram 7-1
X-1 Pin
4MCK Output Pin Notes
u i 16.9344 MHz
X44
17.2872 MHz
Digital PLL ON
84MK
8.4672 MHz
8.6436 MHz
2 Analog PLL ON
Diagram 7-1 Internal Clock Selection Mode
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DP-3010
CIRCUIT DESCRIPTION
@ CPU Interface Circuit (CD Bus Control Circuit)
The CD Bus Control Circuit was designed so that the con-
nection between the general purpose 4-bit CPU and the
TC9201BF could be easily achieved so that data communi-
cation could be done through only six lines, four line of the
V/O Data Bus (BUS 0-3), the Clock Line and the DA/CO line
(for the Data and Command Differential Signal).
The Bus Line conditions for the three modes, idle Mode
and the Read/Write Modes, are explained in the following
Ip Sh.
Before this though, the following points must be noted
about the CD Bus and Data Communications between the
CPU and TC9201BF.
1 Only the CPU will output the BUCK.
2 The level of the BUCK will be "H" when there is no data
being communicated.
3 The period of "H" level of the BUCK will be less than 90
ES while data is being transmitted from the CPU.
4 The BUS 3-0 Input Data should be delayed by more the
4 us in reference to the BUCK trailing edge.
5 The BUS 0-3 and DA/CO pins should be an Open Drain
CPU with Wired OR functions or Open Collector Type
CPU with an I/O port.
6 The transmission/reception of one word (4 bits) data is
to be done with the period from the current trailing
edge to the next one.
TC9201BF
Schmitt Input
Diagram 7-2 BUS Line Input/Output Construction
1) Idle Mode
This is the mode when there is no commmunications
being done with the CPU. In this mode both the BUCK and
DA/CO pin have an "H" level while the internal conditions
for the Monitor Signal are being emitted through BUS 0-3.
From BUS 0, "H" level, from BUS 1, AFCS, from BUS 2,
QDRE, and from BUS 3, FOK external signals are to be
output.
@ AFCS Signal..... CLV Servo Mode Switch Signal
(In Main Servo Mode, AFCS =
"H" Levei)
@ QDRE Signal..... Sub-Code Q Data Lead Enable
Signal
(In Lead Enable, ODRE = "L"
Level)
@ FOK Signal ...... Focus ON/OFF Judgement Signal
(in Focus ON, FOK == "H" Level}
See other reference documents for details of each of the
above mentioned signals.
In Idle Mode. when either BUS 2 or 3 are "L" Level (Sub-
Code Q Data Lead Enable or Focus OFF), DA/CO Line
will be "L" level. This means that the TC9201BF will
break into the Idle Mode when DA/CO is "L" level. It is
possible to make a smooth recovery when becomes FOK
= "L"(Focus OFF).
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