Kenwood DP-3010 Service Manual page 30

DP-3010
CIRCUIT DESCRIPTION
@ PLL Circuit
TC9201BF is equipped with an Analog and a Digital PLL
Circuit As shown in Diagram 7-1 on Page 43, there are
three modes. Switching of these modes is done by using
the SGS pin and 84MK pin.
There is an internal correction circuit for phase deviation
in the EFM for such reasons as Disc Memory Accuracy
and when the Disc is Off Center. This is very useful. espe-
cially when using the digital PLL. Therefore. this lets the
Stice Level of the Data Slicer be fixed (AC center). The
Analog PLL cannot be used for this though
1) Analog PLL Circuit
When SGS is set to "H" jevel {input of X'tal 84672 MHz
Clock from the 84MK pin), the Analog PLL Mode comes
into operation.
The Biock Diagram of this is shown in Diagram 7-6 and
the Timing Chart in Diagram 7-7.
EFMI
Also, the PLCK Phase Polar Differential Signal, in reference
to the EFM Signal Trailing/Leading Edge. is output in tri-
state form the PD pin after passing the Change Pump.
As mentioned before, the Timing of the Analog PLL Circuit
is shown in Diagram 7-7. Here the DouT output EFM signal
is data that has been delayed after being straightened out
in PLCK.
Internat External
Phase
Comparison
Circuit
Diagram 7-7 Analog PLL Timing
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