Kenwood DP-3010 Service Manual page 23

DP-3010
42
CIRCUIT DESCRIPTION
© Data Output Circuit
This circuit outputs the input data from the Correction
Output Circuit.
The channel data of both L and R, from the MSB side to
Beat Serial, are output through the DOUT pin.
edge
in the Timing Chart, Diagram 6-12.
bouT
HOF
CHCK(44.1kHz)
WOCK (88.2kHz)
SYCK(176.4kHz)
APTR
APTL
DOUT
HOF
CHCK
wOCK
SYCK
APTR
APTL
I
Len{n) 16-bit data
i) |
: Lcx{n) LSB side Levin) MSB side
|
=
peat, Sage tc
ie a oa ena aaa ae
| {
|
Ren (n) 16-bit data
{
Ren (n) LSB side Pe Len{(n+1) LSB side
Len{n+1) 16-bit data
Diagram 6-12 Timing Chart
All the data output is synchronized with the BCK trailing
The signals with connection to the Output Data are shown
DP-3010
CIRCUIT DESCRIPTION
® Control Data Input Circuit
Information needed for TC9200BF internal processing is
taken in serial mode from the SCDA pin of TC9201BF.
The circuit is designed so that data input, which is in refer-
ence with the Revision Mode Synchronizing Signal, COFS
(f = 7.35 kHz), is taken in continuously.
Control Data Details:
~ATT: —12dB Attenuation Command
(When "L", Attenuation ON)
~MUTI: Forced Muting Command
(When "L", Muting ON)
MUTC: Internal Muting Control Command
(When "L", Muting Stop)
~HOSTP: Correction Operation Stop Command
(When "L", Correction Operation Stop)
ESGM, Selection Signal for setting the times of Off-
ESGL: Synchronized
Detection in the Frame Synchronizing
Signal Correction Circuit.
WSEG: The Wind Control Signal of the Frame Syn-
chronizing Signa
Correction Circuit.
COFS f |
~ HOSTP soa Farbwr[wre] —_ [esaw[esor [wae
Diagram 6-13 Control Data Input Timing
@ Process Status Signal Output Circuit
The Revision Processing Judgement Results and Memory
Buffer Capacity Information in TC9200BF is output
through th SPDA pin and moved to TC92018BF.
The data output, which is in reference with the Revision
Mode Synchronizing Signal, COFS (f=7.35 kHz), is output
continuously.
Process Status Signal Details:
FSLO: Complete Synchronized Status Fiag
(When "L", Complete Synchronized Con-
dition)
FSPS: Synchronized Status Flag
(When "L", Synchronized Condition)
SPDA FSLO
MUTO: Internal Muting Detection Flag
(When "H", Muting ON)
Note: Will become "H" when 64F-Er.,
DIN-MISS, BUF-OV on Page 40
occur.
C2$1-0
C1 C2-0: C1 and C2 Revision Processing Judge-
ment Result
BUF2-0: Memory Buffer Capacity Output Data
DIV+, DIV—: Disc Motor Control Signal
Diagram 6-14 Process Status Signal Output Timing
43