Kit Contents; Specification - Texas Instruments ADC36 EVMCVAL Series User Manual

Evaluation Module Overview
1 Evaluation Module Overview
1.1 Introduction
This user's guide describes the characteristics, operation, and use of the ADC36xxEVMCVAL and discusses
how to set up and configure the software and hardware, and reviews various aspects of the program operation.
Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous with the
ADC36xxEVMCVAL. In the following sections of this document, the ADC36xxEVMCVAL evaluation board is
referred to as the EVM and the ADC36XXQML-SP devices are referred to as the ADC devices, respectively.
This document applies only to the ADC3683EVMCVAL and ADC3664EVMCVAL.
By default, the EVM is configured to receive external inputs for the sampling clock and analog input via AC-
coupled, transformer (balun) inputs. These transformers perform single-ended to differential conversion, and
provide a low noise/distortion passive input.
To exercise the full performance capabilities of this high performance successive approximation (SAR) ADC,
TI recommends to evaluate the ADC in the default configuration, and then evaluate in other configurations, as
needed.

1.2 Kit Contents

• ADC36xxEVMCVAL
• Mini-USB cable

1.3 Specification

The ADC36xxEVMCVAL receives power from the 5 V jack at J18, which is then converted to +1.8 VDC for
AVDD and +1.8 VDC for DVDD. This conversion happens by way of two ultra-low noise, ultra-high PSRR,
low-dropout regulators, TPS7A9401DSC. USB-to-SPI communication is established using the FTDI (FT4232HL-
REEL). The ADC clocks are supplied externally. The default configuration is to input the device clock (CLK)
single-ended into J12 and the data clock (DCLK) single-ended into J14 (high quality external clocks are used to
achieve best AC performance). The analog inputs by default are supplied through J6 for channel A and J9 for
channel B where the signal is AC coupled through the baluns (ADT4-1WT). The analog input full-scale is 3.2
V . The analog input is driven at -1 dBFs (approximately 2.8 V
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The ADC36XXQML-SP family has a +1.6 V voltage reference (VREF) that can be supplied internally or
externally. By default, the EVM is configured to supply an external voltage reference using REF35160QDBVR
Precision Voltage Reference which is supplied using the VREF test point and 3.3 V supply. At any time, the
reference can be changed to internal via SPI write.
The ADC36XXQML-SP family uses an unbuffered analog input, so a glitch filter is required to attenuate the ADC
sampling glitch from when the sampling capacitors switch (sample/hold). The glitch filter acts as a low pass filter
with a corner frequency (F
The ADC36xxEVMCVAL LVDS output data is routed to an FMC connector, and then connected to an LVDS
Interposer card. This interposer card then maps to the HSMC connector of the TSW1400EVM to capture the
ADC36xxEVMCVAL SLVDS clock and data signals.
2 ADC36xxEVMCVAL Evaluation Module
) at 30 MHz (accepts DC to 30 MHz).
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) in all examples in this user's guide.
pp
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SBAU446 – DECEMBER 2023
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