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D. Other circuits
[a] EEPROM (IC10) circuit
P40/AN0
P63/PRDY
This memory stores the sensitivity data of the reflection sensors, the set position data of the originals on the original glass, and the counter values
such as the original pass count. Data communication with the CPU (IC3) is made through the three-wire serial interface. The stored data remains
even though the power is turned off.
The IC10 1 pin is the chip select pin, which is driven to HIGH to perform data communication.
2 pin is the serial clock pin. The serial data is transmitted in synchronization with the clock inputted to 2 pin. 3 pin is the input pin of serial data from
the CPU. 4 pin is the output pin of serial data from IC10.
D8, R130, and C50 form a circuit which maintain the IC10 voltage in case of a sudden, unexpected drop in the power voltage.
[b] Reset circuit
RESETA
C16
This circuit generates the reset signal of he CPU and G/A, and is composed of IC1 and its peripheral circuits.
The IC1 performs resetting when supplying the power and in case of abnormal drop of +5V. After supplying the power, the power line reaches about
4.3V. The reset state is maintained for a certain period afterward. The reset state remaining time depends on the capacity of C19.
This circuit is also provided with the watch-dog timer function. The watch-dog timer is included in the G/A (IC13), and starts operation when RES2
becomes HIGH. This monitors the CPU abnormalities such as a hang-up.
RES2 is reset for the watch-dog timer in the G/A, and is separated from the CPU and the G/A RES1 by means of D10. Therefore, the CPU RESET
and G/A RESET will not become HIGH in advance to RES2 does.
For monitoring, some data (initial value) is written from the CPU to the G/A once every 5ms. (The value is reset to the initial value once every 5ms.)
This data is used to count down in the G/A. The count will not be "0" because it returns to the initial value every 5ms. If however, the CPU hangs up,
the data does not return to the initial value and the count becomes "0." At this time, reset is made from the G/A to the CPU and G/A (RES1), and
retry is made until the CPU resumes.
+5V
D9
R38
65
16
15
P64/A0
14
P65/CS
R35
R37
R38
+5V
R19
IC4.1
1
2
+5V
+5V
R74
IC1
7
D10
VCC
5
6
C
OUT
GND
4
C19
R129
R114
R128
4
DO
1
R127
CS
2
SK
R126
3
DI
EEPROM circuit
+5V
R67
IC4.5
10
11
Reset circuit
– 32 –
+5V
D8
E2ROM5V
R130
+
C50
IC16
6
ORG
7
TEST
CPU
TP51
26
RESET
C18
G/A
TP26
38
WDT
39
RES2*
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