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Signals
Description
NAND_BOOTn
Low = Enable GPMC_nCS0 for NAND flash
(1)
boot
NOR_BOOTn
(2)
Low = Enable GPMC_nCS0 for NOR flash boot
MMC2_BOOT
Low = Enable MMC2 Interface for eMMC flash
boot
QSPI_BOOT
Low = Enable QSPI1 Interface for QSPI flash
boot
UART_SEL1_3
High = UART3 Interface for UART boot is
enabled
(1) Routing control for GPMC_nCS0 is "shared" between NOR & NAND Flash memories. Ensure that only one DIP switch, SW5.P1
or SW5.P2, is ever set to "ON" state at any one time so that GMPC_nCS0 is only connected to one memory. Failure to adhere
to this requirement causes NOR & NAND memory data bus contention.
(2) GPIO Expander (U57) connections to "Board Signal" nets are intended to provide a "read-only" feature to determine boot image
source (NOR or NAND). Boot image selection must be set before power on sequence by setting DIP Switches SW2 and SW3
along with SW5.P1 and .P2 appropriately, as shown above.
Table 11. Board Controls for Signaling and Operational Modes
Signals
Description
MCASP1_ENn
Low = Enable COMx signal paths
FORCE_EMU
Always set low
PCI_RESET_SEL
High = PCIe device may reset
Low = May reset the PCIe device
GPMC_WPN
Low = Enable write protection of NAND Flash
I2C_EEPROM_WP
High = Enable write protection of Board identification
EEPROM
PMIC_BOOT1
Low = Always, pull-down resistor
PMIC_BOOT0
ON = High = Double Reset Pulse Mode
(Rev E and older only)
OFF = Low = Power-up seq and voltages (Single reset
pulse)
PMIC_BOOT0
ON = Low = Power-up seq and voltages (Single reset
(Rev G+ Board only)
pulse)
OFF = High = Double Reset Pulse Mode
GPIO_PWR_MUX
ON = High = Connect PMIC GPIOs as follows:
(Rev E and older only)
OFF = Low = Connect PMIC GPIOs as follows:
AIC _I2C_ ADDR_CTL
ON = High = i2C – 0X19 (for AIC operation with 10.1"
(SW8.2 reused in Rev G+,
display support)
boards for AIC I2C address
OFF = Low = I2C=0X18 (for AIC operation with 7"
selection)
display support)
SPRUI50 – February 2016
Submit Documentation Feedback
Table 10. Board Controls for Booting Options
• GPIO_4 = EVM_3V3_SW power load switch
enable
• GPIO_6 = 1V35_DDR power converter enable
• GPIO_4 = 1V35_DDR power converter enable
• GPIO_6 = EVM_3V3_SW power load switch
enable
Copyright © 2016, Texas Instruments Incorporated
DIP Switch
Factory Settings
SW5.1
OFF
SW5.2
OFF
SW5.3
OFF
SW5.4
OFF
SW5.5
ON
DIP Switch
Settings
SW5.6
SW5.7
SW5.8
SW5.9
SW5.10
NA
SW8.1
SW8.1
SW8.2
SW8.2
Hardware
I2C1 GPIO
Expander
U57.P10
U57.P11
U57.P12
U57.P13
U57.P14
Factory
I2C1 GPIO
Expander
OFF
U57.P15
OFF
U57.P17
OFF
NA
OFF
NA
OFF
NA
NA
NA
ON
NA
ON
NA
OFF
NA
ON
NA
DRA7x EVM CPU Board
13
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