Control Data Cyber 170 State Hardware Reference Manual page 64

Central Memory Controls
Central Memory Controls
The CM contains six two-position configuration switches (figure 3-3). These
switches are located along the address interface pak switch in the A section of
the memory cabinet.
The switches are used to eliminate CM sections with malfunctions.
Each switch,
SWO
through SW5, inverts the corresponding CM address bit (37 through 42).
The
inversion effectively moves blocks of bad memory to the highest memory block
and moves blocks of good memory down, thereby providing a sequentially
addressable block of error-free memory.
Refer to table 3-3.
In case of CM malfunctions, the remaining good memory can be reconfigured so
it
is accessible by contiguous addresses from zero to the maximum remaining
address. This is accomplished by setting configuration switches (figure 3 - 3 )
as listed in table 3-3.
Refer to the hardware operator's guide listed in the
preface for further information.
t
INV
"TM
ADRS
6
ADRS
i i
ADRS
6
ADRS
6
ADRS
6
ADRS
42
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Figure 3-3. CM Configuration Switches