Control Data Cyber 170 State Hardware Reference Manual page 143

PP LoadlStore
Instructions
Store
Store
R
register
SRD d
Figure 4-4 shows
R
register format. I f
d is not equal to 0, this instruction
stores the upper 10 bits of the
R
register (bits 1 8 through 27) into the
righrmost 10 bits of
PP memory location d. The 12 bits contained In PP memory
location d plus 1 are stored into the next 12 bits of the R register (bits 6
through 1 7 ) . If d equals 0, the instruction is
a
pass.
34d Store (d) STD d
This instruction stores the lower
12
bits of the A register at location d.
44d Store ( ( d l ) ST1 d
This instruction stores the lower 12 bits of the
A
register at the Location
specified by the content of location d .
54dm
Store (m
+
( d ) )
STM m,d
This instruction stores the lower 12 bits of the
A register in the location
determined by indexed direct addressing.
In indexed direct addressing, the quantity m, which is read from PPM location P
plus
1,
serves as the base operand address to which the content of d 1s added.
If d equals
0,
the operand address is m, but if d is not equal to 0, m plus the
content in d is the operand address. Therefore, location d may be used as an
index quantity to modify operand addresses.