Control Data Cyber 170 State Hardware Reference Manual page 45

Execution Section
Execution Section
The execution section combines the operands into results, providing additional
sequencing control where necessary.
Cache Memory
Cache memory is a high-speed buffer memory that is transparent to the user. It
reduces effective CM access time by eliminating unnecessary CM references.
When the CP first reads CM, a block of 4
words from CM (containing the
requested word) is read rapidly into cache memory. These words may be instruc-
tions or data.
On
subsequent reading of any of these words, CM does not have
to be accessed when these words are in cache memory. Often this is the case
because the same data is read more than once or because a loop
o f
instructions
is repeatedly executed. Cache memory is 2048 words or, optionally, 4096 words.
Addressing Section
An addreas adder calculates memory addresses for data and unconditional jump
instructions.
Memory management hardware verifies that memory addresses are to access
permitted memory areas. If this is the case, this hardware accesses cache
memory and, if necessary, central memory.
Central Memory Control
Central memory control (CMC) provides an interface to CM for the CP and IOU.
It is physically located in the CP cabinet. CMC includes:
0
Ports and distributor.
SECDED logic.
Partial-write Logic.
0
Memory control logic.
Maintenance registers.