Control Data Cyber 170 State Hardware Reference Manual page 141

PP LoadlStore Instructions
Load
Load d LDN d
This instruction clears the A register and loads d. The upper 12 bits of A
are 0.
Load complement d LCN d
This instruction clears the A-register and loads the complement of d.
The
upper 12 bits of A are 1 .
2Odm Load dm LDC dm
This instruction clears the A register and loads an 18-bit quantity consisting
of d as the upper 6 bits and m as the lower 12 bits.
The content of the
location (P plus 1 ) which follows the present program address (I?) is read to
provide m .
Load
R
register
LRD d
Figure
4-4
shows B register format. If d is not equal to 0, this instruction
loads the upper 10 bits of the R register (bits 18-27) from the rightmost 10
bits of PP memory location d. The 12 bits contained in PP memory location
d
plus 1 are loaded into the next 12 bits of the R register (bits 6 through 17).
If d equals 0, the instruction is a pass.