Control Data Cyber 170 State Hardware Reference Manual page 161

PP Central Memory Access Instructions
PP Central Memory Access Instructions
The PP central memory access instructions (table 4-21) provide the capability
to read and mite CM words to and from PP memory. The PPs have read access to
all CM storage locations, while the OS bounds register controls write and
exchange accesses. The IOU performs CM addressing with real memory word
addresses. To address all locations in the larger CM sizes available, the IOU
uses address relocation to modify the CM address in the A register of the PP.
If bit 46 in A is 1 during a PP central memory read or write instruction, the
IOU adds the R register contents to A register bits 47 through 63 to produce
the CM address. If bit 46 of A Is 0, the IOU does not perform address
relocation but uses the A address. The R register contains an absolute 64-word
starting boundary within CM. When relocation is desired, an absolute CM
address is formed by concatenating six 0's to the rightmost end of the R
contents and adding bits 47 through 63 of A.
Table 4-21. PP Central Memory Access Instructions
Opcode Format Instruction Mnemonic
60 d Central read from (A) to d CRD
d
61 dm Central read ( d )
words from (A) to m
CRM m,d
62 d Central write to
(A)
from d
CUD d
63 dm Central write (d) words to (A) from m CWM m,d
Central Read
Central read from (A) to
d
CRD d
This instruction disassembles one 60-bit word from central memory into five
12-bit words and stores these in five consecutive PP memory locations,
beginning with the leftmost 12 bits of the 60-bit word.
The parameters of the transfer are as follows: If bit 17 of A is 0, A bits
0
through 16 contain the absolute address of the 60-bit word transferred. If bit
17 of
A is 1, hardware adds relocation register R to zero-extended
A bits 0
through 16 to obtain the absolute address of the 60-bit word transferred. For
further information, refer to R Register under ~nput/~utput Unit in chapter 2,
and PP Relocation Register Format at the beginning of this section on PP
Instruction Descriptions. Field d gives the PP location that receives the
first 12-bit word transferred. PP memory addressing
is
cyclic, and location
0000 follows location 7777.