Control Data Cyber 170 State Hardware Reference Manual page 47

Central Memory
The following l i s t d e f i n e s t h e a d d r e s s f i e l d s f o r f i g u r e
2-2.
Quadrant s e l e c t s p e c i f i e s one of f o u r quadrants ( a r r a y packs) w i t h i n
a
bank.
Chip s e l e c t , i f s e t , enables t h e row a d d r e s s s e l e c t t o t h e upper h a l f ( 7 2 0 )
of t h e 144 c h i p s on memory boards i n a l l e i g h t memory banks. I f c l e a r ,
c h i p enable enables t h e lower h a l f of t h e 144 chips on memory boards i n all
e i g h t banks.
Chip a d d r e s s , which comprises column a d d r e s s s e l e c t and row a d d r e s s s e l e c t ,
s p e c i f i e s t h e a d d r e s s of
1
word on a c h i p f o r t h e s e l e c t e d bank and
quadrant.
Row address s e l e c t s p e c i f i e s t h e row-select p o r t i o n of t h e c h i p a d d r e s s on
a chip.
Column a d d r e s s s e l e c t s p e c i f i e s t h e column-select p o r t i o n of t h e c h i p
a d d r e s s on a chip.
Bank s e l e c t s p e c i f i e s one of e i g h t banks.
CM Access and Cycle Times
The following paragraphs l i s t CM a c c e s s and c y c l e
times
t h a t o p e r a t e on an
i n t e r n a l clock period of 64 n s (major c y c l e ) .
The
CM a c c e s s time f o r a read o p e r a t i o n i s
320 ns ( f i v e major c y c l e s ) .
One bank c y c l e f o r a read o r w r i t e o p e r a t i o n i s 384 ns ( s i x major c y c l e s ) .
Cycle time f o r
a
p a r t i a l w r i t e (read/modify/write) i s 768 n s
(12
major c y c l e s ) .