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BQ77307
SLUSF60 – DECEMBER 2023
SCL
A7 A6
SDA
Start
When enabled, the CRC for a read transaction is calculated as follows:
•
Note that the CRC is reset after each data byte and after each stop.
•
In a single-byte read transaction using a repeated start, the CRC is calculated beginning at the first start, so
will include the target address, the register address, then the target address with read bit set, then the data
byte.
•
In a single-byte read transaction using a stop after the initial register address, the CRC is reset after the stop,
so will only include the target address with read bit set and the data byte.
•
In a block read transaction using repeated starts, the CRC for the first data byte is calculated beginning at the
first start and will include the target address, the register address, then the target address with read bit set,
then the data byte. The CRC for subsequent data bytes is calculated over the data byte only.
•
In a block read transaction using a stop after the initial register address, the CRC is reset after the stop, so
will only include the target address with read bit set and the first data byte. The CRC for subsequent data
bytes is calculated over the data byte only.
The CRC polynomial is x
When the controller detects an invalid CRC, the I
go to an idle state.
For more information, see the
7.5 Protection Subsystem
7.5.1 Protections Overview
The BQ77307 integrates an extensive primary protection subsystem which can monitor a variety of parameters,
initiate protective actions, and autonomously recover based on conditions. The device also includes a wide
range of flexibility, such that the device can be configured to monitor and initiate protective action, but
with recovery controlled by the host processor, or such that the device only monitors and alerts the host
processor whenever conditions warrant protective action, but with action and recovery fully controlled by the host
processor.
The protection subsystem includes a suite of individual protections which can be individually enabled and
configured, including cell undervoltage and overvoltage, overcurrent in charge, two separate overcurrent in
discharge protections, short circuit current in discharge, cell overtemperature and undertemperature in charge
and discharge, internal die overtemperature, and a host processor communication watchdog timeout (for
systems that expect a host processor to remain active). The device integrates NFET drivers for low-side CHG
and DSG protection FETs, which can be configured in a series or parallel configuration, and provides body diode
protection when in series configuration.
7.5.2 Primary Protections
The BQ77307 integrates a broad suite of protections for battery management and provides the capability to
enable individual protections, as well as to select which protections will result in autonomous control of the FETs.
24
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...
A1
R7
R6
R/W
ACK
Target
Target
Register
Address
Address
Address
2
Figure 7-4. I
C Read Without Repeated Start
8
2
+ x
+ x + 1, and the initial value is 0.
2
BQ77307 Technical Reference
Product Folder Links:
...
R0
A7 A6
ACK
Stop Start
...
D7 D6
D0
ACK
Target
Drives Data
C controller will NACK the CRC, which causes the I
Manual.
BQ77307
...
A1
R/W
ACK
Target
Address
...
C7 C6
C0
NACK
Target
Stop
Drives CRC
(optional )
Controller
Drives NACK
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
2
C target to
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