Table of Contents
Advertisement
E331.E2501.061.21.02.02
System SIRECUST 1280/1281
Bedside Monitor - Service Manual
05
Da
i
£8000
00
+
0
CHAN A CC WORDS
1ST
PING"
E
2
48 100
CHAN B CC WORDS
SUB CHANNEL| 18 上 一 一 一 一 一 一 一
6
=
48200
CONVERSIONS
PONG"
3
£
CHAN © Œ WORDS
1.5.9...93
A
2
48300
30
C
:
CHAN
D CC WORDS
UNUSED
E
o
48400
、
o
9
=
~
77 シン
2 NO
"PİNG"
16
:
SUB CHANNEL]
eg llo
e
UNUSED
CONVERSION
.
.
18
3,7,11...95
PONG
i
Vz
ン ノ
70
1€
UNUSED
1E
48 800
L
80
20
=
4a 900
CHAN
A
DATA
3RD
"PING"
2
E
CHAN
B
DATA
SUB CHANNEL]
oof
ll
各
2
LS À 00
CONVERSIONS
_
_
28
>
CHAN
C
DATA
2.6.10...94
PONG
a
z
48 600
Bo
2C
a
CHAN
D
DATA
UNUSE D
ZE
3
48 (00
co
30
]
HAN
A
AUX
-
"
L8 D00
«тн
|
PING
CHAN
6
AUX
SUB CHANNEL!
D8 Joa a
o o e
48 E 00
CONVERSIO
"PONG ©
CHAN
C
AUX
4,812... 96
48 F00
FO
CHAN
D AUX
UNUSED
3€
49 000
FE
Lo
Figure 3-3.
Channel Conversion Memory Map
3.2.3.
SIREM Power Control
A current detector and timer circuit allows
parameter
cartridges
to be
plugged
in
with power ON and protects against short
circuits.
The
current
trip
is
set
for
approximately
1.7
amps.
The
timer
prevents damage to the power transistor
in an
overcurrent
condition
by
turning
power ON for approximately 100 ms and
OFF for approximately six seconds.
3.3.
Display Processor
The Display Processor and Memory
Ex-
tension
Boards
provide
the
main
data
handling
capability in the monitor.
See
Figure 3-5 and also the schematic dia-
grams in Appendix B, Pgs. B-3 thru B-6.
The
Display
Processor
combines
the
68000 MAIN CPU, J11, with the graphic
controller, J32, for the raster display. The
68000 CPU has an internal BUS as well
as an interface to an external BUS on the
Motherboard. A171/A371
Display Proces-
sor Boards have up to 128K X 16 bits of
ROM, 32K X 16 bits of SRAM, and 2K X
8 bits of EPROM, depending on needs of
the
software
version
installed
in
the
monitor. A372 Display Processor Boards
can have up to 512K X 16 bits of ROM,
128K X 16 bits of static RAM, and 8K X
8 bits of EEPROM.
The data BUS
is 16 bits wide and the
address
BUS
is 24 bits wide.
At the
beginning of each BUS cycle the address
decoder determines whether the cycle is
internal on the board or external to the
Motherboard.
All devices shown on the
block diagram are on the internal BUS.
If
the BUS cycle is an external request, the
request is entered into the arbiter. During
external
cycles
the
address
lines
are
buffered from the internal BUS and the
data
BUS
is buffered
for write
cycles.
During
read
cycles
the
data
BUS
is
latched and the external BUS is released
while the 68000 finishes its cycle.
Page 3 - 4
X
Advertisement
Chapters
Table of Contents
