Table of Contents
Advertisement
E331 .E2501.061.21.02.02
System SIRECUST 1280/1281
Bedside Monitor - Service Manual
3.2.
Front End
Board
The Front End Board contains circuitry for
data collection and control of the physio-
logical parameter cartridges via SIREMs.
It generates the time clocks for data ex-
change between the SIREMs and the Dis-
play Processor,
and converts the serial
data streams from the SIREMs into paral-
lel data streams. It is also the interface for
the
+15 Voc needed by the SIREM
to
power cartridges. Refer to Figure 3-4 and
the schematic diagram in Appendix B.
The four main
sections
of the board
are:
¢ dual access RAM (D-RAM) (J57, J59,
J68, J69) for storage and retrieval of
data from the parameter cartridges,
* logic and timing generation circuits
for
parameter
cartridge
communication,
* parameter cartridge power control,
+ additional static RAM (J43, J44) and
EPROMs
J17,
J18,
J33,
and
J34,
(see NOTE:) for the main CPU.
NOTE:
Software
versions
up
to
and
.
including
VCx
use
EPROMS
on
A190
Rev.1 and Rev 2. Front End Boards, Art.
No.
87
91
378
E2501.
For
software
versions VEx
and subsequent
versions,
EPROMS
in positions J17, J18, J33, and
J34
on
the
Memory
Extension
Board
supplant
use of EPROMS
on the Front
End Board. 'See Section 3.16.
3.2.1.
PROM/RAM
Interface
The PROM/RAM interface consists of a 2K
x 8 bit static RAM and 16 Kbytes of dual
access D-RAM. The D-RAM is configured
for dual access using the system address
bus
and
the bus
arbiter located
on the
Display Processor Board. D-RAM is used
for storage
of configuration
codes
for
transmitting
to the
parameter
cartridges
and for storage of auxiliary and data bits
received from the cartridges.
The PROM
and SRAM
are accessed by
the system BUS, whereas D-RAM may be
accessed
by the either the system
BUS
or by internal logic. Access to PROM and
SRAM
is controlled
by an
address
de-
coder
and timer. Access
to D-RAM
by
internal circuits is gained by arbiting for
the system
BUS for address access to
D-RAM. When D-RAM is accessed by in-
ternal logic, the data is passed
on the
internal data BUS (D100-D115) while the
system data BUS is disabled.
3.2.2.
Parameter Cartridge Timing
Timing
is synchronized
to the
50
Hz
DISPLAY field rate by the field bit signal.
Parameter cartridge timing generation can
be divided into three basic sections:
* a prescaler which divides the 4 MHZ
clock
to
generate
the
six
micro-
second clock needed by cartridges,
* a conversion timing generator which
generates all the timing associated
with each conversion, and
* the conversion
address
counter.
Operation of a parameter cartridge is con-
trolled
by
configuration
control
words
CCA-CCD, and by control bits U/LA-U/LD
which direct the CC words to the upper
or lower cartridge pairs.
The CC words
and U/L control bits are read from prede-
termined
locations
in the
D-RAM
and
transmitted to the appropriate cartridge.
Data
and
Aux
words
are
received
and
stored
in
predetermined
locations
in
D-RAM. Each 20 ms period is divided into
96 conversions of 208.25 us each.
The
96 conversions are mapped
into D-RAM
according
to
the
channel
conversion
memory map. "Ping," "Pong," and memory
mapping:
assure
synchronous
software
access to the data.
Refer to the Front*
End
Board
memory
map
in Figure 3-3.
The serial CC and data/aux bit streams
are transmitted to and received from the
SIREMs
using
differential
drivers
and
receivers.
Page 3 - 3
Advertisement
Chapters
Table of Contents
