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Analyzer Problems
This section lists general problems that you might encounter while
using the analyzer.
Intermittent data errors
This problem is usually caused by poor connections, incorrect signal levels, or
marginal timing.
D Remove and reseat all cables and probes, ensuring that there are no
bent pins on the preprocessor interface or poor probe connections.
D Adjust the threshold level of the data pod to match the logic levels
in
the
system under test.
D Use an oscilloscope to check the signal integrity of the data lines.
Clock signals for the state analyzer must meet particular pulse shape and
timing requirements. Data inputs for the analyzer must meet pulse shape and
setup and hold time requirements.
See "Capacitive Loading" in this chapter for information on other sources of
intermittent data errors.
Unwanted triggers
Unwanted triggers can be caused by instructions that were fetched but not
executed.
D Add the prefetch queue or pipeline depth
to
the trigger address to avoid
this problem.
The logic analyzer captures pref etches, even
if
they are not executed. When
you are specifying a trigger condition or a storage qualification that follows an
instruction that may cause branching, an unused prefetch may generate an
unwanted trigger.
E2465A PowerPC 604 PGA Preprocessor Interface
A-3
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