HP E2465A PowerPC 604 PGA User Manual page 31

Analyzing the PowerPC 604
Format Menu
Status Bit Description
Status Bit
BR
BG
ABB
TS
XATS
DBG
DBWO
DBB
AACK
ARTRY
TA
DRTRY
TEA
TT0:4
R/W
(ID)
2-6
Description
The PowerPC 604 asserts Bus Request to indicate that it has
business to conduct on the address bus.
The memory system asserts Bus Grant to allow the 604 onto
the address bus.
Address Bus Busy indicates thatthe address bus is in use.
The PowerPC 604 asserts TS for one cycle to commence a
transaction. It also serves as the data bus request signal if
then signals indicate a data transfer.
XATS commences a "programmed i/o" (PIO) sequence in the
extended address transfer protocol.
The memory system asserts Data Bus Grant to allow the 604
onto the data bus.
The memory system may assert Data Bus Write Only to allow
the 604 to envelope a data write (snoop push, typically)
between the address and data phases of a data read.
Indicates Data Bus Busy.
The memory system asserts AACK for one cycle to
acknowledge an address.
The memory system may assert ARTRY to cause the 604 to
back off the bus and retry the transaction.
The memory system asserts TA to acknowledge a data
transaction.
The memory system may assert DRTRY to cancel the effect of
a TA in the previous cycle.
The memory system may assert TEA to indicate a transfer
error, e.g. an unmapped part of the address space.
The Transfer Type signals indicate the direction and purpose
of a bus transaction.
TI1 is high for a read, low for a write.
E2465A PowerPC 604 PGA Preprocessor