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Overfetch Marking
Analyzing the PowerPC 604
Using the Inverse Assembler
Overfetch refers to instructions which are fetched but not executed by the
processor. They may arise from the following sources:
• When bursting, the 604 first fetches the critical doubleword of an
eight-word cache line. The memory system then provides succeeding
doublewords.
If
the critical doubleword was not the first doubleword of
the line, the memory system wraps at the line boundary to the first
doubleword. Doublewords fetched after the line wrap are not in the
sequential execution path and are marked with an asterisk
"*".
• When the 604 executes a branch instruction, the instructions between the
branch and the branch target are not executed. These instructions are
indicated with a hyphen"-", or
if
the bus trace is ambiguous, with an
interrogation point"?".
If
the instruction cache is enabled, the branch
target may already be in the cache and
will
not be fetched over the bus.
The remaining cache line containing the branch
will
be marked as
overfetch.
An exception to the above includes branches with the link bit set, that record
the next instruction address in the
link
register ("lr"). Frequently, these are
subroutine branches which
will
return to the instructions following the
branch. These branch-and-link instructions are indicated by a">".
For conditional branches whose target addresses are not known, or are
known but not seen in the bus traffic, the inverse assembler cannot always
determine if the branch was taken and will not mark ensuing states as
overfetch.
Little-Endian Mode
The inverse assembler is designed to support the native big-endian mode of
operation on the PowerPC 604. When operating in little-endian mode, the
604 uses a technique known as "address munging" to convert internal little-
endian addresses into external big-endian addresses. Internal and external
addresses may differ from one another in the three least significant bits.
In little-endian operation, in a given data beat, the instruction word from
DL0 .. 31 (DATA_B label; external address xxx4) will be dispatched before the
instruction word from DH0 .. 31 (DATA label; external address
xxxO).
You can
compensate for this by exchanging the DATA and DATA_B labels in the
Format menu. However, while this
will
correctly order 32-bit word reads on
the 64-bit data bus, it
will
cause byte- and half- word reads and writes to
appear on the opposite side of the bus, and swap the halves of double-word
reads and writes.
E2465A PowerPC 604 PGA Preprocessor
2-17
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