To Display Captured State Data - HP E2465A PowerPC 604 PGA User Manual

Analyzing the Power PC 604
Using the Inverse Assembler
To display captured state data
• Select the Listing Menu for your logic analyzer.
The logic analyzer displays captured state data in the Listing Menu. The
inverse assembler display is obtained by setting the base for the DATA label
to Invasm. The following figure shows the Listing Menu as configured on the
HP 16550A.
( 100/500MHz LA B) ( Listing 1
)
(
Invasm
)~
(
Run
Markers Acquisition Time
Off
25 Apr 1996 14:56:31
La be 1 >
I
ADDR
11
604 DATA Bus
11
acks
I
[2]
Base>
I
Hex
lllO=hex
10.=decimal %10=binary
k9
I I
Symbol
I~
206 FFFC0007 506 mfspr rO 1 r TA R
5DC > b 1 FFF065EO
209 FFF065EO
wait AACK
R
210 FFFC0007 5EO mfspr r3 1 r TA R
5E4 ad di r4 r3 0000
211 FFF065E8
wait AACK R
212 FFFC0007 5E6 addi
r-*
r4 0020 TA R
5EC lwz r4 0000Cr4l
213 FFF065FO
wait
AACK R
214 FFFC0007 5FO subi r3 r3 0006 TA R
5F4 add r3 r3 r4
215 FFF065F8
Wait
AACK R
216 FFFC0007 5FB mtspr 1 r rO TA R
5FC b 1 r
217 FFF06600 Wait AACK R
216
FFF06600 600 -f sub?
f31 f31 f 19 TA R
The columns on the left of the inverse assembly data display are the least
significant hexadecimal digits of an instruction or burst address. These may
be useful for matching an execution trace to an assembly listing. Because the
PowerPC 604 presents one address and then reads two or eight instructions
for each address, the less-significant bits are synthesized by the
disassembler. On the HP 16505A Prototype Analyzer, the entire synthesized
address appears under the label "PC". The actual address bits presented by
the PowerPC 604 may be observed under the ADDR label.
The fourth column may contain an underscore "-", which indicates a break in
the sequential flow of instruction addresses.
The fifth column displays overfetch and branch-and-link indicators as
described in the overfetch marking section on page 2-17. The remaining
disassembly listing resembles an assembly listing.
E2465A PowerPC 604 PGA Preprocessor 2-15