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Analyzing the PowerPC 604
Using the Inverse Assembler
Interpreting Data
General purpose registers are displayed as rO, rl, ... , r31. Floating point
registers are displayed as fO, fl, .. ., f31. Condition registers are displayed as
crO, crl, .. ., cr7. Special purpose registers are displayed using their
mnemonic.
Most numerical data is displayed in hexadecimal, e.g., "lwz
r28 0044(rl)."
Bit numbers and shift counts are displayed in decimal with a dot suffix, e.g.,
"cror 31. 31. 31."
A few instructions display their operands in binary with a "%" prefix, e.g.,
"mtfsfi 4 %0101."
The disassembler decodes the full PowerPC instruction set architecture,
including 64-bit mode instructions and optional instructions not implemented
on the 604. When these unimplemented opcodes are encountered, the
instruction mnemonic has a "?" prefix.
If
a reserved bit is set in an instruction
opcode field, a "?" is appended most often to the mnemonic, but in some
cases to an operand.
An
instruction word of 00000000 is decoded as "illegal." Otherwise,
if
an
opcode is invalid, it is shown as "Undefined Opcode".
Branch Instructions
lf
the address of a branch relative instruction is known, its target is presented
as an absolute hex address (or as a symbol
if
it matches an ADDR pattern or
range symbol).
If
the address of a branch relative instruction is not known, its
target is displayed as a hexadecimal offset such as +OOOOOC30 or -00000048.
lf
a branch hint is encoded, a"+" (for predicted taken) or a"-" (for predicted
not taken) is appended to the conditional branch mnemonic.
2-16
E2465A PowerPC 604 PGA Preprocessor
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