GigaDevice Semiconductor GD32E508 Series Manuals

Manuals and User Guides for GigaDevice Semiconductor GD32E508 Series. We have 2 GigaDevice Semiconductor GD32E508 Series manuals available for free PDF download: User Manual

GigaDevice Semiconductor GD32E508 Series User Manual (1245 pages)

Arm Cortex-M33 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 17 MB

Table of Contents
2
List of Figures
21
List of Tables
31
System and Memory Architecture
36
Arm ® Cortex ® -M33 Processor
36
Figure 1-1. the Structure of the Cortex ® -M33 Processor
36
System Architecture
37
Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix
37
Memory Map
39
Figure 1-2. Gd32E50X System Architecture
39
Table 1-2. Memory Map of Gd32E50X Devices
40
On-Chip SRAM Memory
43
On-Chip Flash Memory Overview
43
Boot Configuration
44
Device Electronic Signature
44
Table 1-3. Boot Modes
44
Memory Density Information
45
Unique Device ID (96 Bits)
45
System Configuration Registers
46
Flash Memory Controller (FMC)
47
Overview
47
Characteristics
47
Function Overview
47
Flash Memory Architecture
47
Table 2-1. Gd32E50X_Hd and Gd32E50X_Cl Base Address and Size for Flash Memory
47
Read Operations
48
Table 2-2. the Relation between WSCNT and AHB Clock Frequency
48
Unlock the FMC_CTL Register
49
Page Erase
50
Mass Erase
51
Figure 2-1. Process of Page Erase Operation
51
Main Flash Programming
52
Figure 2-2. Process of Mass Erase Operation
52
OTP Programming
54
Option Bytes Erase
54
Figure 2-3. Process of Word Program Operation
54
Option Bytes Modify
55
Option Bytes Description
55
Table 2-3. Option Bytes
56
Page Erase / Program Protection
57
Security Protection
57
Table 2-4. OB_WP Bit for Pages Protected
57
Register Definition
58
Wait State Register (FMC_WS)
58
Unlock Key Register (FMC_KEY)
59
Option Byte Unlock Key Register (FMC_OBKEY)
59
Status Register (FMC_STAT)
60
Control Register (FMC_CTL)
61
Address Register (FMC_ADDR)
62
Option Byte Status Register (FMC_OBSTAT)
62
Erase/Program Protection Register (FMC_WP)
63
Product ID Register (FMC_PID)
63
Backup Registers (BKP)
65
Overview
65
Characteristics
65
Function Overview
65
RTC Clock Calibration
65
Tamper Detection
65
Register Definition
67
Backup Data Register X (Bkp_Datax) (X= 0
67
RTC Signal Output Control Register (BKP_OCTL)
67
Tamper Pin Control Register (BKP_TPCTL)
68
Tamper Control and Status Register (BKP_TPCS)
69
Power Management Unit (PMU)
70
Overview
70
Characteristics
70
Function Overview
70
Figure 4-1. Power Supply Overview
70
Backup Domain
71
VDD / V Dda
72
Figure 4-2. Waveform of the por / PDR
72
Figure 4-3. Waveform of the BOR
73
Figure 4-4. Waveform of the LVD Threshold
74
1.1V Power Domain
75
Power Saving Modes
75
Table 4-1. Power Saving Mode Summary
78
Register Definition
80
Control Register 0 (PMU_CTL0)
80
Control and Status Register 0 (PMU_CS0)
82
Control Register 1 (PMU_CTL1)
84
Control and Status Register 1 (PMU_CS1)
85
Reset and Clock Unit (RCU)
86
High Density Reset and Clock Control Unit (RCU)
86
Reset Control Unit (RCTL)
86
Overview
86
Function Overview
86
Clock Control Unit (CCTL)
87
Overview
87
Figure 5-1. the System Reset Circuit
87
Figure 5-2. Clock Tree
88
Characteristics
89
Function Overview
89
Figure 5-3. HXTAL Clock Source
90
Figure 5-4. HXTAL Clock Source in Bypass Mode
90
Table 5-1. Clock Output 0 Source Select
93
Table 5-2. 1.1V Domain Voltage Selected in Deep-Sleep Mode
93
Register Definition
94
Control Register (RCU_CTL)
94
Clock Configuration Register 0 (RCU_CFG0)
95
Clock Interrupt Register (RCU_INT)
99
APB2 Reset Register (RCU_APB2RST)
101
APB1 Reset Register (RCU_APB1RST)
104
AHB Enable Register (RCU_AHBEN)
107
APB2 Enable Register (RCU_APB2EN)
108
APB1 Enable Register (RCU_APB1EN)
111
Backup Domain Control Register (RCU_BDCTL)
114
Reset Source/Clock Register (RCU_RSTSCK)
115
AHB Reset Register (RCU_AHBRST)
117
Clock Configuration Register 1 (RCU_CFG1)
118
Deep-Sleep Mode Voltage Register (RCU_DSV)
118
Additional Clock Control Register (RCU_ADDCTL)
119
Additional Clock Interrupt Register (RCU_ADDINT)
120
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)
120
Clock Configuration Register 2 (RCU_CFG2)
121
APB1 Additional Reset Register (RCU_ADDAPB1RST)
122
APB1 Additional Enable Register (RCU_ADDAPB1EN)
122
Connectivity Line Devices: Reset and Clock Control Unit (RCU)
124
Reset Control Unit (RCTL)
124
Overview
124
Function Overview
124
Clock Control Unit (CCTL)
125
Overview
125
Figure 5-5. the System Reset Circuit
125
Figure 5-6. Clock Tree
126
Characteristics
127
Function Overview
128
Figure 5-7. HXTAL Clock Source
128
Figure 5-8. HXTAL Clock Source in Bypass Mode
128
Table 5-3. Clock Output 0 Source Select
131
Table 5-4. 1.1V Domain Voltage Selected in Deep-Sleep Mode
132
Register Definition
133
Control Register (RCU_CTL)
133
Clock Configuration Register 0 (RCU_CFG0)
135
Clock Interrupt Register (RCU_INT)
138
APB2 Reset Register (RCU_APB2RST)
142
APB1 Reset Register (RCU_APB1RST)
144
AHB Enable Register (RCU_AHBEN)
147
APB2 Enable Register (RCU_APB2EN)
149
APB1 Enable Register (RCU_APB1EN)
152
Backup Domain Control Register (RCU_BDCTL)
155
Reset Source/Clock Register (RCU_RSTSCK)
156
AHB Reset Register (RCU_AHBRST)
158
Clock Configuration Register 1 (RCU_CFG1)
159
Deep-Sleep Mode Voltage Register (RCU_DSV)
162
Additional Clock Control Register (RCU_ADDCTL)
162
Additional Clock Configuration Register (RCU_ADDCFG)
164
Additional Clock Interrupt Register (RCU_ADDINT)
165
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)
166
Clock Configuration Register 2 (RCU_CFG2)
167
APB1 Additional Reset Register (RCU_ADDAPB1RST)
168
APB1 Additional Enable Register (RCU_ADDAPB1EN)
168
Clock Trim Controller (CTC)
170
Overview
170
Characteristics
170
Function Overview
170
Figure 6-1. CTC Overview
170
REF Sync Pulse Generator
171
CTC Trim Counter
171
Frequency Evaluation and Automatically Trim Process
172
Figure 6-2. CTC Trim Counter
172
Software Program Guide
173
Register Definition
175
Control Register 0 (CTC_CTL0)
175
Control Register 1 (CTC_CTL1)
176
Status Register (CTC_STAT)
177
Interrupt Clear Register (CTC_INTC)
179
Interrupt/Event Controller (EXTI)
181
Overview
181
Characteristics
181
Interrupts Function Overview
181
Table 7-1. NVIC Exception Types in Cortex ® -M33
182
Table 7-2. Interrupt Vector Table
182
External Interrupt and Event (EXTI) Block Diagram
186
External Interrupt and Event Function Overview
186
Figure 7-1. Block Diagram of EXTI
186
Table 7-3. EXTI Source
186
EXTI Register
189
Interrupt Enable Register (EXTI_INTEN)
189
Event Enable Register (EXTI_EVEN)
189
Rising Edge Trigger Enable Register (EXTI_RTEN)
190
Falling Edge Trigger Enable Register (EXTI_FTEN)
190
Software Interrupt Event Register (EXTI_SWIEV)
190
Pending Register (EXTI_PD)
191
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
192
Overview
192
Characteristics
192
Function Overview
192
GPIO Pin Configuration
193
Figure 8-1. Basic Structure of a General-Pupose I/O
193
Table 8-1. GPIO Configuration Table
193
External Interrupt/Event Lines
194
Alternate Functions (AF)
194
Input Configuration
194
Figure 8-2. Basic Structure of Input Configuration
194
Output Configuration
195
Analog Configuration
195
Figure 8-3. Basic Structure of Output Configuration
195
Figure 8-4. Basic Structure of Analog Configuration
195
Alternate Function (AF) Configuration
196
IO Pin Function Selection
196
Figure 8-5. Basic Structure of Alternate Function Configuration
196
GPIO Locking Function
197
GPIO I/O Compensation Cell
197
Remapping Function I/O and Debug Configuration
197
Introduction
197
Main Features
197
JTAG/SWD Alternate Function Remapping
198
ADC AF Remapping
198
Table 8-2. Debug Interface Signals
198
Table 8-3. Debug Port Mapping and Pin Availability
198
Table 8-4. ADC0/1 External Trigger Routine Conversion AF Remapping Function
198
TIMER AF Remapping
199
Table 8-5. Timerx Alternate Function Remapping
199
USART AF Remapping
200
Table 8-6. TIMER4 Alternate Function Remapping
200
Table 8-7. USART0/1/2 Alternate Function Remapping
200
I2C0 AF Remapping
201
SPI0/SPI2/I2S AF Remapping
201
Table 8-8. I2C0 Alternate Function Remapping
201
CAN0/1 AF Remapping
202
Table 8-9. SPI0/SPI2/I2S Alternate Function Remapping
202
Table 8-10. CAN0/1 Alternate Function Remapping
202
Ethernet AF Remapping
203
CTC AF Remapping
203
CLK Pins AF Remapping
203
Table 8-11. ENET Alternate Function Remapping
203
Table 8-12. CTC Alternate Function Remapping
203
Table 8-13. OSC32 Pins Configuration
203
Table 8-14. OSC Pins Configuration
203
Register Definition
205
Port Control Register 0 (Gpiox_Ctl0, X=A
205
Port Control Register 1 (Gpiox_Ctl1, X=A
207
Port Input Status Register (Gpiox_Istat, X=A
208
Port Output Control Register (Gpiox_Octl, X=A
209
Port Bit Operate Register (Gpiox_Bop , X=A
209
Port Bit Clear Register (Gpiox_Bc, X=A
210
Port Configuration Lock Register (Gpiox_Lock, X=A
210
Port Bit Speed Register (Gpiox_ SPD, X=A
211
Event Control Register (AFIO_EC)
212
AFIO Port Configuration Register 0 (AFIO_PCF0)
212
EXTI Sources Selection Register 0 (AFIO_EXTISS0)
219
EXTI Sources Selection Register 1 (AFIO_EXTISS1)
220
EXTI Sources Selection Register 2 (AFIO_EXTISS2)
221
EXTI Sources Selection Register 3 (AFIO_EXTISS3)
222
AFIO Port Configuration Register 1 (AFIO_PCF1)
224
IO Compensation Control Register (AFIO_CPSCTL)
225
AFIO Port Configuration Register a (AFIO_PCFA)
226
AFIO Port Configuration Register B (AFIO_PCFB)
228
AFIO Port Configuration Register C (AFIO_PCFC)
230
AFIO Port Configuration Register D (AFIO_PCFD)
232
AFIO Port Configuration Register E (AFIO_PCFE)
233
AFIO Port Configuration Register G (AFIO_PCFG)
234
Cyclic Redundancy Checks Management Unit (CRC)
237
Overview
237
Characteristics
237
Figure 9-1. Block Diagram of CRC Management Unit
237
Function Overview
238
Register Definition
239
Data Register (CRC_DATA)
239
Free Data Register (CRC_FDATA)
239
Control Register (CRC_CTL)
240
Initialization Data Register (CRC_IDATA)
240
Polynomial Register (CRC_POLY)
241
Trigonometric Math Unit (TMU)
242
Overview
242
Characteristics
242
Function Overview
242
TMU Block Diagram
242
Table 10-1. 9 Different Operation Modes
242
Data Format
243
Figure 10-1. Block Diagram of Trigonometric Math Unit
243
Table 10-2. IEEE 32-Bit Single Precision Floating-Point Format
243
Mode 0 Description
244
Mode 1 Description
244
Table 10-3. Convert Per-Unit Values to Radians in Mode 0
244
Table 10-4. Convert Radians Values to Per-Unit Values in Mode 1
244
Mode 2 Description
245
Mode 3 Description
245
Mode 4 Description
245
Mode 5 Description
246
Mode 6 Description
246
Table 10-5. the Range of Input Value and R0 Value in Mode 5
246
Figure 10-2. Calculation of R1 (Quadrant) and R0 (Ratio) Based on y and X Values
247
Table 10-6. the Condition of UDRF and OVRF Flag in Mode 6
247
Mode 7 Description
248
Mode 8 Description
248
Software Guideline
248
Table 10-7. the Condition of UDRF and OVRF Flag in Mode 7
248
Figure 10-3. TMU Program Guidline
249
TMU Register
250
Input Data0 Register (TMU_IDATA0)
250
Input Data1 Register (TMU_IDATA1)
250
Control Register (TMU_CTL)
251
Data0 Register (TMU_DATA0)
252
Data1 Register (TMU_DATA1)
252
Status Register (TMU_STAT)
252
Direct Memory Access Controller (DMA)
254
Overview
254
Characteristics
254
Block Diagram
255
Function Overview
255
DMA Operation
255
Figure 11-1. Block Diagram of DMA
255
Table 11-1. DMA Transfer Operation
256
Peripheral Handshake
257
Arbitration
257
Figure 11-2. Handshake Mechanism
257
Address Generation
258
Circular Mode
258
Memory to Memory Mode
258
Channel Configuration
258
Interrupt
259
DMA Request Mapping
259
Figure 11-3. DMA Interrupt Logic
259
Table 11-2. Interrupt Events
259
Figure 11-4. DMA0 Request Mapping
260
Table 11-3. DMA0 Requests for each Channel
260
Table 11-4. DMA1 Requests for each Channel
260
Figure 11-5. DMA1 Request Mapping
261
Register Definition
263
Interrupt Flag Register (DMA_INTF)
263
Interrupt Flag Clear Register (DMA_INTC)
264
Channel X Control Register (Dma_Chxctl)
264
Channel X Counter Register (Dma_Chxcnt)
266
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
267
Channel X Memory Base Address Register (Dma_Chxmaddr)
267
Debug (DBG)
269
Introduction
269
JTAG/SW Function Description
269
Switch JTAG or SW Interface
269
Pin Assignment
269
JTAG Daisy Chained Structure
270
Debug Reset
270
JEDEC-106 ID Code
270
Debug Hold Function Description
270
Debug Support for Power Saving Mode
270
Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN
271
DBG Registers
272
ID Code Register (DBG_ID)
272
Control Register (DBG_CTL)
272
Analog-To-Digital Converter (ADC)
276
Introduction
276
Characteristics
276
Pins and Internal Signals
277
Figure 13-1. ADC Module Block Diagram (for ADC0 and ADC1)
277
Table 13-1. ADC Internal Input Signals
277
Table 13-2. ADC Input Pins Definition
277
Functional Overview
278
Foreground Calibration Function
279
Figure 13-2. ADC Module Block Diagram (for ADC2)
279
ADC Clock
280
ADCON Enable
280
Single-Ended and Differential Input Channels
280
Routine Sequence
281
Operation Modes
281
Figure 13-3. Single Operation Mode
281
Figure 13-4. Continuous Operation Mode
282
Figure 13-5. Scan Operation Mode, Continuous Operation Mode Disable
283
Figure 13-6. Scan Operation Mode, Continuous Operation Mode Enable
283
Figure 13-7. Discontinuous Operation Mode
283
Conversion Result Threshold Monitor
284
Data Storage Mode
284
Figure 13-8. 12-Bit Data Storage Mode
284
Sample Time Configuration
285
External Trigger Configuration
285
Figure 13-9. 6-Bit Data Storage Mode
285
Table 13-3. External Trigger Source for ADC0 and ADC1
285
Table 13-4. External Trigger Source for ADC2
285
DMA Request
286
ADC Internal Channels
286
Programmable Resolution (DRES)
287
On-Chip Hardware Oversampling
287
Table 13-5. Tconv Timings Depending on Resolution
287
Figure 13-10. 20-Bit to 16-Bit Result Truncation
288
Figure 13-11. Numerical Example with 5-Bits Shift and Rounding
288
Table 13-6. Maximum Output Results for N and M Combimations
288
ADC Sync Mode
289
Table 13-7. ADC Sync Mode Table
289
Free Mode
290
Routine Parallel Mode
290
Figure 13-12. ADC Sync Block Diagram
290
Routine Follow-Up Fast Mode
291
Routine Follow-Up Slow Mode
291
Figure 13-13. Routine Parallel Mode on 10 Channels
291
Figure 13-14. Routine Follow-Up Fast Mode on Routine Sequence (the CTN Bit of the Adcs Are Set)
291
ADC Interrupts
292
Figure 13-15. Routine Follow-Up Slow Mode on Routine Sequence Channel
292
ADC Registers
293
Status Register (ADC_STAT)
293
Control Register 0 (ADC_CTL0)
294
Control Register 1 (ADC_CTL1)
296
Sample Time Register 0 (ADC_SAMPT0)
298
Sample Time Register 1 (ADC_SAMPT1)
299
Watchdog High Threshold Register 0 (ADC_WDHT0)
300
Watchdog Low Threshold Register 0 (ADC_WDLT0)
300
Routine Sequence Register 0 (ADC_RSQ0)
300
Routine Sequence Register 1 (ADC_RSQ1)
301
Routine Sequence Register 2 (ADC_RSQ2)
302
Routine Data Register (ADC_RDATA)
302
Oversample Control Register (ADC_OVSAMPCTL)
303
Watchdog 1 Channel Selection Register (ADC_WD1SR)
304
Watchdog 2 Channel Selection Register (ADC_WD2SR)
305
Watchdog Threshold Register 1 (ADC_WDT1)
305
Watchdog Threshold Register 2 (ADC_WDT2)
306
Differential Mode Control Register (ADC_DIFCTL)
307
Digital-To-Analog Converter (DAC)
308
Introduction
308
Main Features
308
Function Description
309
DAC Enable
309
DAC Output Buffer
309
Figure 14-1. DAC Block Diagram
309
Table 14-1. DAC I/O Description
309
DAC Data Configuration
310
DAC Trigger
310
DAC Workflow
310
Table 14-2. External Triggers of DAC
310
DAC Output FIFO
311
DAC Noise Wave
311
DAC Output Calculate
312
DMA Funtion
312
Figure 14-2. DAC LFSR Algorithm
312
Figure 14-3. DAC Triangle Noise Wave
312
DAC Concurrent Conversion
313
DAC Registers
314
Control Register 0 (DAC_CTL0)
314
Software Trigger Register (DAC_SWT)
317
DAC_OUT0 12-Bit Right-Aligned Data Holding Register (OUT0_R12DH)
317
DAC_OUT0 12-Bit Left-Aligned Data Holding Register (OUT0_L12DH)
318
DAC_OUT0 8-Bit Right-Aligned Data Holding Register (OUT0_R8DH)
318
DAC_OUT1 12-Bit Right-Aligned Data Holding Register (OUT1_R12DH)
319
DAC_OUT1 12-Bit Left-Aligned Data Holding Register (OUT1_L12DH)
319
DAC_OUT1 8-Bit Right-Aligned Data Holding Register (OUT1_R8DH)
320
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)
320
DAC Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)
321
DAC Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)
321
DAC_OUT0 Data Output Register (OUT0_DO)
322
DAC_OUT1 Data Output Register (OUT1_DO)
322
DAC Status Register 0 (DAC_STAT0)
323
DAC Control Register 1 (DAC_CTL1)
323
DAC Status Register 1 (DAC_STAT1)
324
Comparator (CMP)
326
Overview
326
Characteristic
326
Function Overview
326
CMP I/O Configuration
327
Figure 15-1. CMP Block Diagram of Gd32E50X Series
327
Table 15-1. CMP Inputs and Outputs Summary
327
CMP Output Blanking
328
CMP Register Write Protection
329
Figure 15-2. the CMP Outputs Signal Blanking
329
CMP Registers
330
CMP1 Control/Status Register (CMP1_CS)
330
CMP3 Control/Status Register (CMP3_CS)
331
CMP5 Control/Status Register (CMP5_CS)
333
Watchdog Timer (WDGT)
336
Free Watchdog Timer (FWDGT)
336
Overview
336
Characteristics
336
Function Overview
336
Figure 16-1. Free Watchdog Block Diagram
337
Table 16-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)
337
Register Definition
339
Window Watchdog Timer (WWDGT)
342
Overview
342
Characteristics
342
Function Overview
342
Figure 16-2. Window Watchdog Timer Block Diagram
342
Figure 16-3. Window Watchdog Timing Diagram
343
Table 16-2. Min/Max Timeout Value at 100 Mhz (F PCLK1 )
344
Register Definition
345
Real-Time Clock (RTC)
347
Overview
347
Characteristics
347
Function Overview
347
RTC Reset
348
RTC Reading
348
RTC Configuration
348
Figure 17-1. Block Diagram of RTC
348
RTC Flag Assertion
349
Figure 17-2. RTC Second and Alarm Waveform Example (RTC_PSC = 3, RTC_ALRM = 2)
349
Figure 17-3. RTC Second and Overflow Waveform Example (RTC_PSC= 3)
350
RTC Register
351
RTC Interrupt Enable Register (RTC_INTEN)
351
RTC Control Register (RTC_CTL)
351
RTC Prescaler High Register (RTC_PSCH)
352
RTC Prescaler Low Register (RTC_PSCL)
353
RTC Divider High Register (RTC_DIVH)
353
RTC Divider Low Register (RTC_DIVL)
353
RTC Counter High Register (RTC_CNTH)
354
RTC Counter Low Register (RTC_CNTL)
354
RTC Alarm High Register (RTC_ALRMH)
355
RTC Alarm Low Register (RTC_ALRML)
355
Timer (Timerx)
356
Table 18-1. Timers (Timerx) Are Divided into Five Sorts
356
Advanced Timer (Timerx, X=0, 7)
357
Overview
357
Characteristics
357
Block Diagram
358
Function Overview
358
Figure 18-1. Advanced Timer Block Diagram
358
Figure 18-2. Timing Chart of Internal Clock Divided by 1
359
Figure 18-3. Timing Chart of PSC Value Change from 0 to 2
360
Figure 18-4. Timing Chart of up Counting Mode, PSC=0/2
360
Figure 18-5. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
361
Figure 18-6. Timing Chart of down Counting Mode, PSC=0/2
362
Figure 18-7. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
363
Figure 18-8. Timing Chart of Center-Aligned Counting Mode
364
Figure 18-9. Repetition Timechart for Center-Aligned Counter
365
Figure 18-10. Repetition Timechart for Up-Counter
365
Figure 18-11. Repetition Timechart for Down-Counter
366
Figure 18-12. Channel Input Capture Principle
367
Figure 18-13. Channel Output Compare Principle (with Complementary Output, X=0,1,2)
368
Figure 18-14. Channel Output Compare Principle (CH3_O)
368
Figure 18-15. Output-Compare in Three Modes
369
Figure 18-16. Timing Chart of EAPWM
371
Figure 18-17. Timing Chart of CAPWM
371
Table 18-2. Complementary Outputs Controlled by Parameters
373
Figure 18-18. Complementary Output with Dead-Time Insertion
374
Figure 18-19. Output Behavior of the Channel in Response to a Break (the Break High Active)
375
Figure 18-20. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
376
Figure 18-21. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
376
Table 18-3. Counting Direction in Different Quadrature Decoder Mode
376
Figure 18-22. Hall Sensor I S Used to BLDC Motor
377
Figure 18-23. Hall Sensor Timing between Two Timers
378
Table 18-4. Examples of Slave Mode
378
Figure 18-24. Restart Mode
379
Figure 18-25. Pause Mode
380
Figure 18-26. Event Mode
380
Figure 18-27. Single Pulse Mode, Timerx_Chxcv = 4, Timerx_Car=99
381
Figure 18-28. Timer0 Master/Slave Mode Example
381
Figure 18-29. Trigger TIMER0 and TIMER2 by the CI0 Signal of TIMER2
383
Timerx Registers(X=0, 7)
385
General Level0 Timer (Timerx, X=1, 2, 3, 4)
413
Overview
413
Characteristics
413
Block Diagram
413
Figure 18-30. General Level 0 Timer Block Diagram
413
Function Overview
414
Figure 18-31. Timing Chart of Internal Clock Divided by 1
415
Figure 18-32. Timing Chart of PSC Value Change from 0 to 2
416
Figure 18-33. Timing Chart of up Counting Mode, PSC=0/2
417
Figure 18-34. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
417
Figure 18-35. Timing Chart of down Counting Mode,Psc=0/2
418
Figure 18-36. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
419
Figure 18-37. Timing Chart of Center-Aligned Counting Mode
420
Figure 18-38. Channel Input Capture Principle
421
Figure 18-39. Channel Output Compare Principle (X=0,1,2,3)
422
Figure 18-40. Output-Compare in Three Modes
423
Figure 18-41. Timing Chart of EAPWM
424
Figure 18-42. Timing Chart of CAPWM
425
Table 18-5. Examples of Slave Mode
426
Figure 18-43. Restart Mode
427
Figure 18-44. Pause Mode
427
Figure 18-45. Event Mode
428
Timerx Registers(X=1, 2, 3, 4)
429
General Level1 Timer (Timerx, X=8, 11)
455
Overview
455
Characteristics
455
Block Diagram
455
Figure 18-46. General Level1 Timer Block Diagram
455
Function Overview
456
Figure 18-47. Timing Chart of Internal Clock Divided by 1
457
Figure 18-48. Timing Chart of PSC Value Change from 0 to 2
458
Figure 18-49. Timing Chart of up Counting Mode, PSC=0/2
458
Figure 18-50. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
459
Figure 18-51. Channel Input Capture Principle
460
Figure 18-52. Channel Output Compare Principle (X=0,1)
461
Figure 18-53. Output-Compare under Three Modes
462
Figure 18-54. PWM Mode Timechart
463
Figure 18-55. Restart Mode
464
Table 18-6. Examples of Slave Mode
464
Figure 18-56. Pause Mode
465
Figure 18-57. Event Mode
465
Figure 18-58. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
466
Timerx Registers(X=8, 11)
467
General Level2 Timer (Timerx, X=9, 10, 12, 13)
480
Overview
480
Characteristics
480
Block Diagram
480
Figure 18-59. General Level2 Timer Block Diagram
480
Function Overview
481
Figure 18-60. Timing Chart of Internal Clock Divided by 1
482
Figure 18-61. Timing Chart of PSC Value Change from 0 to 2
482
Figure 18-62. Timing Chart of up Counting Mode, PSC=0/2
483
Figure 18-63. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
484
Figure 18-64. Channel Input Capture Principle
485
Figure 18-65. Channel Output Compare Principle
486
Figure 18-66. Output-Compare under Three Modes
487
Timerx Registers(X=9, 10, 12, 13)
489
Basic Timer (Timerx, X=5, 6)
500
Overview
500
Characteristics
500
Block Diagram
500
Function Overview
500
Figure 18-67. Basic Timer Block Diagram
500
Figure 18-68. Timing Chart of Internal Clock Divided by 1
501
Figure 18-69. Timing Chart of PSC Value Change from 0 to 2
501
Figure 18-70. Timing Chart of up Counting Mode, PSC=0/2
502
Figure 18-71. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
503
Timerx Registers(X=5, 6)
504
Super High-Resolution Timer (SHRTIMER)
509
Overview
509
Characteristics
509
Block Diagram
509
Figure 19-1. SHRTIMER Block Diagram
509
Function Overview
510
Master_Timer Unit
510
Figure 19-2. Master_Timer Diagram
510
Table 19-1. the Limitations of Auto-Reload and Compare y (Y=0..3) Register
511
Figure 19-3. Counter Clock When Divided by 32
512
Table 19-2. Resolution with F
512
Figure 19-4. Counter Behavior in Single Pulse Mode
513
Figure 19-5. Counter Behavior in Continuous Mode
513
Figure 19-6. Repetition Counter Behavior in Continuous Mode
514
Figure 19-7. Repetition Counter Behavior in Single Pulse Mode with CNTRSTM = 0
514
Figure 19-8. Repetition Counter Behavior in Single Pulse Mode with CNTRSTM = 1
515
Figure 19-9 Reset Event Resynchronization When Prescaling Ratio Is 128
515
Table 19-3. Master_Timer Shadow Registers and Update Event
516
Slave_Timerx(X=0
518
Figure 19-10. Slave_Timerx Diagram
518
Table 19-4. the Limitations of Counter and Capture y(Y=0,1) Value Registers
519
Figure 19-11. Capture 0 Triggered by EXEV0 and EXEV1
522
Figure 19-12．Compare 1 Behavior with Stxcar=0X8, Stxcmp1V=0X02
523
Figure 19-13. Compare Delayed Mode Chart
523
Figure 19-14. Compare 1 Delayed Mode 0
524
Figure 19-15. Compare 1 Delayed Mode 1
525
Figure 19-16. Compare Delayed Mode with SHWEN = 0
526
Figure 19-17. Channel Output Diagram
526
Figure 19-18. O0PRE Wave: Set on CMP0, Reset on CMP1
527
Table 19-5. Slave_Timer Interconnection Event
528
Figure 19-19. Arbitration Mechanism During each T
529
Figure 19-20． Arbitration Mechanism Example
530
Figure 19-23. Super High-Resolution Oxpre Wave
531
Figure 19-24. Oxpre Wave with CNTCKDIV[3:0] = 4'B0110
532
Figure 19-25. C0OPRE Wave in Regular Mode
532
Figure 19-26. C0OPRE and C1OPRE Complementary Wave with de Ad-Time
534
Figure 19-27. Complementary Wave with Pulse Width Less than Dead-Time
534
Figure 19-28. Structure Chart in Balanced Mode
535
Figure 19-29. C0OPRE and C1OPRE Wave in Balanced Mode
536
Table 19-6. Crossbar and IDLE Control Stage Work Together
537
Table 19-7. Request to Enter in IDLE and Exit IDLE State
538
Figure 19-30. ISO0 = 0 and CHOP = 0 in Delayed IDLE
539
Figure 19-31. ISO0 = 1 and CHOP = 0 in Delayed IDLE
539
Figure 19-32. ISO0 = 0 and CHOP = 1 in Delayed IDLE
540
Figure 19-33. ISO0 = 1 and CHOP = 1 in Delayed IDLE
540
Figure 19-34. Balanced IDEL with ISO0 = 0 and ISO1 = 0
541
Table 19-8. Output During IDEL State Controlled by Bunch Mode
542
Figure 19-35. Stxchy_O Wave with Chyp=0 or Chyp=1
543
Table 19-9. Output Stage Status Programming (X=0
543
Figure 19-36. Carrier-Signal Structure Diagram
544
Figure 19-37. SHRTIMER Output with Carrier-Signal Mode Enabled
545
Table 19-10. Slave_Timerx Shadow Registers and Update Event
546
Table 19-11. Stxupiny(Y=0..2) and Chip Internal Signal
546
Figure 19-38. Blanking Mode and Windowing Mode
547
Table 19-12. Filtering Signals Mapping in Blanking Mode
547
Table 19-13. Filtering Signals Mapping in Windowing Mode
548
DLL Calibrate
549
Bunch Mode
549
Figure 19-39. Bunch Mode Timing Chart
550
Table 19-14. Chip Internal Signal in Bunch Mode
550
Figure 19-40. Regular Entry for Bunch Mode
551
Figure 19-41. Delayed Entry for Bunch Mode
553
Synchronization Input/Output
554
Figure 19-42. Emulate Bunch Mode Example
554
External Event
555
Figure 19-43. Extern Event y(Y=0..4) Processed Diagram
556
Figure 19-44. Extern Event y(Y=5..9) Processed Diagram
556
Fault Input
557
Figure 19-45. Fault Input Diagram
557
Table 19-15. External Events Mapping
557
Table 19-16. Fault Channel Mapping
558
Trigger to ADC
559
Trigger to DAC
560
Figure 19-46. Trigger to ADC Selection Overview
560
Figure 19-47. Trigger to DAC Selection Overview
560
Interrupt
561
Table 19-17. Interrupt Mapping
561
DMA Request
562
Table 19-18. DMA Request Mapping
562
DMA Mode
563
Debug Mode
564
Register Definition
564
Figure 19-48. DMA Mode Operation Flowchart
564
Master_Timer Registers
565
Slave_Timerx Registers(X=0
577
Common Registers
639
Universal Synchronous/Asynchronous Receiver /Transmitter (USART)
683
Table 20-1. Description of USART Important Pins
684
Figure 20-1. USART Module Block Diagram
685
Figure 20-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
685
Table 20-2. Configuration of Stop Bits
685
Figure 20-3. USART Transmit Procedure
687
Figure 20-4. Receiving a Frame Bit by Oversampling Method
688
Figure 20-5. Configuration Step When Using DMA for USART Transmission
690
Figure 20-6. Configuration Steps When Using DMA for USART Reception
691
Figure 20-7. Hardware Flow Control between Two Usarts
691
Figure 20-8. Hardware Flow Control
692
Figure 20-9. Break Frame Occurs During Idle State
693
Figure 20-10. Break Frame Occurs During a Frame
693
Figure 20-11. Example of USART in Synchronous Mode
694
Figure 20-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
694
Figure 20-13. Irda SIR ENDEC Module
695
Figure 20-14. Irda Data Modulation
695
Figure 20-15. ISO7816-3 Frame Format
696
Table 20-3. USART Interrupt Requests
698
Figure 20-16. USART Interrupt Mapping Diagram
699
Table 20-4. Description of USART Important Pins
715
Figure 20-17. USART Module Block Diagram
716
Figure 20-18. USART Character Frame (8 Bits Data and 1 Stop Bit)
716
Table 20-5. Configuration of Stop Bits
716
Figure 20-19. USART Transmit Procedure
718
Figure 20-20. Oversampling Method of a Receive Frame Bit (OSB=0)
719
Figure 20-21. Configuration Step When Using DMA for USART Transmission
721
Figure 20-22. Configuration Step When Using DMA for USART Reception
722
Figure 20-23. Break Frame Occurs During Idle State
723
Figure 20-24. Break Frame Occurs During a Frame
723
Figure 20-25. Example of USART in Synchronous Mode
724
Figure 20-26. 8-Bit Format USART Synchronous Waveform (CLEN=1)
724
Figure 20-27. Irda SIR ENDEC Module
725
Figure 20-28. Irda Data Modulation
725
Figure 20-29. ISO7816-3 Frame Format
726
Figure 20-30. USART Receive FIFO Structure
729
Table 20-6. USART Interrupt Requests
729
Figure 20-31. USART Interrupt Mapping Diagram
731
Figure 21-1. I2C Module Block Diagram
749
Table 21-1. Definition of I2C-Bus Terminology
750
Figure 21-2. Data Validation
751
Figure 21-3. START and STOP Signal
751
Figure 21-4. Clock Synchronization
752
Figure 21-5. SDA Line Arbitration
752
Figure 21-6. I2C Communication Flow with 7-Bit Address
753
Figure 21-7. I2C Communication Flow with 10-Bit Address (Master Transmit)
753
Figure 21-8. I2C Communication Flow with 10-Bit Address (Master Receive)
753
Figure 21-9. Programming Model for Slave Transmitting (10-Bit Address Mode)
755
Figure 21-10. Programming Model for Slave Receiving (10-Bit Address Mode)
755
Figure 21-11. Programming Model for Master Transmitting (10-Bit Address Mode)
757
Figure 21-12. Programming Model for Master Receiving Using Solution a
759
Figure 21-13. Programming Model for Master Receiving Mode Using Solution B (10-Bit Address Mode)
760
Table 21-2. Event Status Flags
764
Table 21-3. Error Flags
765
Figure 21-14. I2C Module Block Diagram
780
Table 21-4. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
781
Figure 21-15. Data Validation
782
Figure 21-16. START and STOP Signal
783
Figure 21-17. I2C Communication Flow with 10-Bit Address (Master Transmit)
783
Figure 21-18. I2C Communication Flow with 7-Bit Address (Master Transmit)
784
Figure 21-19. I2C Communication Flow with 7-Bit Address (Master Receive)
784
Figure 21-20. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=0)
784
Figure 21-21. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=1)
784
Figure 21-22. Data Hold Time
785
Figure 21-23. Data Setup Time
785
Table 21-5. Data Setup Time and Data Hold Time
786
Figure 21-24. Data Transmission
787
Figure 21-25. Data Reception
788
Table 21-6. Communication Modes to be Shut down
788
Figure 21-26. I2C Initialization in Slave Mode
791
Figure 21-27. Programming Model for Slave Transmitting When SS=0
792
Figure 21-28. Programming Model for Slave Transmitting When SS=1
793
Figure 21-29. Programming Model for Slave Receiving
794
Figure 21-30. I2C Initialization in Master Mode
795
Figure 21-31. Programming Model for Master Transmitting (N<=255)
796
Figure 21-32. Programming Model for Master Transmitting (N>255)
797
Figure 21-33. Programming Model for Master Receiving (N<=255)
798
Figure 21-34. Programming Model for Master Receiving (N>255)
799
Figure 21-35. Smbus Master Transmitter and Slave Receiver Communication Flow
802
Figure 21-36. Smbus Master Receiver and Slave Transmitter Communication Flow
803
Table 21-7. I2C Error Flags
804
Table 21-8. I2C Interrupt Events
804
Figure 22-1. Block Diagram of SPI
821
Table 22-1. SPI Signal Description
821
Table 22-2. Quad-SPI Signal Description
822
Figure 22-2. SPI Timing Diagram in Normal Mode
823
Figure 22-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
823
Table 22-3. NSS Function in Slave Mode
824
Table 22-4. NSS Function in Master Mode
824
Table 22-5. SPI Operation Modes
825
Figure 22-4. a Typical Full-Duplex Connection
826
Figure 22-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
826
Figure 22-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
827
Figure 22-7. a Typical Bidirectional Connection
827
Figure 22-8. Timing Diagram of TI Master Mode with Discontinuous Transfer
829
Figure 22-9. Timing Diagram of TI Master Mode with Continuous Transfer
829
Figure 22-10. Timing Diagram of TI Slave Mode
829
Figure 22-11. Timing Diagram of NSS Pulse with Continuous Transmit
830
Figure 22-12. Timing Diagram of Write Operation in Quad-SPI Mode
831
Figure 22-13. Timing Diagram of Read Operation in Quad-SPI Mode
832
Figure 22-14. Block Diagram of I2S
835
Table 22-6. SPI Interrupt Requests
835
Figure 22-15. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
836
Figure 22-16. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
837
Figure 22-17. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
837
Figure 22-18. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
837
Figure 22-19. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
837
Figure 22-20. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
837
Figure 22-21. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
838
Figure 22-22. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
838
Figure 22-23. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
838
Figure 22-24. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
838

GigaDevice Semiconductor GD32E508 Series User Manual (65 pages)

Brand: GigaDevice Semiconductor | Category: Computer Hardware | Size: 2 MB

Table of Contents
2
List of Figures
4
List of Tables
5
Introduction
7
Table 1-1. Applicable Products
7
Library Architecture and File Structure
8
Library Architecture
8
Figure 2-1. GD32 USBFS Firmware Library Framework
8
File Structure
9
Figure 2-2. USBFS Firmware Library Folder
9
Figure 2-3. Device Folder
9
Figure 2-4. Driver Folder
10
Figure 2-5. Host Folder
10
Figure 2-6. Ustd Folder
11
USBFS Bottom Driver
12
Table 3-1. USBFS Underlying File
12
Table 3-2. Usb_Core.h/.C File Function
12
USBFS Middle Layer Driver
13
Host Middle Layer Driver Function
13
Table 4-1. USBFS Middle Layer Driver File
13
Table 4-2. Drv_Usb_Host.h/.C File Function
13
Table 4-3. Drv_Usbh_Int.h/.C File Function
13
Table 4-4. Usbh_Core.h/.C File Function
14
Table 4-5. Usbh_Enum.h/.C File Function
14
Table 4-6. Usbh_Pipe.h/.C File Function
14
Device Middle Layer Driver Function
15
Table 4-7. Usbh_Transc.h/.C File Function
15
Table 4-8. Drv_Usb_Dev.h/.C File Function
15
Table 4-9. Drv_Usbd_Int.h/.C File Function
16
Table 4-10. Usbd_Core.h/.C File Function
16
Table 4-11. Usbd_Enum.h/.C File Function
16
Table 4-12. Usbd_Transc.h/.C File Function
17
USBFS Device Library
18
Device Library Configuration
18
Usbd_Conf.h
18
Usb_Conf.h
18
Table 5-1. Usbd_Conf.h Configuration Description
18
Firmware Library Process
19
Table 5-2. Usb_Conf.h Configuration Description
19
Descriptor
20
Figure 5-1. Firmware Library Flowchart
20
Figure 5-2. Device Class File Path
21
Interrupt Handling
22
Table 5-3. USBFS Device Interruption
22
USB Device Class Interface
26
Figure 5-3. Device Class File
27
Data Transmission Process
28
IN Direction
28
OUT Direction
28
USB Device Class Routine
29
Audio
29
Figure 5-4. AUDIO Macro Configuration
29
Table 5-4. AUDIO Relevant Descriptors
29
Table 5-5. AUDIO Device Class Interface Function
30
Table 5-6. AUDIO Device Class Request
30
Figure 5-5. AUDIO Device Class
31
Table 5-7. AUDIO User Interface Functions
31
Figure 5-6. Audio Playback File
32
CDC
33
Figure 5-7. Audio System Sound Configuration
33
Figure 5-8. Audio Recording Listening Configuration
33
Table 5-8. CDC Relevant Descriptors
34
Table 5-9. CDC Device Class Interface Functions
34
Figure 5-9. CDC Device Class
35
Table 5-10. CDC Device Class Request
35
Table 5-11. CDC User Interface Functions
35
Dfu
36
Figure 5-10. Virtual Serial Data Transmitting and Receiving
36
Figure 5-11. Virtual Serial Port Large Data Transmitting and Receiving
36
Figure 5-12. DFU State Machine Flow Chart
37
Table 5-12. Dfurelevant Descriptors
37
Table 5-13. DFU Device Class Interface Functions
38
Table 5-14. DFU Device Class Request
38
Figure 5-13. DFU Device Class
39
Table 5-15. DFU User Interface Functions
39
Figure 5-14. All in One Connection
40
Figure 5-15. All in One Uploading
41
Figure 5-16. All in One Option Byte Operation
41
Msc
42
Table 5-16. MSC Device Class Interface Functions
42
Table 5-17. MSC Device Class Request
42
Table 5-18. MSC User Interface Functions
43
Figure 5-17. MSC Device Class
44
Figure 5-18. MSC Device Formatting
44
Figure 5-19. MSC Device Read-Write Test
44
Hid
45
Table 5-19. HID Relevant Descriptors
45
Table 5-20. HID Device Class Interface Functions
45
Table 5-21. HID Device Class Request
45
Figure 5-20. HID Device Class
46
Table 5-22. HID User Interface Functions
46
USB Printer
47
Table 5-23. Printer Device Class Interface Function
47
Table 5-24. Printer Device Class Request
47
Figure 5-21. Printer Device Class
48
USBFS Host Library
49
Host Library Configuration
49
Usbh_Conf.h
49
Usb_Conf.h
49
Table 6-1. Usbh_Conf.h Configuration Description
49
Host VBUS Configuration
50

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GigaDevice Semiconductor GD32E508 Series User Manual (1245 pages)

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GigaDevice Semiconductor GD32E508 Series User Manual (65 pages)

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