Supermicro SUPERSERVER 6021i User Manual page 78

S S 6021i
UPER ERVER
System BIOS Cacheable
If enabled, the system BIOS information stored in the BIOS ROM (Read Only
Memory) chip will be written and temporarily stored in the "cacheable"
section of the memory, so the CPU has faster access to the information.
The settings are "Enabled" or "Disabled".
Video BIOS Cacheable
If enabled, the Video BIOS information stored in the BIOS ROM (Read Only
Memory) chip will be written and temporarily stored in the "cacheable"
section of the memory for faster access. The settings are "Enabled" and
"Disabled".
Memory Hole
To improve the performance of the sytem, a certain section of the memory
will be reserved for the use of the devices installed in the PCI slots. This
section of memory must be mapped into the memory space below 16 MB.
The settings are "15M-16M" and "Disabled".
CPU to PCI Write Buffer
To improve the performance of the system, a certain section of the memory
will be designated as "Write Buffer" to temporarily store the data CPU writes
to PCI to provide faster access. This information can be exe.codes or
operational instructions for the system. The settings are "Enabled" and
"Disabled".
PCI Master 0 WS Write
If enabled, the transimission of PCI Master Write PCI Master Write signals
will have no delays. The settings are "Enabled" and "Disabled".
PCI Delayed Transition
If enabled, the PCI signal transition will be delayed. The settings are
"Enabled" and "Disabled".
Manual
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