Texas Instruments TPSF12C1QEVM User Manual page 9

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2. Circuit Simulation – Avail of PSPICE or SIMPLIS simulation models for the TPSF12C1 device. Use such
models along with prepared test benches to investigate the operation of the complete active filter circuit.
See the SIMPLIS schematic in
analyses as required.
Figure 2-6. SIMPLIS Simulation Schematic of an Active Filter Circuit Using the TPSF12C1
Note that the CM choke model schematics are not shown above. If the choke model equivalent circuit
parameters are defined in the quickstart calculator, transfer them directly to the simulation model as needed.
3. Low-Voltage Tests – Validate the filter design at low voltage prior to connecting to the switching regulator.
This is a relatively easy step to confirm various aspect of the design, including filter stability, insertion loss,
voltage swing on the INJ pin, and EMI performance with CM signal excitation. See
tests 4 through 7 described in
• Insertion loss – measure with 50-Ω source and load impedances.
• Apply a CM excitation signal with a function generator.
– Check the dynamic voltage range of the INJ pin (TPSF12C1 pin 13).
– Measure the EMI (CM only, there is no DM propagation in this test).
4. High-Voltage Tests – Validate the filter design while connected to the switching regulator. See
and refer to tests 8 and 9 described in
• Check the dynamic voltage range of the INJ pin.
• Calculate the device power dissipation
junction temperature is less than 150°C under the worst case operating conditions.
• Check the sense and inject capacitance variation over temperature and ensure the circuit is stable under
all operating conditions.
• Measure the total EMI. Separate the CM (asymmetrical) and DM (symmetrical) propagation components,
as the TPSF12C1-based AEF circuit only attenuates the CM noise.
SLVUCK7A – NOVEMBER 2022 – REVISED JULY 2023
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Figure 2-6 as an example. Perform both time-domain and frequency-domain
Section 2.4.
Section 2.4.
(4)
based on V
VDD
Active EMI Filter Evaluation Module for Single-Phase AC Power Systems
Copyright © 2023 Texas Instruments Incorporated
Figure 2-4
, I , T and R . Verify that the maximum
VDD A θJA
Hardware
and refer to
Figure 2-2
9