Texas Instruments TPSF12C1QEVM User Manual page 5

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The AC/DC regulator has internal high-dv/dt switching nodes that can capacitively couple CM noise to the
chassis. As such, verifying the Y-capactiors in the EMI filter are closely referenced to the chassis is imperative,
as illustrated in Figure 2-1. The Y-capacitors can then return the CM noise current back to the noise source in
a tight conduction loop. Otherwise, the noise current can flow in the reference ground plane back to the LISNs,
rendering the EMI filter less effective.
2.2.1 High-Voltage Testing
Referencing the header connections described in
of Figure 2-2 to evaluate the performance of the TPSF12C1 with a single-phase AC/DC regulator. A two-phase
interleaved boost PFC topology represents a typical power stage and is drawn for illustrative purposes in
2-2 (the setup is essentially agnostic to regulator topology).
AC Mains
L
Dual
C
X1
LISN
GND
N
C
C
Y1
Y2
LISNs bonded
to the reference
ground plane
for EMI
measurement
Chassis (PE)
Figure 2-2. EVM Setup Schematic for High-Voltage Testing With an AC/DC Regulator Connected
2.2.2 EVM Connections
The EVM daughter-card connects to the main EMI filter board through header J1. The sense and inject
capacitors, along with a robust ground connection, interfaces the low-voltage EVM to the high-voltage power
lines.
Header J1 provides an interface through terminals S1, S2, INJ and GND, as described in
and S2 to sense capacitors, designated as C
the sense capacitors to the Live and Neutral power lines between the CM chokes, L
to the inject capacitor, designated as C
power line as shown. The X-capacitor at this position, designated as C
power lines from a CM standpoint – this means that a single inject capacitor is adequate for current injection.
Finally, connect a nominal 12-V bias supply from VDD to GND to power the AEF circuit. The GND attachment
point on the filter board corresponds to where the Y-capacitors in a passive design normally connect.
Refer to the diagram of Figure 2-3
header J1 can mount directly to receptacle J2.
SLVUCK7A – NOVEMBER 2022 – REVISED JULY 2023
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Table
L
CM1
C
X2
C C
C
SEN2 SEN1 INJ
680 pF 680 pF 4.7 nF
Chassis
(PE)
To enable the IC, leave EN open or
connect it to VDD using a jumper
S2 S1 INJ VDD
J1
EN
C
U1
VDD
C
NC IGND
D3
C
D1
R
D1A
VDD INJ
TPSF12C1
R
D1
NC NC
SENSE1A COMP2
C
G1
C
G2
SENSE1B
COMP1
R
G
SENSE2A REFGND
SENSE2B EN
TI standalone active EMI filter EVM
and C
SEN1
, whose opposite terminal then connects to either the Live or Neutral
INJ
for an example of component placement on a filter board, where the EVM
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2-1, use the recommended setup from the schematic
L
CM2
L'
C
X3
N'
C C
Y3
Y4
Chassis (PE)
Chassis-referred VDD bias supply = 12 V
R
D3
D
1
C
D2
R
D2
in Figure 2-2. Connect the opposite terminals of
SEN2
, sets a low impedance between the
X2
Active EMI Filter Evaluation Module for Single-Phase AC Power Systems
Hardware
Figure
Interleaved boost PFC
= AC/DC regulator
= Dual LISN for EMI measurement
= EVM
= Single-phase AEF IC
= Y-rated sense and inject capacitors
= 6-pin header
Table 2-1. Connect S1
and L . Connect INJ
CM1 CM2
5