ARTERY AT32F435ZDT7 Reference Manual

Arm-based 32-bit cortex-m4f mcu+fpu with 256 to 4032 kb flash, slib, dual qspi, sdram, dual otgfs, ethernet, camera, 18 timers, 3 adcs, 23 communication interfaces
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®
ARM
-based 32-bit Cortex
dual QSPI, SDRAM, dual OTGFS, Ethernet, camera, 18 timers, 3 ADCs, 23
communication interfaces
Feature
®
Core: ARM
32-bit Cortex
− 288 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
− Floating Point Unit (FPU)
− DSP instructions
Memories
− 256 to 4032 KBytes of Flash memory
− sLib: configurable part of main Flash set as a library
area with code executable but secured, non-
readable
− 384 to 512 KBytes of SRAM
− External memory controller (XMC) with 16-bit data
bus: supports CF, SRAM, PSRAM, NOR, NAND,
SDRAM memories
− Up to 2 x QSPI interfaces for external SPI Flash or
SPI RAM extension, and memory mapping mode
LCD parallel interface, 8080/6800 modes
Power control (PWC)
− 2.6 V ~ 3.6 V application supply
− Power-on reset (POR)/ low-voltage reset (LVR), and
power voltage monitor (PVM)
− Low power: Sleep, Deepsleep, and Standby modes
− VBAT supply for LEXT, ERTC and 20 x 32-bit battery
power register (ERTC_BPR)
Clock and reset management (CRM)
− 4 to 25 MHz crystal oscillator (HEXT)
− Internal 48 MHz factory-trimmed clock (HICK),
accuracy 1% at T
+105 °C, with automatic clock calibration (ACC)
− PLL with configurable frequency multiplication and
division factor
− 32.768 kHz crystal oscillator (LEXT)
− Internal 40 kHz RC oscillator (LICK)
Analog
− 3 x 12-bit 5.33 MSPS A/D converters, up to 24 input
channels, 12-bit/10-bit/8-bit/6-bit configurable
resolution
− Temperature sensor (V
voltage (V
), V
I N T R
(V
/4)
B A T
− 2 x 12-bit D/A converters
DMA:
− 2 x general-purpose DMAs and 1 x EDMA
− 22 channels in all
Up to 116 Fast I/O Interfaces
2023.08.02
AT32F435/437 Series Reference Manual
®
-M4F MCU+FPU with 256 to 4032 KB Flash, sLib,
®
-M4F CPU with FPU
=25 °C, 2.5 % at T
=-40 to
A
A
), internal reference
T S
battery voltage monitor
B A T
− All mappable to 16 external interrupt vectors
− Almost 5 V-tolerant
Up to 18 Timers (TMR)
− Up to 13 x 16-bit timers + 2 x 32-bit timers, each with 4
IC/OC/PWM or pulse counter channels
− 2 x Watchdog timers (WDT and WWDT)
− SysTick timer: 24-bit downcounter
ERTC: enhanced RTC with auto wakeup, alarm,
subsecond precision, hardware calendar and
calibration feature
Up to 23 communication interfaces
− Up to 3 x I
2
C interfaces (SMBus/PMBus)
− Up to 4 x USARTs/4 x UARTs (ISO7816 interface, LIN,
IrDA capability, modem control and RS485 drive enable,
with interchangeable TX/RX)
− Up to 4 x SPIs (36 Mbit/s), all with I
2
multiplexed, I
S2/ I
− Up to 2 x CAN interfaces (2.0B Active)
− Up to 2 x OTG FS controllers supporting crystal-less
− Up to 2 x SDIO interfaces
− Infrared transmitter (IRTMR)
− 10/100M Ethernet MAC with dedicated DMA and
SRAM(4 Kbytes): IEEE1588 hardware support, MII/RMII
available (For AT32F437 only)
8~14 bit parallel digital camera interface (DVP)
CRC Calculation Unit
96-bit ID (UID)
Debug mode
− SWD and JTAG interfaces
Temperature range: -40 to 105℃
Packaging
− LQFP144 20 x 20 mm LQFP100 14 x 14 mm
− LQFP64 10 x 10 mm
− QFN48 6 x 6 mm
 List of Models
Internal Flash
AT32F435ZMT7, AT32F435VMT7,AT32F435RMT7,
AT32F435CMT7, AT32F435CMU7, AT32F437ZMT7,
4032 KBytes
AT32F437VMT7, AT32F437RMT7
AT32F435ZGT7, AT32F435VGT7, AT32F435RGT7,
AT32F435CGT7, AT32F435CGU7, AT32F437ZGT7
1024 KBytes
AT32F437VGT7, AT32F437RGT7
AT32F435ZDT7, AT32F435VDT7,AT32F435RDT7,
AT32F435CDT7,AT32F435CDU7, AT32F437ZDT7
448 KBytes
AT32F437VDT7, AT32F437RDT7
AT32F435ZCT7, AT32F435VCT7,AT32F435RCT7,
256 KBytes
AT32F435CCT7,AT32F435CCU7, AT32F437ZCT7
AT32F437VCT7, AT32F437RCT7
Page 1
2
S interface
2
S3 support full-duplex
LQFP48 7 x 7 mm
Model
Rev 2.05

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Summary of Contents for ARTERY AT32F435ZDT7

  • Page 1 AT32F437VMT7, AT32F437RMT7 AT32F435ZGT7, AT32F435VGT7, AT32F435RGT7, B A T AT32F435CGT7, AT32F435CGU7, AT32F437ZGT7 1024 KBytes − 2 x 12-bit D/A converters AT32F437VGT7, AT32F437RGT7 AT32F435ZDT7, AT32F435VDT7,AT32F435RDT7,  DMA: AT32F435CDT7,AT32F435CDU7, AT32F437ZDT7 448 KBytes − 2 x general-purpose DMAs and 1 x EDMA AT32F437VDT7, AT32F437RDT7 AT32F435ZCT7, AT32F435VCT7,AT32F435RCT7, −...
  • Page 2: Table Of Contents

    AT32F435/437 Series Reference Manual Contents System architecture ..............44 System overview ................46 ® 1.1.1 ARM Cortex -M4F processor ............46 1.1.2 BusMatrix ................... 46 1.1.3 Bit band ..................48 1.1.4 Interrupt and exception vectors ............ 50 1.1.5 System Tick (SysTick) ..............53 1.1.6 Reset ..................
  • Page 3 AT32F435/437 Series Reference Manual Clock ..................70 4.1.1 Clock sources ................70 4.1.2 System clock ................71 4.1.3 Peripheral clock ................71 4.1.4 Clock fail detector ............... 72 4.1.5 Auto step-by-step system clock switch .......... 72 4.1.6 Clock output ................72 4.1.7 Interrupts ..................
  • Page 4 AT32F435/437 Series Reference Manual 4.3.19 APB2 peripheral clock enable in low power mode register (CRM_AHB2LPEN) ................91 4.3.20 Battery powered domain control register (CRM_BPDC) ....92 4.3.21 Control/status register (CRM_CTRLSTS) ........93 4.3.22 Additional register1 (CRM_MISC1) ..........94 4.3.23 Additional register2 (CRM_MISC2) ..........95 Flash memory controller (FLASH) ..........
  • Page 5 AT32F435/437 Series Reference Manual 5.6.11 Flash status register2 (FLASH_STS2) ......... 114 5.6.12 Flash control register2 (FLASH_CTRL2) ........114 5.6.13 Flash address register2 (FLASH_ADDR2) ........115 5.6.14 Flash continue read register (FLASH_CONTR) ......115 5.6.15 Flash divider register (FLASH_DIVR) .......... 115 5.6.16 Flash security library status register2 (SLIB_STS2) ......
  • Page 6 AT32F435/437 Series Reference Manual 6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..H) ....138 6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A..H) ....138 6.3.5 GPIO input register (GPIOx_IDH) (x=A..H) ........138 6.3.6 GPIO output register (GPIOx_IDH) (x=A..H) ......... 138 6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A..H) ......138 6.3.8 GPIO write protection register (GPIOx_WPR) (x=A..H) ....
  • Page 7 AT32F435/437 Series Reference Manual Main features ................152 Function overview ..............153 9.3.1 DMA configuration ..............153 9.3.2 Handshake mechanism ............... 153 9.3.3 Arbiter ..................154 9.3.4 Programmable data transfer width ..........154 9.3.5 Errors ..................155 9.3.6 Interrupts ................... 155 DMA multiplexer (DMAMUX) ............
  • Page 8 AT32F435/437 Series Reference Manual 10.3.4 Initialization register (CRC_IDT) ..........171 10.3.5 Polynomial register (CRC_POLY) ..........171 C interface ................172 11.1 I C introduction ................172 11.2 I C main features ............... 172 11.3 I C function overview ..............172 11.4 I C interface ................
  • Page 9 AT32F435/437 Series Reference Manual 12.3 Mode selector ................207 12.3.1 Introduction................207 12.3.2 Configuration procedure ............. 207 12.4 USART frame format and configuration ........210 12.5 DMA transfer introduction ............212 12.5.1 Transmission using DMA ............212 12.5.2 Reception using DMA ..............212 12.6 Baud rate generation ..............
  • Page 10 AT32F435/437 Series Reference Manual 13.2.3 Chip select controller ..............228 13.2.4 SPI_SCK controller ..............229 13.2.5 CRC ..................229 13.2.6 DMA transfer ................230 13.2.7 TI mode ..................230 13.2.8 Transmitter ................231 13.2.9 Receiver ..................231 13.2.10 Motorola mode ................ 232 13.2.11 TI mode ..................
  • Page 11 AT32F435/437 Series Reference Manual 14.1 Basic timer (TMR6 and TMR7) ............ 251 14.1.1 TMR6 and TMR7 introduction ............251 14.1.2 TMR6 and TMR7 main features ........... 251 14.1.3 TMR6 and TMR7 function overview ..........251 14.1.3.1 Counting clock ..............251 14.1.3.2 Counting mode ..............
  • Page 12 AT32F435/437 Series Reference Manual 14.2.4.11 TMR2 to TMR5 division value (TMRx_DIV) ......280 14.2.4.12 TMR2 to TMR5 period register (TMRx_PR) ......280 14.2.4.13 TMR2 to TMR5 channel 1 data register (TMRx_C1DT) ..280 14.2.4.14 TMR2 to TMR5 channel 2 data re gister (TMRx_C2DT) ..280 14.2.4.15 TMR2 to TMR5 channel 3 data register (TMRx_C3DT) ..
  • Page 13 AT32F435/437 Series Reference Manual 14.3.5.2 TMR10, TMR11, TMR13 and TMR14 DMA/interrupt enable register (TMRx_IDEN) ..................300 14.3.5.3 TMR10, TMR11, TMR13 and TMR14 interrupt status register (TMRx_ISTS) ..................300 14.3.5.4 TMR10, TMR11, TMR13 and TMR14 software event register (TMRx_SW EVT)................. 300 14.3.5.5 TMR10, TMR11, TMR13 and TMR14 channel mode register1 (TMRx_CM1) ..................
  • Page 14 AT32F435/437 Series Reference Manual 14.4.4.11 TMR1, TMR8 and TMR20 division value (TMRx_DIV) ... 332 14.4.4.12 TMR1, TMR8 and TMR20 period register (TMRx_PR) ... 332 14.4.4.13 TMR1, TMR8 and TMR20 rep etition period register (TMRx_RPR) 332 14.4.4.14 TMR1, TMR8 and TMR20 channel 1 data register (TMRx_C1DT) 332 14.4.4.15 TMR1, TMR8 and TMR20 channel 2 data register (TMRx_C2DT) 333 14.4.4.16...
  • Page 15 AT32F435/437 Series Reference Manual Enhanced real-time clock (ERTC) ..........342 17.1 ERTC introduction..............342 17.2 ERTC main features ..............342 17.3 ERTC function overview ............. 343 17.3.1 ERTC clock ................343 17.3.2 ERTC initialization ..............343 17.3.3 Periodic automatic wakeup ............345 17.3.4 ERTC calibration ................
  • Page 16 AT32F435/437 Series Reference Manual Analog-to-digital converter (ADC) ..........359 18.1 ADC introduction ............... 359 18.2 ADC main features ..............359 18.3 ADC structure ................359 18.4 ADC functional overview ............. 360 18.4.1 Channel management ..............360 18.4.1.1 Internal temperature sensor ........... 361 18.4.1.2 Internal reference voltage ............
  • Page 17 AT32F435/437 Series Reference Manual 18.6.4 ADC sampling time register 1 (ADC_SPT1) ........381 18.6.5 ADC sampling time register 2 (ADC_SPT2) ........382 18.6.6 ADC preempted channel data offset register x (ADC_ PCDTOx) (x=1..4) ..............384 18.6.7 ADC voltage monitor high threshold register (ADC_VWHB) ... 384 18.6.8 ADC voltage monitor low threshold register (ADC_ VWLB) ....
  • Page 18 AT32F435/437 Series Reference Manual 19.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_ DDTH12R) 398 19.5.10 Dual DAC 12-bit left-aligned data holding register (DAC_ DDTH12L) 399 19.5.11 Dual DAC 8-bit right-aligned data holding register (DAC_ DDTH8R)399 19.5.12 DAC1 data output register (DAC_ D1ODT) ........ 399 19.5.13 DAC2 data output register (DAC_ D2ODT) ........
  • Page 19 AT32F435/437 Series Reference Manual 20.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) ... 421 20.7.2.5 Receive FIFO mailbox identifier register (CAN_RFIx) (x=0..1) .. 421 20.7.2.6 Receive FIFO mailbox data length and time stamp register (CAN_RFCx) (x=0..1) ................. 421 20.7.2.7 Receive FIFO mailbox data low register (CAN_RFDTLx) (x=0..1) 422 20.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx) (x=0..1) 422 20.7.3 CAN filter registers ..............
  • Page 20 AT32F435/437 Series Reference Manual 21.5.3.10 Initialize interrupt OUT transfers ........440 21.5.3.11 Initialize synchronous IN transfers ........442 21.5.3.12 Initialize synchronous OUT transfers ........443 21.5.4 OTGFS device mode ..............445 21.5.4.1 Device initialization ............... 445 21.5.4.2 Endpoint initialization on USB reset ........445 21.5.4.3 Endpoint initialization on enumeration completion ....
  • Page 21 AT32F435/437 Series Reference Manual 21.6.3.10 OTGFS non-periodic Tx FIFO size (OTGFS_GNPTXFSIZ)/Endpoint 0 Tx FIFO size registers (OTGFS_DIEPTXF0) ......... 475 21.6.3.11 OTGFS non-periodic Tx FIFO size/request queue status register (OTGFS_GNPTXSTS) ................ 476 21.6.3.12 OTGFS general controller configuration register (OTGFS_GCCFG) ................476 21.6.3.13 OTGFS controller ID register (OTGFS_GUID) ......
  • Page 22 AT32F435/437 Series Reference Manual 21.6.5.8 OTGFS device IN endpoint FIFO empty interrupt mask register (OTGFS_DIEPEMPMSK) ..............488 21.6.5.9 OTGFS device control IN endpoint 0 control register (OTGFS_DIEPCTL0) ................488 21.6.5.10 OTGFS device IN endpoint -x control register (OTGFS_ DIEPCTLx) (x=x=1…7, where x is endpoint number) ..........490 21.6.5.11 OTGFS device control OUT endpoint 0 control register (OTGFS_DOEPCTL0) .................
  • Page 23 AT32F435/437 Series Reference Manual 22.6.5 Compare value 1 (ACC_C1) ............503 22.6.6 Compare value 2 (ACC_C2) ............504 22.6.7 Compare value 3 (ACC_C3) ............504 Infrared timer (IRTMR) ..............505 External memory controller (XMC) ..........506 24.1 XMC introduction ............... 506 24.2 XMC main features ..............
  • Page 24 AT32F435/437 Series Reference Manual 24.7.2 NAND Flash control registers ............542 24.7.2.1 NAND Flash control register x (XMC_BKxCTRL) (x=2,3) ..542 24.7.2.2 Interrupt enable and FIFO status register x (XMC_BKxIS) (x=2,3) 542 24.7.2.3 Regular memory timing register x (XMC_ BKxTMGRG) (x=2,3) . 543 24.7.2.4 Special memory timing register x (XMC_ BKxTMGSP) (x=2,3) ..
  • Page 25 AT32F435/437 Series Reference Manual 25.4 SDIO registers ................571 25.4.1 SDIO power control register (SDIO_ PWRCTRL) ......571 25.4.2 SDIO clock control register (SDIO_ CLKCTRL) ......572 25.4.3 SDIO argument register (SDIO_ARG) .......... 573 25.4.4 SDIO command register (SDIO_CMD) ......... 573 25.4.5 SDIO command response register (SDIO_RSPCMD) ....
  • Page 26 AT32F435/437 Series Reference Manual 26.3.7 Ethernet MAC flow control register (EMAC_MACFCTRL) ....618 26.3.8 Ethernet MAC VLAN tag register (EMAC_MACVLT) ...... 620 26.3.9 Ethernet MAC remote wakeup frame filter register (EMAC_MACRWFF) 620 26.3.10 Ethernet MAC PMT control and status register (EMAC_MACPMTCTRLSTS) ..............
  • Page 27 AT32F435/437 Series Reference Manual 26.3.37 Ethernet MMC receive interrupt register (EMAC_MMCRIM) ..637 26.3.38 Ethernet MMC transmit interrupt register (EMAC_MMCTIM) ..637 26.3.39 Ethernet MMC transmitted good frame single coll ision counter register (EMAC_MMCTFSCC) ................637 26.3.40 Ethernet MMC transmitted good frame more than a single collision counter register (EMAC_MMCTFMSCC) ..........
  • Page 28 AT32F435/437 Series Reference Manual 27.4.2 Data output packing ..............649 27.5 Interrupts and interrupt control ............ 650 27.6 Functional overview ..............651 27.6.1 Frame rate control ..............651 27.6.2 Crop window ................651 27.6.3 Image resizing ................652 27.6.4 Grayscale image binarization conversion ........655 27.7 Data formats ................
  • Page 29 AT32F435/437 Series Reference Manual 28.3.2 CPU PIO mode ................666 28.3.3 DMA handshake mode ..............666 28.3.4 XIP port (direct address mapping read/write) ....... 667 28.3.5 XIP port prefetch ................ 667 28.3.6 SPI device operation ..............667 28.4 QSPI registers ................673 28.4.1 Command word 0 (CMD_W0) ............
  • Page 30 AT32F435/437 Series Reference Manual 29.3.8 2D transfer mechanism ............... 687 29.3.9 Errors ..................688 29.3.10 Interrupts ................689 29.4 DMA multiplexer (DMAMUX) ............689 29.4.1 DMAMUX functional overview ............. 689 29.4.2 DMAMUX overflow interrupts ............691 29.5 EDMA registers ................. 693 29.5.1 DMA status register 1 (DMA_STS1) ..........
  • Page 31 AT32F435/437 Series Reference Manual Debug (DEBUG) ................708 30.1 Debug introduction ..............708 30.2 Debug and Trace ............... 708 30.3 I/O pin control................708 30.4 DEGUB registers ............... 708 30.4.1 DEBUG device ID (DEBUG_IDCODE) .......... 709 30.4.2 DEBUG control register (DEBUG_CTRL) ........710 30.4.3 DEBUG APB1 pause register (DEBUG_ APB1_PAUSE) ....
  • Page 32 AT32F435/437 Series Reference Manual List of figures Figure 1-1 AT32F435/437 Series microcontrollers system architecture ............. 45 Figure 1-2 Internal block diagram of Cortex ® -M4F ..................46 Figure 1-3 Internal block diagram of AHB BusMatrix.................. 47 Figure 1-4 Comparison between bit-band region and its alias region: image A ......... 48 Figure 1-5 Comparison between bit-band region and its alias region: image B .........
  • Page 33 AT32F435/437 Series Reference Manual Figure 11-12 I C slave receive flow ......................185 Figure 11-13 I C slave receive timing ......................185 Figure 11-14 SMBus master transmission flow ..................190 Figure 11-15 SMBus master transmission timing ..................191 Figure 11-16 SMBus master receive flow ....................191 Figure 11-17 SMBus master receive timing ....................
  • Page 34 AT32F435/437 Series Reference Manual Figure 13-23 Audio standard timings ......................243 Figure 13-24 I S interrupts ......................... 244 Figure 14-1 Basic timer block diagram ...................... 251 Figure 14-2 Control circuit with CK_INT divided by 1 ................251 Figure 14-3 Counter structure ........................252 Figure 14-4 Overflow event when PRBEN=0 ....................
  • Page 35 AT32F435/437 Series Reference Manual Figure 14-44 Counter timing with prescaler value changing from 1 to 4 ..........285 Figure 14-45 Counter structure ......................... 286 Figure 14-46 Overflow event when PRBEN=0 ..................287 Figure 14-47 Overflow event when PRBEN=1 ..................287 Figure 14-48 Input/output channel 1 main circuit ..................
  • Page 36 AT32F435/437 Series Reference Manual Figure 14-89 Example of reset mode ......................320 Figure 14-90 Example of suspend mode ....................321 Figure 14-91 Example of trigger mode ...................... 321 Figure 15-1 Window watchdog block diagram ..................336 Figure 15-2 Window watchdog timing diagram ..................337 Figure 16-1 WDT block diagram ........................
  • Page 37 AT32F435/437 Series Reference Manual Figure 21-4 Reading the receive FIFO ...................... 432 Figure 21-5 HFIR behavior when HFIRRLDCTRL=0x0 ................433 Figure 21-6 HFIR behavior when HFIRRLDCTRL=0x1 ................434 Figure 21-7 Example of common Bulk/Control OUT/SETUP and Bulk/Control IN transfer ...... 437 Figure 21-8 Example of common interrupt OUT/IN transfers ..............
  • Page 38 AT32F435/437 Series Reference Manual Figure 25-8 SDIO command transfer ......................568 Figure 25-9 Data channel state machine (DCSM) ..................568 Figure 26-1 Block diagram of EMAC ......................580 Figure 26-2 SMI interface signals ......................582 Figure 26-3 MII signals ..........................583 Figure 26-4 Reduced media-independent interface signals ..............
  • Page 39 AT32F435/437 Series Reference Manual Figure 28-8 Quick read dual-wire I/O ......................669 Figure 28-9 Quick read quad output ......................669 Figure 28-10 Quick read quad I/O command .................... 670 Figure 29-1 Block diagram......................... 681 Figure 29-2 Channel select and synchronizer ................... 683 Figure 29-3 Re-arbitrate after Request/Acknowledge ................
  • Page 40 AT32F435/437 Series Reference Manual List of tables Table 1-1 Bit-band address mapping in SRAM ................... 49 Table 1-2 Bit-band address mapping in the peripheral area ............... 49 Table 1-3 AT32F435/437 series vector table ....................50 Table 1-4 List of abbreviations for registers ....................56 Table 1-5 List of abbreviations for registers ....................
  • Page 41 AT32F435/437 Series Reference Manual Table 12-2 Data sampling over start bit and noise detection ..............216 Table 12-3 Data sampling over valid data and noise detection ..............217 Table 12-4 USART interrupt request ......................218 Table 12-5 USART register map and reset value ..................219 Table 13-1 Audio frequency precision using system clock ................
  • Page 42 AT32F435/437 Series Reference Manual Table 24-2 NAND pins ..........................509 Table 24-3 PC card pins ..........................509 Table 24-4 SDRAM pins ..........................509 Table 24-5 Memory bank selection ......................511 Table 24-6 8-bit SDRAM address mapping ....................511 Table 24-7 16-bit SDRAM address mapping ..................... 512 Table 24-8 Pin signals for NOR and PSRAM ....................
  • Page 43 AT32F435/437 Series Reference Manual Table 25-7 Erase commands ........................561 Table 25-8 I/O mode commands ....................... 561 Table 25-9 Card lock commands ....................... 561 Table 25-10 Application-specific commands ..................... 562 Table 25-11 R1 response ........................... 562 Table 25-12 R2 response........................... 563 Table 25-13 R3 response...........................
  • Page 44: System Architecture

    AT32F435/437 Series Reference Manual 1 System architecture ® ® AT32F435/437 series microcontrollers incorporates a 32-bit ARM Cortex -M4F processor core, multiple 16-bit and 32-bit timers, Infrared Transmitter (IRTMR), DMA controller, EDMA controller, ERTC, communication interfaces such as SPI, QSPI, I2C, USART/UART and SDIO, CAN bus controller, external memory controller (XMC), USB2.0 full-speed interfaces, Ethernet MAC, parallel digital camera interface, HICK with automatic clock calibration (ACC), 12-bit ADC, 12-bit DAC, programmable voltage ®...
  • Page 45: Figure 1-1 At32F435/437 Series Microcontrollers System Architecture

    AT32F435/437 Series Reference Manual Figure 1-1 AT32F435/437 Series microcontrollers system architecture HEXT 4~25 MHz SWJTAG HICK 48 MHz Cortex-M4F SDIO1/2 Max.288 MHz (Freq. Max. MHz) FCLK HCLK NVIC PCLK1 PCLK2 DMA1_2 14 Channel AHB1 EDMA Flash Flash 8 Channal Controller POR/LVR OTGFS1/2 SRAM1...
  • Page 46: 1.1 System Overview

    AT32F435/437 Series Reference Manual 1.1 System overview ® 1.1.1 ARM Cortex -M4F processor Cortex ® -M4F processor is a low-power consumption processor featuring low gate count, low interrupt latency, and low-cost debug. It supports DSP instruction set and FPU, and is applicable to deeply-embedded applications that require quicker response to interruption.
  • Page 47: Figure 1-3 Internal Block Diagram Of Ahb Busmatrix

    AT32F435/437 Series Reference Manual Figure 1-3 Internal block diagram of AHB BusMatrix. DMA1 EMAC DMA2 EDMA Corter-M4 ICODE DCODE SBUS FLASH SRAM1 SRAM2 APB1 APB2 GPIO AHB1 EMAC SDIO1 USBOTG2 USBOTG1 SDIO2 XMC_ QSPI1_ QSPI2_ AHB BUS MATRIX 2023.08.02 Page 47 Rev 2.05...
  • Page 48: Bit Band

    AT32F435/437 Series Reference Manual 1.1.3 Bit band With the help of bit-band, read and write access to a single bit can be performed using common load/store operations. The Cortex ® -M4F memory includes two bit-band regions: the least significant 1M bytes of SRAM and the least significant 1Mbytes of peripherals.
  • Page 49: Table 1-1 Bit-Band Address Mapping In Sram

    AT32F435/437 Series Reference Manual The lowest 1 Mbyte of peripherals: 0x4000_0000~0x400F_FFFF For a bit in the SRAM bit-band region, if the byte address is A, the bit number is n (0<=n<=7), then the alias address where the bit is: AliasAddr = 0x2200_0000+ (A-0x2000_0000)*32+n*4 For a bit in the peripheral bit-band region, if the byte address is A, the bit number is n (0<=n<=7), then the alias address where the bit is: AliasAddr = 0x4200_0000+ (A-0x4000_0000)*32+n*4...
  • Page 50: Interrupt And Exception Vectors

    AT32F435/437 Series Reference Manual For now, you just need do: Read the bit status from the bit-band alias region   Compare and jump Apart from making code more concise, its important function is also reflected in multi-task environment. When it comes to multiple tasks, it turns the read-modify-write operations into a hardware-supported atomic operation to avoid the scenario where the read-modify-write operation is disrupted, resulting in disorder.
  • Page 51 AT32F435/437 Series Reference Manual Configu EDMA data flow5 EDMA data flow5 global interrupt 0x0000_007C rable Configu EDMA data flow6 EDMA data flow6 global interrupt 0x0000_0080 rable Configu EDMA data flow7 EDMA data flow7 global interrupt 0x0000_0084 rable Configu ADC1_2_3 ADC1, ADC2 and ADC3 global interrupt 0x0000_0088 rable Configu...
  • Page 52 AT32F435/437 Series Reference Manual Configu SDIO1 SDIO1 global interrupt 0x0000_0104 rable Configu TMR5 TMR5 global interrupt 0x0000_0108 rable Configu SPI3_I2S3EXT SPI3 and I2S3EXT global interrupt 0x0000_010C rable Configu UART4 UART4 global interrupt 0x0000_0110 rable Configu UART5 UART5 global interrupt 0x0000_0114 rable Configu TMR6 global interrupt...
  • Page 53: System Tick (Systick)

    AT32F435/437 Series Reference Manual rable Configu SPI4 SPI4 global interrupt 0x0000_0190 rable 0x0000_0194 0x0000_0198 0x0000_019C 0x0000_01A0 0x0000_01A44 0x0000_01A8 Configu QSPI2 QSPI2 global interrupt 0x0000_01AC rable Configu QSPI1 QSPI1 global interrupt 0x0000_01B0 rable 0x0000_01B4 Configu DMAMUX DMAMUX overflow interrupt 0x0000_01B8 rable 0x0000_01BC 0x0000_01C0 0x0000_01C4...
  • Page 54: Reset

    AT32F435/437 Series Reference Manual 1.1.6 Reset The processor reads the first two words from the CODE memory after a system reset and before program execution.  Get the initial value of the main stack pointer (MSP) from address 0x0000_0000 Get the initial value of the program counter (PC) from address 0x0000_0004. This value is a reset ...
  • Page 55: Figure 1-7 Example Of Msp And Pc Initialization

    AT32F435/437 Series Reference Manual Figure 1-7 Example of MSP and PC initialization Other Memory Initial SP Value 0x2000_8000 0x2000_8000 1st push data 0x2000_7FFC Stack grows 0x2000_7FF8 2nd push data downward Stack Memory 0x2000_7C00 Other Memory Code Boot Code 0x0000_0100 Other Exception Vectors 0x0000_0101 0x0000_0004...
  • Page 56: 1.2 List Of Abbreviations For Registers

    AT32F435/437 Series Reference Manual 1.2 List of abbreviations for registers List of abbreviations for registers Table 1-4 Register type Description Software can read and write to this bit. Software can only read this bit. Software can only write to the bit. Reading it returns its reset value. Software can read this bit.
  • Page 57: Memory Resources

    AT32F435/437 Series Reference Manual Bit 31: 0 UID[95: 64] 0xXXXX XXXX UID for bit 95 to bit 64 Note: UID[95:88] is series ID, which is 0x0D for AT32F435, and 0x0E for AT32F437. 2 Memory resources 2.1 Internal memory address map Internal memory contains program memory (Flash), data memory (SRAM), peripheral registers and core registers.
  • Page 58 AT32F435/437 Series Reference Manual Bank Name Address range Sector 0 0x0800 0000 - 0x0800 0FFF Sector 1 0x0800 1000 - 0x0800 1FFF Sector 2 0x0800 2000 - 0x0800 2FFF Block 0 … … Sector 15 0x0800 F000 - 0x0800 FFFF Sector 16 0x0801 0000 - 0x0801 0FFF Bank 1...
  • Page 59 AT32F435/437 Series Reference Manual Flash memory organization (1024K) The main memory features bank 1 and bank 2, with 512 Kbytes in each. Each bank is divided into 8 blocks, each of which includes 32 sectors and 2 Kbytes per sector. User system data area is 512 bytes.
  • Page 60: 2.3 Sram Memory

    AT32F435/437 Series Reference Manual Flash memory organization (256K) Main Flash memory (256 KB) has only bank 1, which is divided into 4 blocks that include 32 sectors in each, and 2 K per sector. User system data area is 512 bytes. Bank Name Address range...
  • Page 61 AT32F435/437 Series Reference Manual 0x4002 1800 - 0x4002 1BFF GPIO port G 0x4002 1400 - 0x4002 17FF GPIO port F 0x4002 1000 - 0x4002 13FF GPIO port E 0x4002 0C00 - 0x4002 0FFF GPIO port D 0x4002 0800 - 0x4002 0BFF GPIO port C 0x4002 0400 - 0x4002 07FF GPIO port B...
  • Page 62 AT32F435/437 Series Reference Manual 0x4000 7000 - 0x4000 73FF Power control (PWC) 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2...
  • Page 63: Power Control (Pwc)

    AT32F435/437 Series Reference Manual 3 Power control (PWC) 3.1 Introduction For AT32F435/437 series, its operating voltage supply is 2.6 V ~ 3.6 V, with a temperature range of -40~+105 °C. To reduce power consumption, this series provides three types of power saving modes, including Sleep, Deepsleep and Standby modes so as to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
  • Page 64: Power Voltage Monitor (Pvm)

    AT32F435/437 Series Reference Manual Figure 3-2 Power-on reset/Low voltage reset waveform hysteresis Temporization tRESTTEMPO Reset 3.4 Power voltage monitor (PVM) The PVM is used to monitor the power supply variations. It is enabled by setting the PVMEN bit in the power control register (PWC_CTRL), and the threshold value for voltage monitor is selected with the PVMSEL[2: 0].
  • Page 65: 3.6 Power Saving Modes

    AT32F435/437 Series Reference Manual VDD/VDDA domain VDD/VDDA domain includes VDD domain and VDDA domain. The VDD domain contains I/O circuit, power-saving mode wakeup circuit, watchdog timer (WDT), power-on reset/low voltage reset (POR/LVR), LDO and all PAD circuits other than PC13, PC14 and PC15. The VDDA domain contains DAC/ADC (DA/AD converters), temperature sensor and so on.
  • Page 66 AT32F435/437 Series Reference Manual mode as soon as the system exits the lowest-priority interrupt service routine. In Sleep mode, all clocks and LDO work normally except CPU clocks (stopped), and all I/O pins keep the same state as in Run mode. The LDO provides a 1.2 V power (for CPU core, memory and embedded peripherals) as it is in normal power consumption mode.
  • Page 67: 3.7 Pwc Registers

    AT32F435/437 Series Reference Manual disabled. The whole 1.2 V domain, PLL, HICK and HEXT oscillators are also powered off. SRAM and register contents are lost. Only registers in the battery powered domain and standby circuitry remain supplied. The Standby mode is entered by the following procedures: –...
  • Page 68: Power Control Register (Pwc_Ctrl)

    AT32F435/437 Series Reference Manual 3.7.1 Power control register (PWC_CTRL) Name Reset value Type Description Kept at its default value. Bit 31: 9 Reserved 0x000000 resd Battery powered domain write enable 0: Disabled 1: Enabled Bit 8 BPWEN Note: After reset, the battery powered domain write access is disabled.
  • Page 69: Ldo Output Voltage Select Register (Pwc_Ldoov)

    AT32F435/437 Series Reference Manual 1: Device is in Standby mode Note: This bit is set by hardware (enter Standby mode) and cleared by POR/LVR or by setting the CLSEF bit. Standby wake-up event flag 0: No wakeup event occurred 1: A wakeup event occurred Note: This bit is set by hardware (on a wakeup event), and cleared by POR/LVR or by setting the CLSWEF bit.
  • Page 70: Clock And Reset Manage (Crm)

    HICK clock is 48 MHz. Although it is less accurate, its startup time is shorter than the HEXT crystal oscillator. The HICK clock frequency of each device is calibrated by ARTERY to 1% accuracy (25°C) in factory. The factory calibration value is loaded in the HICKCAL[7: 0] bit of the clock control register. The 2023.08.02...
  • Page 71: System Clock

    AT32F435/437 Series Reference Manual RC oscillator speed may be affected by voltage or temperature variations. Thus the HICK frequency can be trimmed using the HICKTRIM[5: 0] bit in the clock control register. The HICK clock signal is not released until it becomes stable. PLL clock ...
  • Page 72: Clock Fail Detector

    AT32F435/437 Series Reference Manual ERTC clock, the ERTC is not affected when the VDD is powered off. If the HEXT or LICK is selected as an ERTC clock, the ERTC state is not guaranteed when both HEXT and LICK are powered off. Watchdog is clocked by LICK oscillator.
  • Page 73 AT32F435/437 Series Reference Manual powered domain; the power-on reset, low-voltage reset or reset generated when exiting Standby mode sets all registers to their reset values except the battery powered domain registers. 2023.08.02 Page 73 Rev 2.05...
  • Page 74: Battery Powered Domain Reset

    AT32F435/437 Series Reference Manual Figure 4-2 System reset circuit Pulse generator (Min 20 µs) NRST CTRL NRST reset Filter System WDT reset reset WWDT reset CPU software reset Low-power management reset standby return reset 4.2.2 Battery powered domain reset Battery powered domain has two specific reset sources: ...
  • Page 75: Clock Control Register (Crm_Ctrl)

    AT32F435/437 Series Reference Manual 4.3.1 Clock control register (CRM_CTRL) Name Reset value Type Description Bit 30: 26 Reserved 0x00 resd Kept at its default value. PLL clock stable This bit is set by hardware after PLL is ready. Bit 25 PLLSTBL 0: PLL clock is not ready.
  • Page 76: Pll Clock Configuration Register (Crm_Pllcfg)

    AT32F435/437 Series Reference Manual High speed internal clock enable This bit is set and cleared by software. It can also be set by hardware when exiting Standby or Deepsleep mode. When a HEXT clock failure occurs. This bit can also be set. When Bit 0 HICKEN the HICK is used as the system clock, this bit cannot be...
  • Page 77: Clock Configuration Register (Crm_Cfg)

    AT32F435/437 Series Reference Manual 4.3.3 Clock configuration register (CRM_CFG) Access: 0 to 2 wait states. 1 or 2 wait states are inserted only when the access occurs during a clock source switch. Name Reset value Type Description Clock output2 selection 1 This field is set and cleared by software.
  • Page 78 AT32F435/437 Series Reference Manual APB2 division The divided HCLK is used as APB2 clock. 0xx: not divided 100: divided by 2 Bit 15: 13 APB2DIV 101: divided by 4 110: divided by 8 111: divided by 16 Note: The software must set these bits correctly to ensure that the APB2 clock frequency does not exceed 144 MHz.
  • Page 79: Clock Interrupt Register (Crm_Clkint)

    AT32F435/437 Series Reference Manual 4.3.4 Clock interrupt register (CRM_CLKINT) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value. Clock failure detection flag clear Writing 1 by software to clear CFDF.
  • Page 80: Apb Peripheral Reset Register1 (Crm_Apbrst1)

    AT32F435/437 Series Reference Manual PLL stable flag Set by hardware. Bit 4 PLLSTBLF 0: PLL is not ready. 1: PLL is ready. HEXT stable flag Set by hardware. Bit 3 HEXTSTBLF 0: HEXT is not ready. 1: HEXT is ready. HICK stable flag Set by hardware.
  • Page 81: Apb Peripheral Reset Register2 (Crm_Apbrst2)

    AT32F435/437 Series Reference Manual IO port E reset Bit 4 GPIOERST 0: Does not reset IO port E 1: Reset IO port E IO port D reset Bit 3 GPIODRST 0: Does not reset IO port D 1: Reset IO port D IO port C reset Bit 2 GPIOCRST...
  • Page 82 AT32F435/437 Series Reference Manual 1: Reset UART8 UART7 reset Bit 30 UART7RST 0: Does not reset UART7 1: Reset UART7 DAC interface reset Bit 29 DACRST 0: Does not reset DAC interface 1: Reset DAC interface Power interface reset Bit 28 PWCRST 0: Does not reset Power interface 1: Reset Power interface...
  • Page 83: Apb2 Peripheral Reset Register (Crm_Apb2Rst)

    AT32F435/437 Series Reference Manual Timer6 reset Bit 4 TMR6RST 0: Does not reset Timer6 1: Reset Timer6 Timer5 reset Bit 3 TMR5RST 0: Does not reset Timer5 1: Reset Timer5 Timer4 reset Bit 2 TMR4RST 0: Does not reset Timer4 1: Reset Timer4 Timer3 reset Bit 1...
  • Page 84: Apb Peripheral Clock Enable Register1 (Crm_Ahben1)

    AT32F435/437 Series Reference Manual 0: Does not reset TMR1 1: Reset TMR1 4.3.10 APB peripheral clock enable register1 (CRM_AHBEN1) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value. OTGFS2 clock enable 0: Disabled Bit 29...
  • Page 85: Apb Peripheral Clock Enable Register2 (Crm_Ahben2)

    AT32F435/437 Series Reference Manual IO port D clock enable Bit 3 GPIODEN 0: Disabled 1: Enabled IO port C clock enable Bit 2 GPIOCEN 0: Disabled 1: Enabled IO port B clock enable Bit 1 GPIOBEN 0: Disabled 1: Enabled IO port A clock enable Bit 0 GPIOAEN...
  • Page 86 AT32F435/437 Series Reference Manual UART7 clock enable Bit 30 UART7EN 0: Disabled 1: Enabled DAC interface clock enable Bit 29 DACEN 0: Disabled 1: Enabled Power interface clock enable Bit 28 PWCEN 0: Disabled 1: Enabled Bit 27 Reserved resd Kept at its default value.
  • Page 87: Apb2 Peripheral Clock Enable Register (Crm_Ahb2En)

    AT32F435/437 Series Reference Manual Timer13 clock enable Bit 7 TMR13EN 0: Disabled 1: Enabled Timer12 clock enable Bit 6 TMR12EN 0: Disabled 1: Enabled Timer7 clock enable Bit 5 TMR7EN 0: Disabled 1: Enabled Timer6 clock enable Bit 4 TMR6EN 0: Disabled 1: Enabled Timer5 clock enable...
  • Page 88: 4.3.15 Apb Peripheral Clock Enable In Low Power Mode Register1

    AT32F435/437 Series Reference Manual SPI4 clock enable Bit 13 SPI4EN 0: Disabled 1: Enabled SPI1 clock enable Bit 12 SPI1EN 0: Disabled 1: Enabled Bit 11 Reserved resd Kept at its default value. ADC3 interface clock enable Bit 10 ADC3EN 0: Disabled 1: Enabled ADC2 interface clock enable...
  • Page 89: 4.3.16 Apb Peripheral Clock Enable In Low Power Mode Register2

    AT32F435/437 Series Reference Manual DMA2 clock enable in sleep mode Bit 24 DMA2LPEN 0: Disabled 1: Enabled Bit 23 Reserved resd Kept at its default value. DMA1 clock enable in sleep mode Bit 22 DMA1LPEN 0: Disabled 1: Enabled EDMA clock enable in sleep mode Bit 21 EDMALPEN 0: Disabled...
  • Page 90: 4.3.17 Apb Peripheral Clock Enable In Low Power Mode Register3

    AT32F435/437 Series Reference Manual Bit 6: 1 Reserved 0x00 resd Kept at its default value. DVP clock enable in sleep mode Bit 0 DVPLPEN 0: Disabled 1: Enabled 4.3.17 APB peripheral clock enable in low power mode register3 (CRM_AHBLPEN3) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type...
  • Page 91: 4.3.19 Apb2 Peripheral Clock Enable In Low Power Mode Register

    AT32F435/437 Series Reference Manual 0: Disabled 1: Enabled USART3 clock enable in sleep mode Bit 18 USART3LPEN 0: Disabled 1: Enabled USART2 clock enable in sleep mode Bit 17 USART2LPEN 0: Disabled 1: Enabled Bit 16 Reserved resd Kept at its default value. SPI3 clock enable in sleep mode Bit 15 SPI3LPEN...
  • Page 92: Battery Powered Domain Control Register (Crm_Bpdc)

    AT32F435/437 Series Reference Manual 0: Disabled 1: Enabled Timer10 clock enable in sleep mode Bit 17 TMR10LPEN 0: Disabled 1: Enabled Timer9 clock enable in sleep mode Bit 16 TMR9LPEN 0: Disabled 1: Enabled Bit 15 Reserved resd Kept at its default value. SCFG clock enable in sleep mode Bit 14 SCFGLPEN...
  • Page 93: Control/Status Register (Crm_Ctrlsts)

    AT32F435/437 Series Reference Manual Bit 14: 10 Reserved 0x00 resd Kept at its default value. eRTC clock selection Once the ERTC clock source is selected, it cannot be changed until the BPDRST bit is reset. Bit 9: 8 eRTCSEL 00: No clock 01: LEXT 10: LICK 11: Divided HEXT (with the ERTC_DIV bit in the CRM_CFG)
  • Page 94: Additional Register1 (Crm_Misc1)

    AT32F435/437 Series Reference Manual Bit 25 Reserved resd Kept at its default value. Reset flag clear Cleared by writing 1 through software. Bit 24 RSTFC 0: No effect 1: Clear the reset flag. Bit 23: 2 Reserved 0x000000 resd Kept at its default value. LICK stable Bit 1 LICKSTBL...
  • Page 95: Additional Register2 (Crm_Misc2)

    AT32F435/437 Series Reference Manual This bit is used to select HICK or HICK /6. If the HICK/6 is selected, the clock frequency is 8 MHz. Otherwise, the clock frequency is 48 MHz. 0: HICK/6 1: HICK Note: When HICK is used as PLL clock source, do not modify HICKDIV while PLL is enabled.
  • Page 96: Flash Memory Controller (Flash)

    AT32F435/437 Series Reference Manual 5 Flash memory controller (FLASH) 5.1 FLASH introduction Flash memory is divided into three parts: main Flash memory, information block and Flash memory registers.  Main Flash memory is up to 4032 KB, including bank 1 and bank 2. Information block consists of 16 KB boot loader and the user system data area.
  • Page 97: Table 5-2 Flash Memory Architecture (1024 K)

    AT32F435/437 Series Reference Manual Main Flash memory (1024 KB) is divided into bank 1 and bank 2 with 512 KB in each. Each bank is sub- divided into 8 blocks that include 32 sectors in each, and 2 KB per sector. User system data area is 512 B.
  • Page 98: Table 5-4 Flash Memory Architecture (256 K)

    AT32F435/437 Series Reference Manual Main Flash memory (256 KB) has only bank 1, which is divided into 4 blocks that include 32 sectors in each, and 2 K per sector. User system data area is 512 B. Table 5-4 Flash memory architecture (256 K) Bank Name Address range...
  • Page 99 AT32F435/437 Series Reference Manual Standby mode 0: Reset occurs when entering Deepsleep mode Bit 1 (nDEPSLP_RST) 1: No reset occurs when entering Deepsleep mode 0: Watchdog is enabled Bit 0 (nWDT_ATO_EN) 1: Watchdog is disabled [31: 24] nSSB[7: 0]: Inverse code of SSB[7: 0] Data0[7: 0]: User data 0 (It is stored in the FLASH_USD[17:10] [7: 0] register)
  • Page 100 AT32F435/437 Series Reference Manual 0: Erase/write protection is enabled 1: Erase/write protection is disabled [15: 8] nEPP6[7: 0]: Inverse code of EPP6[7: 0] EPP7[7:0]: Flash erase/write protection byte 7 (stored in the FLASH_EPPS1[31: 24]) [23: 16] Bit 7 is reserved. Bit 6:0 is used to protect the 3201st~4032nd KB of main Flash memory.
  • Page 101: Table 5-6 Extended System Options

    AT32F435/437 Series Reference Manual 2. For 4032 KB Flash memory and 448 KB Flash memory, there are 2048 bytes of user system data, ranging from 0x1FFF_C000 to 0x1FFF_CFFF, including 2012 bytes of user data. 3. For 448 KB Flash memory, only EPP0[7:0], EPP1[7:0], EPP2[7:0], EPP3[7:0] and EPP4[2:0] bits are configurable, and other EPPx bits must be fixed to 1.
  • Page 102: 5.2 Flash Memory Operation

    AT32F435/437 Series Reference Manual 5.2 Flash memory operation 5.2.1 Unlock/lock After reset, Flash memory is protected, by default. FLASH_CTRLx cannot be written. Write and erase operation can be performed only when the Flash memory is unlocked. Unlock procedure: Flash memory block can be unlocked by writing KEY1 (0x45670123) and KEY2 (0xCDEF89AB) to the FLASH_UNLOCKx register.
  • Page 103: Figure 5-1 Flash Memory Sector Erase Process

    AT32F435/437 Series Reference Manual Flash memory sector erase process Figure 5-1 Start Check the OBF bit in FLASH_STSx OBF = 0 ? Write the erased sector address to FLASH_ADDRx Set SECERS = 1 and ERSTR =1 in FLASH_CTRLx Check the OBF bit in FLASH_STSx OBF = 0 ? Read EPPERR bit and ODF bit in FLASH_STSx...
  • Page 104: Figure 5-2 Flash Memory Block Erase Process

    AT32F435/437 Series Reference Manual Flash memory block erase process Figure 5-2 Start Check the OBF bit in FLASH_STSx OBF = 0 ? Write the erased block address to FLASH_ADDRx Set BLKERS = 1 and ERSTR =1 in FLASH_CTRLx Check the OBF bit in FLASH_STSx OBF = 0 ? Read EPPERR bit and ODF bit in FLASH_STSx...
  • Page 105: Programming Operation

    AT32F435/437 Series Reference Manual Flash memory mass erase process Figure 5-3 Start Check the OBF bit in FLASH_STSx OBF = 0? Set BANKERS = 1 and ERSTR =1 in FLASH_CTRLx Check the OBF bit in FLASH_STSx OBF = 0 ? Read EPPERR bit and ODF bit in FLASH_STSx 5.2.3...
  • Page 106: Read Operation

    AT32F435/437 Series Reference Manual Figure 5-4 Flash memory programming process Start Check the OBF bit in FLASH_STSx OBF = 0? Set the FPRGM bit = 1 in FLASH_CTRLx Write word/half-word/byte (32bits/16 bits/8bits) data Check the OBF bit in FLASH_STSx OBF = 0? Read EPPERR bit、PRGMERR bit and ODF bit in FLASH_STSx 5.2.4...
  • Page 107: Erase Operation

    AT32F435/437 Series Reference Manual Lock procedure: User system data area is locked by clearing the USDULKS bit in the FLASH_CTRL register by software. 5.3.2 Erase operation Erase operation must be done before programming. User system data area can perform erase operation independently.
  • Page 108: Programming Operation

    AT32F435/437 Series Reference Manual 5.3.3 Programming operation The User system data area can be programmed with 16 bits at a time. The following process is recommended:  Check the OBF bit in the FLASH_STS register to confirm that there is no other programming operation in progress;...
  • Page 109: Read Operation

    AT32F435/437 Series Reference Manual 5.3.4 Read operation User system data area can be accessed through AHB bus of the CPU. 5.4 Flash memory protection Flash memory includes access and erase/program protection. 5.4.1 Access protection When the contents in the nFAP and FAP byte are different from 0x5A and 0xA5, the Flash memory will activate access protection after a system reset.
  • Page 110: 5.6 Flash Memory Registers

    AT32F435/437 Series Reference Manual Advantages of security library: Security library is protected by codes so that solution providers can program core algorithm into this area; Security library cannot be read or deleted (including ISP/IAP/SWD) but only executed unless code defined by the solution provider is keyed in; The rest of the area can be used for secondary development by solution providers;...
  • Page 111: Flash Performance Select Register (Flash_Psr)

    AT32F435/437 Series Reference Manual Table 5-8 Flash memory interface—Register map and reset value Register Offset Reset value FLASH_PSR 0x00 0x0000 0330 FLASH_UNLOCK 0x04 0xXXXX XXXX FLASH_USD_UNLOCK 0x08 0xXXXX XXXX FLASH_STS 0x0C 0x0000 0000 FLASH_CTRL 0x10 0x0000 0080 FLASH_ADDR 0x14 0x0000 0000 FLASH_USD 0x1C 0x03FF FFFC...
  • Page 112: Flash Unlock Register (Flash_Unlock)

    AT32F435/437 Series Reference Manual 5.6.2 Flash unlock register (FLASH_UNLOCK) Only used in Flash memory bank 1. Abbr. Reset value Type Description Unlock key value Bit 31: 0 UKVAL 0xXXXX XXXX wo This is used to unlock Flash memory bank 1. Note: All these bits are write-only, and return 0 when being read.
  • Page 113: Flash Address Register (Flash_Addr)

    AT32F435/437 Series Reference Manual hardware after unlock, indicating that erase/program operation to Flash memory is allowed. Writing “1” can re- lock Flash memory operations. Erase start An erase operation is triggered when this bit is set. This bit Bit 6 ERSTR is cleared by hardware after the completion of the erase operation.
  • Page 114: Erase/Program Protection Status Register0 (Flash_Epps0)

    AT32F435/437 Series Reference Manual 5.6.8 Erase/program protection status register0 (FLASH_EPPS0) Register Reset value Type Description Erase/Program protection status This register reflects the erase/program protection byte Bit 31: 0 EPPS 0xFFFF FFFF ro status in the loaded user system data. 5.6.9 Erase/program protection status register1 (FLASH_EPPS1) Register...
  • Page 115 AT32F435/437 Series Reference Manual Kept at its default value Bit 9,8 Reserved resd Operation lock This bit is set by default, indicating that Flash memory is protected against operations. This bit is cleared by Bit 7 OPLK hardware after unlock, indicating that erase/program operation to Flash memory is allowed.
  • Page 116 AT32F435/437 Series Reference Manual 5.6.16 Flash security library status register2 (SLIB_STS2) Only used in Flash security library. Register Reset value Type Description Kept at its default value Bit 31: 16 Reserved 0x0000 resd sLib instruction start sector 0: Sector 0 1: Sector 1 Bit 15: 0 SLIB_INST_SS...
  • Page 117 AT32F435/437 Series Reference Manual When this bit is set, it indicates that sLib-related setting registers can be configured. Security library password ok Bit 1 SLIB_PWD_OK This bit is set by hardware when the password is correct. Security library password error This bit is set by hardware when the password is incorrect and the setting value of the password clear register is different from 0xFFFF FFFF.
  • Page 118 AT32F435/437 Series Reference Manual start sector. 0: Sector 0 1: Sector 1 2: Sector 2 … 0xFFFF: Non-sLib instruction 5.6.24 Security library unlock register (SLIB_UNLOCK) Only used for Flash security library unlock setting. Register Reset value Type Description Security library unlock key value Bit 31: 0 SLIB_UKVAL 0x0000 0000...
  • Page 119: Figure 6-1 Gpio Basic Structure

    AT32F435/437 Series Reference Manual 6 GPIOs and IOMUX 6.1 Introduction AT32F435 series supports up to 116 bidirectional I/O pins, which are grouped as eight categories, namely PA0-PA15, PB0-PB15, PC0-PC15, PD0-PD15, PE0-PE15, PF0-PF15, PG0-PG15 and PH0- PH3. Each of these pins features communication, control and data collection. In addition, their main features also include: ...
  • Page 120 AT32F435/437 Series Reference Manual  PA14/JTCK in multiplexed pull-down mode; PB3/TDO in multiplexed mode without pull-up/pull-down capability  6.2.3 General-purpose input configuration Mode IOMC PUPD Floating input Pull-down input Pull-up input When I/O port is configured as input:  Get I/O states by reading the input data register. Floating input, pull-up/pull-down input is configurable ...
  • Page 121: Figure 6-2 Iomux Structure

    AT32F435/437 Series Reference Manual 6.2.6 I/O port protection Locking mechanism can freeze the I/O configuration for the purpose of protection. When LOCK is applied to a port bit, its configuration cannot be modified until the next reset or power on. 6.2.7 IOMUX structure Several peripheral functions can be mapped on each IO pin.
  • Page 122: Table 6-1 Port A Multiplexed Function Configuration With Gpioa_Mux* Register

    AT32F435/437 Series Reference Manual  GPIO pin output is disabled. 6.2.9 IOMUX input/output The multiplexed function of each IO port line is configured through the GPIOx_MUXL (for pin 0 to 7) or GPIOx_MUXH (for pin 8 to 15) register. Table 6-1 Port A multiplexed function configuration with GPIOA_MUX* register MUX0 MUX1 MUX2...
  • Page 123 AT32F435/437 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 name UART4_TX EMAC_MII_CRS EVENTOUT EMAC_MII_RX_CLK UART4_RX QSPI1_IO3 EVENTOUT EMAC_RMII_REF_CLK SDIO2_CK EMAC_MDIO XMC_D4 EVENTOUT QSPI2_IO3 SDIO2_CMD EMAC_MII_COL XMC_D5 EVENTOUT OTG2_SO USART6_TX SDIO2_D4 SDIO2_D0 DVP_HSYNC XMC_D6 EVENTOUT USART6_RX QSPI2_IO2 SDIO2_D5 SDIO2_D1 XMC_D7 EVENTOUT...
  • Page 124: Table 6-2 Port B Multiplexed Function Configuration With Gpiob_Mux* Register

    AT32F435/437 Series Reference Manual Table 6-2 Port B multiplexed function configuration with GPIOB_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 SPI3_MOSI TMR1_CH2C TMR3_CH3 TMR8_CH2C I2S1_MCK USART2_RX I2S3_SD SPI2_SCK TMR1_CH3C TMR3_CH4 TMR8_CH3C I2S2_CK SPI3_MOSI TMR2_CH4 TMR20_CH1 I2C3_SMBA I2S3_SD JTDO SPI1_SCK SPI3_SCK TMR2_CH2...
  • Page 125 AT32F435/437 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 QSPI1_IO USART3_CK QSPI2_IO0 EMAC_MII_RXD2 SDIO1_D1 EVENTOUT QSPI2_S USART3_RTS_DE QSPI1_SCK EMAC_MII_RXD3 SDIO1_D2 EVENTOUT SDIO1_C QSPI1_SCK EVENTOUT QSPI1_IO UART7_RX DVP_D4 EVENTOUT UART7_TX SDIO1_D0 DVP_D5 EVENTOUT XMC_SD UART5_RX CAN2_RX EMAC_PPS_OUT DVP_D10 SDIO1_D3 EVENTOUT CKE1...
  • Page 126: Table 6-3 Port C Multiplexed Function Configuration With Gpioc_Mux* Register

    AT32F435/437 Series Reference Manual Table 6-3 Port C multiplexed function configuration with GPIOC_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 I2C3_SCL SPI3_MOSI SPI2_MOSI I2C3_SDA I2S3_SDEXT I2S2_SDEXT TMR20_CH2 SPI2_MISO I2S2_SDEXT SPI2_MOSI I2S2_SDEXT TMR9_CH I2S1_MCK USART3_TX TMR9_CH I2C1_SMBA USART3_RX TMR8_CH TMR3_CH1 I2C1_SCL I2S2_MCK...
  • Page 127 AT32F435/437 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 UART7_TX SDIO2_D0 XMC_SDNWE EVENTOUT UART7_RX SDIO2_D1 EMAC_MDC EVENTOUT UART8_TX SDIO2_D2 EMAC_MII_TXD2 XMC_SDCS0 XMC_NWE EVENTOUT EMAC_MII_TX_C UART8_RX QSPI2_IO1 SDIO2_D3 XMC_SDCKE0 XMC_A0 EVENTOUT EMAC_MII_RXD0 QSPI1_IO2 EMAC_RMII_RX XMC_SDCS0 SDIO2_CK XMC_NE4 EVENTOUT EMAC_MII_RXD1 QSPI1_IO3 EMAC_RMII_RX...
  • Page 128: Table 6-4 Port D Multiplexed Function Configuration With Gpiod_Mux* Register

    AT32F435/437 Series Reference Manual Table 6-4 Port D multiplexed function configuration with GPIOD_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 SPI3_MOSI SPI2_CS SPI4_MISO I2S3_SDEXT I2S2_WS SPI2_SCK SPI2_CS I2S2_CK I2S2_WS TMR3_EXT USART3_RTS_DE SPI2_SCK SPI2_MISO USART2_CTS I2S2_CK SPI2_MOSI USART2_RTS_DE I2S2_SDEXT USART2_TX SPI3_MOSI USART2_RX...
  • Page 129 AT32F435/437 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 CAN1_RX XMC_A5 XMC_D2 EVENTOUT CAN1_TX XMC_A6 XMC_D3 EVENTOUT UART5_RX XMC_A7 SDIO1_CMD DVP_D11 XMC_NWE EVENTOUT QSPI1_SCK XMC_A8 XMC_CLK DVP_D5 EVENTOUT XMC_A9 XMC_NOE EVENTOUT XMC_A10 XMC_NWE EVENTOUT XMC_A11 XMC_NWAIT DVP_D10 EVENTOUT XMC_NE1 XMC_A12...
  • Page 130: Table 6-5 Port E Multiplexed Function Configuration With Gpioe_Mux* Register

    AT32F435/437 Series Reference Manual Table 6-5 Port E multiplexed function configuration with GPIOE_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 TMR4_EX TMR20_EXT TMR1_CH2C TMR20_CH4 TMR3_EX SPI4_SCK TMR20_CH1 I2S4_CK TMR3_CH TMR20_CH2 CLKOUT TMR3_CH SPI4_CS TMR20_CH1C I2S4_WS TMR3_CH TMR9_CH SPI4_MISO TMR20_CH2C TMR3_CH TMR9_CH...
  • Page 131 AT32F435/437 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 XMC_LB/XM UART8_RX DVP_D2 EVENTOUT C_SDDQML XMC_UB/XM UART8_TX DVP_D3 EVENTOUT C_SDDQMH QSPI1_IO2 XMC_SDNCAS EMAC_MII_TXD3 XMC_A23 EVENTOUT XMC_A19 DVP_D9 EVENTOUT XMC_A20 DVP_D4 EVENTOUT XMC_A21 DVP_D6 EVENTOUT XMC_SDNRAS XMC_A22 DVP_D7 EVENTOUT UART7_RX QSPI2_IO0 XMC_D4...
  • Page 132: Table 6-6 Port F Multiplexed Function Configuration With Gpiof_Mux* Register

    AT32F435/437 Series Reference Manual Table 6-6 Port F multiplexed function configuration with GPIOF_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 I2C2_SDA I2C2_SCL TMR20_CH3 I2C2_SMBA TMR20_CH4 TMR20_CH1C TMR20_CH2C TMR20_CH4 TMR10_CH1 TMR20_BRK TMR11_CH1 TMR20_BRK PF10 TMR1_EXT TMR5_CH4 PF11 TMR20_EXT TMR8_EXT PF12 TMR20_CH1 TMR8_BRK...
  • Page 133 AT32F435/437 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 XMC_A0 EVENTOUT XMC_A1 EVENTOUT XMC_A2 EVENTOUT XMC_A3 EVENTOUT XMC_A4 EVENTOUT XMC_A5 EVENTOUT UART7_RX QSPI1_IO3 XMC_NIORD EVENTOUT UART7_TX QSPI1_IO2 XMC_NREG EVENTOUT TMR13_CH1 QSPI1_IO0 XMC_NIOWR EVENTOUT TMR14_CH1 QSPI1_MOSI_IO1 XMC_CD EVENTOUT PF10 QSPI1_SCK XMC_INTR...
  • Page 134: Table 6-7 Port G Multiplexed Function Configuration With Gpiog_Mux* Register

    AT32F435/437 Series Reference Manual Table 6-7 Port G multiplexed function configuration with GPIOG_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 TMR20_CH1C SPI1_MISO SPI1_MOSI TMR20_CH2C I2S1_SDEXT TMR20_CH3C TMR20_BRK TMR20_EXT QSPI2_CS PG10 QSPI2_IO2 SPI4_SCK PG11 QSPI2_IO3 I2S4_CK PG12 QSPI2_IO1 SPI4_MISO SPI4_MOSI PG13 QSPI2_SCK...
  • Page 135 AT32F435/437 Series Reference Manual MUX1 MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX15 CAN1_RX XMC_A10 EVENTOUT CAN1_TX XMC_A11 EVENTOUT XMC_A12 EVENTOUT XMC_A13 EVENTOUT XMC_A14 EVENTOUT XMC_SDBA0 XMC_A15 EVENTOUT XMC_SDBA1 QSPI1_CS XMC_INT2 DVP_D12 EVENTOUT USART6_CK XMC_INT3 DVP_D13 EVENTOUT USART6_RTS_DE EMAC_PPS_OUT XMC_SDCLK EVENTOUT XMC_NE2 DVP_VSY USART6_RX...
  • Page 136: Table 6-8 Port H Multiplexed Function Configuration With Gpioh_Mux* Register

    AT32F435/437 Series Reference Manual Table 6-8 Port H multiplexed function configuration with GPIOH_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 I2C1_SDA I2C1_SCL TMR5_CH1 I2C2_SCL TMR5_CH2 I2C2_SDA MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 EVENTOUT EVENTOUT UART4_RX QSPI1_IO0 EVENTOUT UART4_TX QSPI1_IO1...
  • Page 137: Table 6-10 Gpio Register Map And Reset Values

    AT32F435/437 Series Reference Manual CRM_CTRL[18]=0 Note: Either PA0 or PC13 cannot be used as TAMPER_BPR and WKUP of PWC simultaneously. 6.2.12 External interrupt/wake-up lines Each pin can be used as an external interrupt input. The corresponding pin should be configured as input mode.
  • Page 138 AT32F435/437 Series Reference Manual 6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..H) Address offset: 0x08 Reset values: 0x0000 00C0 for port B 0x00000000 for other ports Register Reset value Type Description GPIOx drive capability (y=0…15) This field is used to configure the IO port drive capability. ODRVy 0x0000 0000 x0: Normal sourcing/sinking strength...
  • Page 139 AT32F435/437 Series Reference Manual 6.3.8 GPIO write protection register (GPIOx_WPR) (x=A..H) Register Reset value Type Description Bit 31: 17 Reserved 0x0000 resd Kept at its default value. Write protect sequence Write protect enable sequence bit and WPEN bit must be enabled at the same time to achieve write protection for some I/O bits.
  • Page 140 AT32F435/437 Series Reference Manual 6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..H) Register Reset value Type Description Multiplexed function select for GPIOx pin y (y=8…15) This field is used to configure multiplexed function IOs 0000: MUX0 0001: MUX1 0010: MUX2 0011: MUX3 0100: MUX4 0101: MUX5...
  • Page 141: Table 7-1 Scfg Register Map And Reset Values

    AT32F435/437 Series Reference Manual 7 System configuration controller (SCFG) 7.1 Introduction This device contains a set of system configuration register. The system configuration controller is mainly used to:  Manage the external interrupts connected to the GPIOs Control the memory mapping mode ...
  • Page 142 AT32F435/437 Series Reference Manual as that of the BOOT0 and BOOT1 pins. After changing this field, the user can decide which of the following memory to be mapped at 0x0000 0000. 000: Main Flash memory mapped at 0x0000 0000 001: Boot loader memory mapped at 0x0000 0000 010: XMC BANK1 mapped at 0x0000 0000 011: Embedded SRAM mapped at 0x0000 0000 100: XMC SDRAM BANK1 mapped at 0x0000 0000...
  • Page 143 AT32F435/437 Series Reference Manual 0000: GPIOA pin1 0001: GPIOB pin1 0010: GPIOC pin1 0011: GPIOD pin1 0100: GPIOE pin1 0101: GPIOF pin1 0110: GPIOG pin1 0111: GPIOH pin1 Others: Reserved EXINT0 input source configuration These bits are used to select the input source for the EXINT0 external interrupt.
  • Page 144 AT32F435/437 Series Reference Manual 0111: GPIOH pin6 Others: Reserved EXINT5 input source configuration These bits are used to select the input source for the EXINT5 external interrupt. 0000: GPIOA pin5 0001: GPIOB pin5 0010: GPIOC pin5 Bit 7: 4 EXINT5 0x0000 0011: GPIOD pin5 0100: GPIOE pin5...
  • Page 145 AT32F435/437 Series Reference Manual 0010: GPIOC pin10 0011: GPIOD pin10 0100: GPIOE pin10 0101: GPIOF pin10 0110: GPIOG pin10 0111: GPIOH pin10 Others: Reserved EXINT9 input source configuration These bits are used to select the input source for the EXINT9 external interrupt. 0000: GPIOA pin9 0001: GPIOB pin9 0010: GPIOC pin9...
  • Page 146 AT32F435/437 Series Reference Manual EXINT14 input source configuration These bits are used to select the input source for the EXINT14 external interrupt. 0000: GPIOA pin14 0001: GPIOB pin14 0010: GPIOC pin14 Bit 11: 8 EXINT14 0x0000 0011: GPIOD pin14 0100: GPIOE pin14 0101: GPIOF pin14...
  • Page 147 AT32F435/437 Series Reference Manual 7.2.7 SCFG ultra high sourcing/sinking strength (SCFG_UHDRV) Register Reset value Type Description Bit 31: 11 Reserved 0x0000 00 resd Kept at its default value PF15 Ultra high sourcing/sinking strength This bit is written by software to control the PF15 PAD sourcing/sinking strength.
  • Page 148 AT32F435/437 Series Reference Manual When this bit is set, the control bits of GPIOx_OTYPER&GPIOx_HDRV become invalid. PB9 Ultra high sourcing/sinking strength This bit is written by software to control the PB9 PAD sourcing/sinking strength. 0: Not active Bit 1 PB9_UH 1: Corresponding GPIO is switched to ultra-high sourcing/sinking strength When this bit is set, the control bits of...
  • Page 149: Figure 8-1 External Interrupt/Event Controller Block Diagram

    AT32F435/437 Series Reference Manual 8 External interrupt/Event controller (EXINT) 8.1 EXINT introduction EXINT consists of 23 interrupt lines EXINT_LINE[22:0], each of which can generate an interrupt or event by edge detection trigger or software trigger. EXINT can enable or disable an interrupt or event independently through software configuration, and utilizes different edge detection modes (rising edge, falling edge or both edges) as well as trigger modes (edge detection, software trigger or both triggers) to respond to the trigger source in order to generate an interrupt or event.
  • Page 150: Table 8-1 External Interrupt/Event Controller Register Map And Reset Value

    AT32F435/437 Series Reference Manual  Enable interrupt or event by setting EXINT_INTEN and EXINT_EVTEN register Generate software trigger by setting EXINT_SWTRG register (This is applied to only software  trigger interrupt) Interrupt clear procedure  Writing “1” to the EXINT_INTSTS register to clear the interrupts generated, and the corresponding bits in the EXINT_SWTRG register.
  • Page 151 AT32F435/437 Series Reference Manual 8.3.4 Polarity configuration register2 (EXINT_ POLCFG2) Register Reset value Type Description Bit 31: 23 Reserved 0x000 resd Forced to be 0 by hardware. Falling polarity configuration bit on line x These bits are used to select a falling edge to trigger an interrupt and event on line x.
  • Page 152: Figure 9-1 Dma Block Diagram

    AT32F435/437 Series Reference Manual 9 DMA controller (DMA) 9.1 Introduction Direct memory access (DMA) controller is designed for 32-bit MCU applications with the aim of enhancing system performance and reducing the generation of interrupts. There are two DMA controllers in the microcontroller. Each controller contains 7 DMA channels. Each channel manages memory access requests from one or more peripherals.
  • Page 153 AT32F435/437 Series Reference Manual 9.3 Function overview 9.3.1 DMA configuration 1. Set the peripheral address in the DMA_CxPADDR register The initial peripheral address for data transfer remains unchanged during transmission. 2. Set the memory address in the DMA_CxMADDR register The initial memory address for data transfer remains unchanged during transmission. 3.
  • Page 154: Figure 9-2 Re-Arbitrate After Request/Acknowledge

    AT32F435/437 Series Reference Manual 9.3.3 Arbiter When several channels are enabled simultaneously, the arbiter will restart arbitration after full data transfer by the master controller. The channel with very high priority waits until the channel of the master controller has completed data transfers before taking control of it. The master controller will re-arbitrate to serve other channels as long as the channel completes a single transfer based on the master controller priority.
  • Page 155: Figure 9-4 Pwidth: Half-Word, Mwidth: Word

    AT32F435/437 Series Reference Manual Figure 9-4 PW IDTH: half-word, MW IDTH: word AHB Read Sequence AHB Write Sequence HW3 HW2 HW1 HW0 W3 W2 W1 W0 word2 word0 word3 word1 Figure 9-5 PW IDTH: word, MW IDTH: byte AHB Read Sequence AHB Write Sequence Byte2 Byte0...
  • Page 156: Figure 9-6 Dmamux Block Diagram

    AT32F435/437 Series Reference Manual 9.4.1 DMAMUX functional overview The DMAMUX consists of a request generator and a request multiplexer. Each of the DMAMUX generator channel x has a GEN enable bit in the DMA_MUXGxCTR register. The SIGSEL bit is used to select the trigger input of the DMAMUX generator. Typically, the number of DMA requests equals GREQCNT + 1.
  • Page 157: Table 9-3 Flexible Dma1/Dma2 Request Mapping

    AT32F435/437 Series Reference Manual Table 9-3 Flexible DMA1/DMA2 request mapping DMAMUX DMAMUX DMAMUX DMAMUX Source Source Source Source request request request request DMA_MUXREQG1 33 UART5_TX TMR3_OVERFLOW 97 reserved DMA_MUXREQG2 34 reserved TMR3_TRIG reserved DMA_MUXREQG3 35 reserved TMR4_CH1 reserved DMA_MUXREQG4 36 ADC2 TMR4_CH2 reserved...
  • Page 158: Figure 9-7 Dmamux Request Synchronized Mode

    AT32F435/437 Series Reference Manual Table 9-4 DMAMUX EXINT LINE for trigger input and synchronized input EXINT EXINT EXINT EXINT Source Source Source Source LINE LINE LINE LINE exint_gpio[0] exint_gpio[8] DMA_MUXevt1 reserved exint_gpio[1] exint_gpio[9] DMA_MUXevt2 reserved exint_gpio[2] exint_gpio[10] DMA_MUXevt3 reserved exint_gpio[3] exint_gpio[11] DMA_MUXevt4 reserved...
  • Page 159: Figure 9-8 Dmamux Event Generation

    AT32F435/437 Series Reference Manual Figure 9-8 DMAMUX event generation Selected all_req[n] chx_mux_req SYNCEN EVTGEN mux_req_cnt mux_evtx SYNCEN = 0, EVTGEN = 1, REQCNT = 2 9.5 DMA registers Table 9-5 shows DMA register map and their reset values. These peripheral registers must be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits). Table 9-5 DMA register map and reset value Register...
  • Page 160 AT32F435/437 Series Reference Manual DMA_C6DTCNT 0x70 0x0000 0000 DMA_C6PADDR 0x74 0x0000 0000 DMA_C6MADDR 0x78 0x0000 0000 DMA_C7CTRL 0x80 0x0000 0000 DMA_C7DTCNT 0x84 0x0000 0000 DMA_C7PADDR 0x88 0x0000 0000 DMA_C7MADDR 0x8c 0x0000 0000 DMA_MUXSEL 0x100 0x0000 0000 DMA_MUXC1CTRL 0x104 0x0000 0000 DMA_MUXC2CTRL 0x108 0x0000 0000...
  • Page 161 AT32F435/437 Series Reference Manual Channel 6 half transfer event flag Bit 22 HDTF6 0: No half-transfer event occurred. 1: Half-transfer event occurred. Channel 6 transfer complete event flag Bit 21 FDTF6 0: No transfer complete event occurred. 1: Transfer complete event occurred. Channel 6 global event flag 0: No transfer error, half transfer or transfer complete event Bit 20...
  • Page 162 AT32F435/437 Series Reference Manual Channel 2 transfer complete event flag Bit 5 FDTF2 0: No transfer complete event occurred. 1: Transfer complete event occurred. Channel 2 global event flag 0: No transfer error, half transfer or transfer complete event Bit 4 occurred.
  • Page 163 AT32F435/437 Series Reference Manual Channel 5 half transfer flag clear Bit 18 HDTFC5 rw1c 0: No effect 1: Clear the HDTF5 flag in the DMA_STS register Channel 5 transfer complete flag clear Bit 17 FDTFC5 rw1c 0: No effect 1: Clear the FDTF5 flag in the DMA_STS register Channel 5 global interrupt flag clear 0: No effect Bit 16...
  • Page 164 AT32F435/437 Series Reference Manual Channel 1 global interrupt flag clear 0: No effect Bit 0 GFC1 rw1c 1: Clear the DTERRF1, HDTF1, FDTF1 and GF1 in the DMA_STS register 9.5.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…7) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type...
  • Page 165 AT32F435/437 Series Reference Manual 9.5.4 DMA channel-x number of data register (DMA_CxDTCNT) (x = 1…7) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. Number of data to transfer The number of data to transfer is from 0x0 to 0xFFFF.
  • Page 166 AT32F435/437 Series Reference Manual DMA request count These bits indicate the number of DMA requests sent to the DMA controller after synchronization is enabled, and/or Bit 23: 19 REQCNT 0x00 DMA request count before event output is generated. These bits are reserved only when both SYNCEN and EVTGEN bits are low.
  • Page 167 AT32F435/437 Series Reference Manual DMA request generation enable Bit 16 0: DMA request generation is disabled 1: DMA request generation is enabled Bit 15: 9 Reserved 0x00 resd Kept at its default value. Trigger overrun interrupt enable Bit 8 TRGOVIEN 0: Interrupt disabled 1: Interrupt enabled Bit 7: 5...
  • Page 168 AT32F435/437 Series Reference Manual 9.5.13 DMAMUX generator interrupt flag clear register (DMA_MUXGCLR) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Register Reset value Type Description Trigger overrun interrupt flag clear Bit 3: 0 TRGOVFC 0x00 rw1c...
  • Page 169: Figure 10-1 Crc Calculation Unit Block Diagram

    AT32F435/437 Series Reference Manual 10 CRC calculation unit (CRC) 10.1 CRC introduction The Cyclic Redundancy Check (CRC) is an independent peripheral with CRC check feature. It follows CRC32/MPEG-2 standard. The CRC_CTRL register is used to select output data toggle (word, REVOD=1) or input data toggle (byte, REVID=01;...
  • Page 170: Figure 10-2 Diagram Of Byte Reverse

    AT32F435/437 Series Reference Manual register. If f it is not the first data input, the initial value is the previously calculated result. CRC calculation. Dividing the input data by the generator polynominal (0x4C11DB7) using mod 2  division method produces a remainder, that is, CRC value. ...
  • Page 171 AT32F435/437 Series Reference Manual 10.3.3 Control register (CRC_CTRL) Register Reset value Type Description Bit 31: 8 Reserved 0x000000 resd Kept at its default value. Reverse output data Set and cleared by software. This bit is used to control Bit 7 REVOD resd whether or not to reverse output data.
  • Page 172: Figure 11-1 I C Bus Protocol

    AT32F435/437 Series Reference Manual 11 I C interface 11.1 I C introduction C (inter-integrated circuit) bus interface manages the communication between the microcontroller and serial I C bus. It supports master and slave modes, with up to 1 Mbit/s of communication speed (enhanced edition).
  • Page 173: Figure 11-2 I C Function Block Diagram

    AT32F435/437 Series Reference Manual 11.4 I C interface Figure 11-2 shows the block diagram of I C function. Figure 11-2 I C function block diagram I2CCLK Clock Control TIMEOUT_Frozen I2C_SCL_out Master clock generation CPU_Halt_en GPIO I2C_SCL Slave clock Digital I2C_SCL_in stretching noise filter Register...
  • Page 174 AT32F435/437 Series Reference Manual Slave address masking capability The Slave address 2 (OADDR2) is maskable, which is done by setting the ADDR2MASK[2: 0]. ― 0: Address bit [7: 1] ― 1: Address bit [7: 2] ― 2: Address bit [7: 3] ―...
  • Page 175: Figure 11-3 Setup And Hold Time

    AT32F435/437 Series Reference Manual  Address reception: The SCL clock is not stretched when the address received by slave matches the local address enabled (ADDRF=1 in the I2C_STS)  Data reception: If there is data to be read in the I2C_RXDT register before the next ACK signal, an overflow will occur, and the OUF bit will also be set in the I2C_STS register ...
  • Page 176: Table 11-1 I C Timing Specifications

    AT32F435/437 Series Reference Manual 0], SCLH[7: 0] and SCLL[7: 0] in the I2C_CLKCTRL register. SCL low: When the SCL low signal is detected, the internal SCLL counter starts counting until it reaches the SCLL value. At this point, the SCL line is released and become high. SCL high: When the SCL high signal is detected, the internal SCLH counter starts counting.
  • Page 177: Table 11-2 I 2 C Configuration Table

    AT32F435/437 Series Reference Manual ― Step 4: After the completion of the second 255-byte data transfer, the TCRLD is set in the I2C_STS register, and then set RLDEN=0 to disable reload mode before setting CNT[7:0]=90 for continuous transfer. There are two ways to stop the last data transfer (RLDEN=0, reload mode is disabled) ...
  • Page 178 AT32F435/437 Series Reference Manual Set the number of bytes to be transferred ― ≤255 bytes Disable reload mode by setting RLDEN=0 in the I2C_CTRL2 register Set CNT[7:0]=N in the I2C_CTRL2 register ― >255 bytes Enable reload mode by setting RLDEN=1 in the I2C_CTRL register Set CNT[7:0]=255 in the I2C_CTRL2 register Remaining bytes N=N-255 End of data transfer...
  • Page 179: Figure 11-4 I 2 C Master Transmission Flow

    AT32F435/437 Series Reference Manual is asserted in the I2C_STS register. The STOPF flag can be cleared by setting STOPC=1 in the I2C_CLR register, and then transfer stops When the host receives an NACK signal during transmission, then ACKFAIL is set in the I2C_STS register, and a STOP condition is sent to stop communication, whatever mode (either ASTOPEN=0 or ASTOPEN=1).
  • Page 180: Figure 11-5 Transfer Sequence Of I

    AT32F435/437 Series Reference Manual Figure 11-5 Transfer sequence of I C master transmitter I2C master transmitter N bytes Initial setting flow : 1. I2C_CTRL2_CNT = N 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL2_GENSTART = 1 Initial setting Address Data1 Data2...
  • Page 181: Figure 11-7 Transfer Sequence Of I

    AT32F435/437 Series Reference Manual Figure 11-7 Transfer sequence of I C master receiver I2C master receiver N bytes Initial setting flow : 1. I2C_CTRL2_CNT = N 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL2_GENSTART = 1 Initial setting Address Data1 Data2...
  • Page 182 AT32F435/437 Series Reference Manual 11.4.4 I C slave communication flow C clock initialization (by setting the I2C_CLKCTRL register) C clock divider: DIV[7: 0] ― I ― Data hold time (t ): SDAD[3: 0] H D ;D A T ― Data setup time (t ): SCLD[3: 0] S U ;D AT This register can be configured by means of Artery_I2C_Timing_Configuration tool.
  • Page 183 AT32F435/437 Series Reference Manual software, and then write the first data to the TXDT register, the TDBE is cleared ― Write operation through interrupts or DMA: Clear the TXDT register by setting the TDBE bit through software, then set the TDIS bit to generate a TDIS event, which generates an interrupt or DMA request.
  • Page 184: Figure 11-10 I 2 C Slave Transmission Flow

    AT32F435/437 Series Reference Manual Slave transmission Figure 11-10 I C slave transmission flow Slave initialization (if STRETCH =1, write data to I2C_TXDT_DT ) I2C_STS_ADDRF=1? Read I2C_STS_ADDR Read I2C_STS_SDIR Set I2C_CLR_ADDRC =1 I2C_STS_ACKFAIL=1? Write I2C_CLR_ACKFAILC I2C_STS_TDIS=1? I2C_STS_STOPF=1? Write I2C_TXDT_DT Set I2C_STS_TDBE = 1 and I2C_CLR_TDIS = 1 Set I2C_CLR_STOPC = 1 Figure 11-11 I...
  • Page 185: Figure 11-12 I 2 C Slave Receive Flow

    AT32F435/437 Series Reference Manual Slave receive Figure 11-12 I C slave receive flow Slave initialization I2C_STS_ADDRF=1? Read I2C_STS_ADDR Read I2C_STS_SDIR Set I2C_CLR_ADDRC =1 I2C_STS_STOPF=1? Set I2C_CLR_STOPC=1 I2C_STS_RDBF=1? Read I2C_RXDT_DT Figure 11-13 I C slave receive timing I2C Slave receiver N bytes from I2C master EV4 EV5 Address Data1...
  • Page 186 AT32F435/437 Series Reference Manual 11.4.5 SMBus The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other. It is based on I C. With SMBus, the device can provide manufacturer information, tell the system its model/part number, report different types of errors and accept control parameters and so on.
  • Page 187: Table 11-3 Smbus Timeout Specification

    AT32F435/437 Series Reference Manual PEC calculation is enabled when PECEN=1 to check address and data. PEC transfer: ― Host: PEC transfer is enabled by setting PECTEN=1 in the I2C_CTRL2 register. The host sends a PEC as soon as the number of data transfer reaches N-1 (CNT=N) ―...
  • Page 188: Table 11-5 Smbus Mode Configuration

    AT32F435/437 Series Reference Manual Slave receive byte control In slave receive mode, the slave receive byte control mode (SCTRL=1) can be used to control ACK/NACK signals of each received byte. Refer to section 11.4.2 for more information. Table 11-5 SMBus mode configuration Transfer mode PECEN PECTEN...
  • Page 189 AT32F435/437 Series Reference Manual ― Set 7-bit slave address mode (by setting the ADDR10=0 in the I2C_CTRL2 register) Set transfer direction (by setting the DIR bit in the I2C_CTRL2 register) ― DIR=0: Master reception ― DIR=1: Master transmission Start data transfer In case of GENSTART=1 in the I2C_CTRL2 register, the master starts sending a START condition and slave address.
  • Page 190: Figure 11-14 Smbus Master Transmission Flow

    AT32F435/437 Series Reference Manual SMBus master transmission flow Figure 11-14 SMBus master transmission flow Master initialization Set I2C_CTRL2_CNT = N+1 I2C_CT RL1_PE CEN=1 I2C_CT RL2_PE CTEN=1 Configure slave address GENSTART = 1 Wait I2C_STS_STOPF=1 I2C_STS_ACKFAIL=1? Set I2C_CLR_STOPC=1 I2C_CLR_ACKFAILC=1 I2C_STS_TDIS=1? Write I2C_TXDT_DT N Bytes Transmitted? (ASTOPEN = 1)
  • Page 191: Figure 11-15 Smbus Master Transmission Timing

    AT32F435/437 Series Reference Manual Figure 11-15 SMBus master transmission timing SMBus master transmitter N bytes + PEC Initial setting flow : 1. I2C_CTRL2_CNT = N+ 1 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL1_PECEN = 1 5. I2C_CTRL2_PECTEN = 1 6.
  • Page 192: Figure 11-17 Smbus Master Receive Timing

    AT32F435/437 Series Reference Manual Figure 11-17 SMBus master receive timing SMBus master receiver N bytes +PEC Initial setting flow : 1. I2C_CTRL2_CNT = N+ 1 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL1_PECEN = 1 5. I2C_CTRL2_PECTEN = 1 6.
  • Page 193 AT32F435/437 Series Reference Manual The ADDRF flag can be cleared by setting ADDRC=1 in the I2C_CLR register, and then data transfer starts. Data transfer (slave transmission, clock stretching enabled, STRETCH=0) After address matching: I2C_TXDT data register becomes empty, the shift register becomes empty, and TDIS=1 in the I2C_STS register Data is then transferred to the shift register after writing 1 to the TXDT register The TXDT register then becomes empty, and the TDIS is set again...
  • Page 194: Figure 11-18 Smbus Slave Transmission Flow

    AT32F435/437 Series Reference Manual SMBus slave transmission Figure 11-18 SMBus slave transmission flow Slave initialization I2C_CTRL1_PECEN = 1 I2C_STS_ADDRF=1? Set I2C_CTRL2_CNT =N+ 1 I2C_CTRL2_PECTEN = 1 I2C_CLR_ADDRC =1 I2C_STS_ACKFAIL=1? Write I2C_CLR_ACKFAILC I2C_STS_TDIS=1? I2C_STS_STOPF=1? Write I2C_TXDT_DT Set I2C_STS_TDBE = 1 and I2C_CLR_TDIS = 1 Set I2C_CLR_STOPC = 1 Figure 11-19 SMBus slave transmission timing SMBus slave transmitter N bytes + PEC...
  • Page 195: Figure 11-20 Smbus Slave Receive Flow

    AT32F435/437 Series Reference Manual SMBus slave receive Figure 11-20 SMBus slave receive flow Slave initialization I2C_CTRL1_PECEN = 1 Read I2C_RXDT_DT Set I2C_CTRL2_NACKEN = 0 I2C_CTRL2_RLDEN =0 I2C_STS_ADDRF=1? I2C_CTRL2_CNT = 1 Set I2C_CTRL2, CNT = 1, RLDEN=1 , PECTEN = 1 I2C_STS_RDBF = 1? Set I2C_CLR_ADDRC =1 Read I2C_RXDT_DT...
  • Page 196: Table 11-6 I 2 C Error Events

    AT32F435/437 Series Reference Manual 11.4.8 Data transfer using DMA C data transfer can be done using DMA controller so as to reduce the burden on the CPU. The TDIEN and RDIEN must be set 0 when using DMA for data transfer. Transmission using DMA (DMATEN=1) Set the peripheral address (DMA_CxPADDR= I2C_TXDT address) Set the memory address (DMA_CxMADDR=data memory address)
  • Page 197 AT32F435/437 Series Reference Manual Overrun/underrun ERRIEN OUFC Arbitration lost ARLOST ERRIEN ARLOSTC Bus error BUSERR ERRIEN BUSERRC Overrun/Underrun (OUF) In slave mode, an underrun/overrun may appear if the clock stretching feature is disabled (STRETCH=1 in the I2C_CTRL1 register) In slave transmit mode: if data has not yet been written to the TXDT register before the transmission of the first bit of the to-be-transferred data (that is, before the generation of SDA edge), an underrun error may occur, and the OUF bit is set in the I2C_STS register, sending 0xFF to the bus.
  • Page 198: Table 11-7 I 2 C Interrupt Requests

    AT32F435/437 Series Reference Manual 11.5 I C interrupt requests The following table lists all the I C interrupt requests. Table 11-7 I C interrupt requests Interrupt event Event flag Enable control bit Address matched ADDRF ADDRIEN Acknowledge failure ACKFAIL ACKFAILIEN Stop condition received STOPF STOPIEN...
  • Page 199 AT32F435/437 Series Reference Manual 11.7.1 Control register1 (I2C_CTRL1) Register Reset value Type Description Bit 31:24 Reserved 0x00 Kept at its default value. PEC calculation enable Bit 23 PECEN 0: PEC calculation disabled 1: PEC calculation enabled SMBus alert enable / pin set To enable SMBus master alert feature: 0: SMBus alert disabled Bit 22...
  • Page 200 AT32F435/437 Series Reference Manual Acknowledge fail interrupt enable Bit 4 ACKFAILIEN 0: Acknowledge fail interrupt disabled 1: Acknowledge fail interrupt enabled Address match interrupt enable Bit 3 ADDRIEN 0: Address match interrupt disabled 1: Address match interrupt enabled Data receive interrupt enable Bit 2 RDIEN resd...
  • Page 201 AT32F435/437 Series Reference Manual 11.7.3 Address register1 (I2C_OADDR1) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 Kept at its default value. Own Address 1 enable Bit 15 ADDR1EN 0: Own Address 1 disabled 1: Own Address 1 enabled Bit 14: 11 Reserved Kept at its default value.
  • Page 202 AT32F435/437 Series Reference Manual Corresponds to T in SMBus. TIMEOUT Bit 14: 13 Reserved Kept at its default value. Clock timeout detection mode Bit 12 TOMODE 0: Clock low level detection 1: Clock high level detection Clock timeout detection time For clock low level detection (TOMODE = 0): Bit 11: 0 TOTIME[11:0]...
  • Page 203 AT32F435/437 Series Reference Manual 1: Data transfer is completed (shift register become empty and all data has been sent to the bus) This bit is set when ASTOPEN = 0, RLDEN = 0, CNT = 0. It is automatically cleared after a START or a STOP condition is received.
  • Page 204 AT32F435/437 Series Reference Manual 11.7.9 PEC register (I2C_PEC) Register Reset value Type Description Bit 31: 8 Reserved 0x000000 Kept at its default value. Bit 7: 0 PECVAL[7: 0] 0x00 PEC value 11.7.10 Receive data register (I2C_RXDT) Register Reset value Type Description Bit 31: 8 Reserved...
  • Page 205: Figure 12-1 Usart Block Diagram

    AT32F435/437 Series Reference Manual 12 Universal synchronous/asynchronous receiver/transmitter (USART) 12.1 USART introduction The universal synchronous/asynchronous receiver/transmitter (USART) serves an interface for communication by means of various configurations and peripherals with different data formats. It supports asynchronous full-duplex and half-duplex as well as synchronous transfer. With a programmable baud rate generator, USART offers up to 9 MBits/s of baud rate by setting the system frequency and frequency divider, which is also convenient for users to configure the required communication frequency.
  • Page 206 AT32F435/437 Series Reference Manual USART main features: Programmable full-duplex or half-duplex communication  ─ Full-duplex, asynchronous communication ─ Half-duplex, single communication  Programmable communication modes ─ NRZ standard format (Mark/Space) ─ LIN (Local Interconnection Network) ─ IrDA SIR ─ Asynchronous SmartCard protocol defined in ISO7816-3 standard: Support 0.5 or 1.5 stop bits in Smartcard mode ─...
  • Page 207 AT32F435/437 Series Reference Manual ─ Parity error 12.2 Full-duplex/half-duplex selector The full-duplex and half-duplex selector enables USART to perform data exchanges with peripherals in full-duplex or half-duplex mode, which is achieved by setting the corresponding registers. In two-wire unidirectional full-duplex mode (by default), TX pin is used for data output, while the RX pin is used for data input.
  • Page 208: Figure 12-2 Bff And Ferr Detection In Lin Mode

    AT32F435/437 Series Reference Manual Figure 12-2 BFF and FERR detection in LIN mode CASE1:BREAK frame occurring after idle frame Idle frame frame1 frame0 RX pin BREAK 1 frame time RDBF/ FERR CASE2:BREAK frame occurring while a frame is being received frame0 frame1 RX pin...
  • Page 209: Figure 12-4 Irda Data(3/16) - Normal Mode

    AT32F435/437 Series Reference Manual Figure 12-4 IrDA DATA(3/16) – normal mode Start Normal frame Stop TX pin 3/16 RX pin 4. Hardware flow control mode: RTS and CTS flow control can be enabled by setting RTSEN=1 and CTSEN=1, respectively. RTS: the RTS becomes active (pull-down means low) as soon as the USART receiver is ready to receive a data.
  • Page 210: Figure 12-6 Mute Mode Using Idle Line Or Address Mark Detection

    AT32F435/437 Series Reference Manual bits. Figure 12-6 Mute mode using Idle line or Address mark detection Idle line detection(WUM = 0): frame2 3 4 frame0 frame1 frame5 RX pin Idle RDBF Normal mode Mute mode Address mark detection(WUM = 1): frame1 2 3 4 ADDR=0 frame0...
  • Page 211: Figure 12-8 Word Length

    AT32F435/437 Series Reference Manual The DBN1 and DBN0 bits are used to program 7-bit (DBN[1:0]=10), 8-bit (DBN[1:0]=00) or 9-bit (DBN[1:0]=01) data bits. Figure 12-8 Word length 9-bit word length (DBN1, DBN0 = 01): Clock PEN = 1, Next Data frame Next Data frame Parity bit Start...
  • Page 212: Figure 12-9 Stop Bit Configuration

    AT32F435/437 Series Reference Manual Figure 12-9 Stop bit configuration Clock PEN = 1, Next STOPBN = 00 Data frame Parity bit Start Start 1 Stop bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 1 Stop bit PEN = 1,...
  • Page 213: Table 12-1 Error Calculation For Programmed Baud Rate

    AT32F435/437 Series Reference Manual transfer in the DMA control register. Data will be loaded from the USART_DT register to the programmed destination after reception request is received by DMA. Configure the source of DMA transfer: Configure the USART_DT register address as the source of DMA transfer in the DMA control register.
  • Page 214 AT32F435/437 Series Reference Manual 115.384Kbps. The % error between the desired and actual value is calculated based on the formula: (Calculated actual result-Desired)/desired baud rate*100%, that is, (115.384 - 115.2) / 115.2 * 100% = 0.15%. 12.7 Transmitter 12.7.1 Transmitter introduction USART transmitter has its individual TEN control bit.
  • Page 215: Figure 12-10 Tdc/Tdbe Behavior When Transmitting

    AT32F435/437 Series Reference Manual Figure 12-10 TDC/TDBE behavior when transmitting Set by hardware Set by hardware Set by hardware TDBE DATA0 DATA1 DATA2 USART_DT Idle frame frame1 frame2 frame0 TX pin Set by hardware Cleared by software 12.8 Receiver 12.8.1 Receiver introduction USART receiver has its individual REN control bit (bit 2 in the USART_CTRL1 register).
  • Page 216: Table 12-2 Data Sampling Over Start Bit And Noise Detection

    AT32F435/437 Series Reference Manual  The error flag is set when a framing error, noise error or overrun error is detected during reception.  In DMA mode, the RDNE bit is set after every byte is received, and it is cleared when the data register is read by DMA.
  • Page 217: Figure 12-11 Data Sampling For Noise Detection

    AT32F435/437 Series Reference Manual mentioned requirements, the USART receiver does not think that a correct start bit is received, and thus it will abort the start bit detection and return to idle state waiting for a falling edge. The USART receiver has the ability to detect noise. In the non-synchronous mode, the USART receiver samples data on the 7 and 9 bits, with its oversampling techniques, to distinguish valid data input...
  • Page 218: Figure 12-12 Tx/Rx Swap

    AT32F435/437 Series Reference Manual  If the Tx/Rx were reversed while the user attempts to connect the device externally to a RS-232 chip, they can be swapped through the TRPSWAP bit, without the need of hardware intervention.  If the user only connected the master Tx to the slave Rx in full-duplex mode, the Tx/Rx can be interchangeable with the TRPSWAP bit, after the master and slave are swapped, without the need of hardware intervention.
  • Page 219: Figure 12-13 Usart Interrupt Map Diagram

    AT32F435/437 Series Reference Manual Figure 12-13 USART interrupt map diagram TDBE TDBEIEN TDCIEN CTSCF CTSCFIEN USART interrupt IDLEF IDLEIEN RDBFIEN ROERR RDBFIEN RDBF PERRIEN PERR BFIEN FERR NERR ERRIEN ROERR DMAREN 12.11 I/O pin control The following five interfaces are used for USART communication. RX: Serial data input.
  • Page 220 AT32F435/437 Series Reference Manual 1: Break frame is detected. Transmit data buffer empty This bit is set by hardware when the transmit data buffer is empty. It is cleared by a USART_DT register write Bit 7 TDBE operation. 0: Data is not transferred to the shift register. 1: Data is transferred to the shift register.
  • Page 221 AT32F435/437 Series Reference Manual receiving with the parity bit enabled, the value in the MSB bit is the received parity bit. 12.12.3 Baud rate register (USART_BAUDR) Note: If the TE and RE are both disabled, the baud counter stops counting. Register Reset value Type...
  • Page 222 AT32F435/437 Series Reference Manual PERR interrupt enable Bit 8 PERRIEN 0: Interrupt is disabled. 1: Interrupt is enabled. TDBE interrupt enable Bit 7 TDBEIEN 0: Interrupt is disabled. 1: Interrupt is enabled. TDC interrupt enable Bit 6 TDCIEN 0: Interrupt is disabled. 1: Interrupt is enabled.
  • Page 223 AT32F435/437 Series Reference Manual Clock polarity In synchronous mode or Smartcard mode, this bit is used to select the polarity of the clock output on the clock pin in Bit 10 CLKPOL idle state. 0: Clock output low 1: Clock output high Clock phase This bit is used to select the phase of the clock output on Bit 9...
  • Page 224 AT32F435/437 Series Reference Manual DMA transmitter enable Bit 7 DMATEN 0: DMA transmitter is disabled. 1: DMA transmitter is enabled. DMA receiver enable Bit 6 DMAREN 0: DMA receiver is disabled. 1: DMA receiver is enabled. Smartcard mode enable Bit 5 SCMEN 0: Smartcard mode is disabled.
  • Page 225: Figure 13-1 Spi Block Diagram

    AT32F435/437 Series Reference Manual 13 Serial peripheral interface (SPI) 13.1 SPI introduction The SPI interface supports either the SPI protocol or the I S protocol, depending on software configuration. This chapter gives an introduction of the main features and configuration procedure of SPI used as SPI or I 13.2 Function overview 13.2.1 SPI description...
  • Page 226: Figure 13-2 Spi Two-Wire Unidirectional Full-Duplex Connection

    AT32F435/437 Series Reference Manual  Programmable clock polarity and phase Programmable data transfer order (MSB-first or LSB-first)   Programmable error interrupt flags (CS pulse error, receiver overflow error, master mode error and CRC error)  Programmable transmit data buffer empty interrupt and receive data buffer full interrupt Support transmission and reception using DMA ...
  • Page 227: Figure 13-3 Single-Wire Unidirectional Receive Only In Spi Master Mode

    AT32F435/437 Series Reference Manual Figure 13-3 Single-wire unidirectional receive only in SPI master mode SPI master SPI slave MISO MISO MOSI MOSI Figure 13-4 Single-wire unidirectional receive only in SPI slave mode SPI master SPI slave MISO MISO MOSI MOSI In master mode, it is necessary to wait until the second-to-last RDBF bit is set and then another SPI_CPK period before disabling the SPI.
  • Page 228: Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode

    AT32F435/437 Series Reference Manual Figure 13-5 Single-wire bidirectional half -duplex mode SPI master SPI slave MISO MISO MOSI MOSI When the SPI is selected for data transmission in single-wire bidirectional half-duplex mode (master or slave), the TDBE bit must be set, and the BF must be 0 before disabling the SPI. The power-saving mode (or disabling SPI system clock) cannot be entered unless the SPI is disabled.
  • Page 229 AT32F435/437 Series Reference Manual 13.2.4 SPI_SCK controller The SPI protocol adopts synchronous transmission. In master mode with the SPI being used as SPI, it is required to generate a communication clock for data reception and transmission on the SPI, and the communication clock should be output to the slave via IO for data reception and transmission.
  • Page 230 AT32F435/437 Series Reference Manual 13.2.6 DMA transfer The SPI supports write and read operations with DMA. Refer to the following configuration procedure. Special attention should be paid to: when the CRC calculation and check is enabled, the number of data transferred by DMA is configured as the number of the data to be transferred. The number of data read with DMA is configured as the number of the data to be received.
  • Page 231 AT32F435/437 Series Reference Manual a CS pulse error is detected. At this point, the detected pulse error will be discarded by the SPI. However, since there is something wrong with the CS signal, the software should disable the SPI slave and re- configure the SPI master before re-enabling the SPI slave for communication.
  • Page 232: Figure 13-6 Master Full-Duplex Communications

    AT32F435/437 Series Reference Manual  Configure full-duplex/half-duplex selector Configure chip select controller   Configure SPI_SCK controller  Configure CRC (if necessary)  Configure DMA transfer (if necessary)  If the DMA transfer mode is not used, the software will check whether to enable receive data interrupt (RDBEIE =1) through the RDBE bit.
  • Page 233: Figure 13-7 Slave Full-Duplex Communications

    AT32F435/437 Series Reference Manual Figure 13-7 Slave full-duplex communications Sampling Drive MISO MOSI TDBE flag Transmit buffer empty and RDBF flag software can write data BF flag Software needs to read the received data Half-duplex communication – master transmit Configured as follows: MSTEN=1: Master enable SLBEN=1: Single line bidirectional mode CLKPOL=0, CLKPHA=0: SCK idle output low, use the first edge for sampling...
  • Page 234: Figure 13-10 Slave Half-Duplex Transmit

    AT32F435/437 Series Reference Manual FBN=0: 8-bit frame Slave transmit: 0xaa, 0xcc, 0xaa Figure 13-10 Slave half-duplex transmit Drive MISO Transmit buffer empty and TDBE flag software can write data BF flag Half-duplex communication – master receive Configured as follows: MSTEN=1: Master enable SLBEN=1: Single line bidirectional mode SLBTD=0: Receive enable CLKPOL=0, CLKPHA=0: SCK idle output low, use the first edge for sampling...
  • Page 235: Figure 13-13 Ti Mode Continous Transfer With Dummy Clk

    AT32F435/437 Series Reference Manual Figure 13-13 TI mode continous transfer with dummy CLK Write the to-be-transmitted data MISO MOSI dumm When the to-be-transmitted data is written after the falling SCK edge corresponding to the last data of the current transmit frame, the host always issues a valid SCK clock after 1T SCK + 4T PCLK. If the slave still does not detect a valid CS pulse at the end of the current data reception, it disables MISO output after 1/2T SCK + 3T PCLK to control MISO floating.
  • Page 236: Figure 13-16 I 2 S Block Diagram

    AT32F435/437 Series Reference Manual 13.2.14 Precautions  CRC value is obtained by software reading DT register at the end of CRC reception  In the case of CPOL=1 and CPHA=1, the clock divided by 3 that is generated inside the SPI must be less than 32 MHz.
  • Page 237: Figure 13-17 I 2 S Full-Duplex Structure

    AT32F435/437 Series Reference Manual  Programmable audio protocol ─ I S Philips standard ─ MSB-aligned standard (left-aligned) ─ LSB-aligned standard (right-aligned) ─ PCM standard (long or short frame) S full-duplex   DMA transfer  Main peripheral clock with a fixed frequency of 256x Fs (audio sampling frequency) 13.3.2 I S full-duplex Two extra I...
  • Page 238: Figure 13-19 I 2 S Slave Device Reception

    AT32F435/437 Series Reference Manual Slave device reception: Set the I2SMSEL bit, and OPERSEL[1:0]=01, the I S will work in slave device reception mode. Figure 13-19 I S slave device reception I2S master I2S slave Master device transmission: Set the I2SMSEL bit, and OPERSEL[1:0]=10, the I S will work in master device transmission mode.
  • Page 239 AT32F435/437 Series Reference Manual 13.3.4 Audio protocol selector While being used as I S, the SPI supports multiple audio protocols. The user can control the audio protocol selector through software configuration to select the desired audio protocol, with the data bits and channel bits being controlled by the audio protocol selector.
  • Page 240: Figure 13-22 Ck & Mck Source In Master Mode

    AT32F435/437 Series Reference Manual 13.3.5 I2S_CLK controller The audio protocols the SPI supports adopts synchronous transmission. In master mode, it is required to generate a communication clock for data reception and transmission on the SPI, and the communication clock should be output to the slave via IO for data reception and transmission. In slave mode, the communication clock is provided by master, and is input to the SPI via IO.
  • Page 241 AT32F435/437 Series Reference Manual 11025 11029 0.04% 11029 0.04% 8000 8012 0.16% 8012 0.16% 192000 189393.9 1.36% 195312.5 1.73% 96000 96153.85 0.16% 94696.97 1.36% 48000 48076.92 0.16% 48076.92 0.16% 44100 44014.08 0.19% 44014.08 0.19% 32000 32051.28 0.16% 31887.76 0.35% 22050 22084.81 0.16% 22007.04...
  • Page 242 AT32F435/437 Series Reference Manual 11025 10817.31 1.88% 10817.31 1.88% 8000 8035.714 0.45% 8035.714 0.45% 13.3.6 DMA transfer The SPI supports write and read operations with DMA. Whether used as SPI or I S, read/write request using DMA comes from the same peripheral. As a result, their configuration procedure are the same, described as follows.
  • Page 243: Figure 13-23 Audio Standard Timings

    AT32F435/437 Series Reference Manual before disabling the I ─ I2SDBN=00, I2SCBN=1, STDSLE=00 or STDSLE=01 or STDSLE=11: wait for the last RDBF=1 and one CK period before the I ─ I2SDBN, I2SCBN,STDSLE combination: wait for the second-to-last RDBF=1 and one CK period before disabling the I S transmitter configuration procedure: ...
  • Page 244: Figure 13-24 I S Interrupts

    AT32F435/437 Series Reference Manual 13.3.9 Interrupts Figure 13-24 I S interrupts RDBF RDBFIE TDBE TDBEIE I2S中断 ERRIE ROERR TUERR 13.3.10 IO pin control The I S needs three pins for transfer operation, namely, the SD, WS and CK. The MCLK pin is also required if need to provide main clock for peripherals.
  • Page 245: Table 13-2 Spi Register Map And Reset Value

    AT32F435/437 Series Reference Manual 13.4 SPI registers These peripheral registers must be accessed by half-word (16 bits) or word (32 bits). Table 13-2 SPI register map and reset value Register Offset Reset value SPI_CTRL1 0x00 0x0000 SPI_CTRL2 0x04 0x0000 SPI_STS 0x08 0x0002 SPI_DT...
  • Page 246 AT32F435/437 Series Reference Manual LSB transmit first This bit is used to select for MST transfer first or LSB Bit 7 transfer first. 0: MSB 1: LSB SPI enable Bit 6 SPIEN 0: Disabled 1: Enabled Master clock frequency division In master mode, the peripheral clock divided by the prescaler is used as SPI clock.
  • Page 247 AT32F435/437 Series Reference Manual I2S mode. Bit 3 Reserved resd Kept at its default value Hardware CS output enable This bit is valid only in master mode. When this bit is set, the I/O output on the CS pin is low; when this bit is 0, the Bit 2 HWCSOE I/O input on the CS pin must be set high.
  • Page 248 AT32F435/437 Series Reference Manual 0: Transmit data buffer is not full. 1: Transmit data buffer is full. 13.4.4 SPI data register (SPI_DT) Register Reset value Type Description Data value Bit 15: 0 0x0000 This register controls read and write operations. When the data bit is set as 8 bit, only the 8-bit LSB [7: 0] is valid.
  • Page 249 AT32F435/437 Series Reference Manual 1: Long frame synchronization Bit 6 Reserved resd Kept at its default value S standard select 00: Philips standard Bit 5: 4 STDSEL 01: MSB-aligned standard (left-aligned) 10: LSB-aligned standard (right-aligned) 11: PCM standard S clock polarity This bit indicates the clock polarity on the clock pin in idle Bit 3 I2SCLKPOL...
  • Page 250: Table 14-1 Tmr Functional Comparison

    AT32F435/437 Series Reference Manual 14 Timer AT32F435 timers include basic timers, general-purpose timers, and advanced timers. Please refer to Section 14.1 ~ Section 14.4 for the detailed function modes. All functions of different timers are shown in the following tables. Table 14-1 TMR functional comparison Counter Count...
  • Page 251: Figure 14-1 Basic Timer Block Diagram

    AT32F435/437 Series Reference Manual 14.1 Basic timer (TMR6 and TMR7) 14.1.1 TMR6 and TMR7 introduction Each of the basic timers (TMR6 and TMR7) includes a 16-bit up counter and the corresponding control logic. without being connected to external I/Os, they can be used for a basic timing and providing clocks for the digital-to-analog converter (DAC).
  • Page 252: Figure 14-3 Counter Structure

    AT32F435/437 Series Reference Manual timer controller in reset mode trigger the generation of an overflow event. When the OVFS bit is set, only counter overflow/underflow triggers an overflow event. Setting the TMREN bit (TMREN=1) enables the timer to start counting. Base on synchronization logic, however, the actual enable signal TMR_EN is set 1 clock cycle after the TMREN is set.
  • Page 253: Table 14-2 Tmr6 And Tmr7- Register Table And Reset Value

    AT32F435/437 Series Reference Manual 14.1.3.3 Debug mode ® When the microcontroller enters debug mode (Cortex -M4F core halted), the TMRx counter stops counting when the TMRx_PAUSE bit is set. Refer to section 30.2 for details. 14.1.4 TMR6 and TMR7 registers These peripheral registers must be accessed by word (32 bits).
  • Page 254 AT32F435/437 Series Reference Manual 14.1.4.2 TMR6 and TMR7 control register2 (TMRx_CTRL2) Register Reset value Type Description Bit 15: 7 Reserved 0x000 resd Kept at its default value. Master TMR output selection This field is used to select the signals in master mode to be sent to slave timers.
  • Page 255: Figure 14-7 General-Purpose Timer Block Diagram

    AT32F435/437 Series Reference Manual 14.1.4.7 TMR6 and TMR7 division (TMRx_DIV) Register Reset value Type Description Divider value The counter clock frequency f / (DIV[15: CK_CNT TMR_CLK Bit 15: 0 0x0000 0]+1). At each overflow event, DIV value is sent to the DIV register.
  • Page 256: Figure 14-8 Count Clock

    AT32F435/437 Series Reference Manual 14.2.3 TMR2 to TMR5 functional overview 14.2.3.1 Counting clock The count clock of TMR2~TMR5 can be provided by the internal clock (CK_INT), external clock (external clock mode A and B) and internal trigger input (ISx). Figure 14-8 Count clock Encoder mode (SMSEL=3'b001/010/011) CK_INT(form CRM)
  • Page 257: Figure 14-10 Block Diagram Of External Clock Mode A

    AT32F435/437 Series Reference Manual Set external source TRGIN parameters If the TMRx_CH1 is used as a source of TRGIN, it is necessary to configure channel 1 input filter (C1DF[3:0] in TMRx_CM1 register) and channel 1 input polarity (C1P/C1CP in TMRx_CCTRL register);...
  • Page 258: Figure 14-12 Block Diagram Of External Clock Mode B

    AT32F435/437 Series Reference Manual Figure 14-12 Block diagram of external clock mode B polarity and edge detector TMRx_EXT ECMBEN=1 CK_CNT DIV_counter CNT_counter ESDIV prescaler External clock mode B filter enable Note: The delay between the EXT signal on the input side and the actual clock of the counter is due to the synchronization circuit.
  • Page 259: Figure 14-14 Counter Timing With Prescaler Value Changing From 1 To 4

    AT32F435/437 Series Reference Manual Figure 14-14 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER DIV[15:0] PR[15:0] OVFIF Clear 14.2.3.2 Counting mode The timer (TMR2 to TMR5) supports several counting modes to meet different application scenarios. Each timer has an internal 16-bit upcounter, downcounter, upcounter/downcounter.
  • Page 260: Figure 14-16 Overflow Event When Prben=0

    AT32F435/437 Series Reference Manual Figure 14-16 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-17 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1register to enable downcounting mode. In this mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed, and generates a counter underflow event.
  • Page 261: Figure 14-19 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32

    AT32F435/437 Series Reference Manual Figure 14-19 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32 TMR_CLK COUNTER OWCDIR PR[15:0] DIV[15:0] TWCMSEL [1:0] OVFIF Clear Clear Clear Encoder interface mode To enable the encoder interface mode, write SMSEL[2: 0]= 3’b001/3’b010/3’b011. In this mode, the two inputs (C1IN/C2IN) are required.
  • Page 262: Figure 14-21 Example Of Counter Behavior In Encoder Interface Mode (Encoder Mode C)

    AT32F435/437 Series Reference Manual − Enable counter through the TMREN bit in the TMRx_CTRL1 register Table 14-4 Counting direction versus encoder signals C1INFP1 signal C2INFP2 signal Level on opposite signal Active edge (C1INFP1 to C2IN, C2INFP2 to C1IN) Rising Falling Rising Falling High...
  • Page 263: Figure 14-22 Input/Output Channel 1 Main Circuit

    AT32F435/437 Series Reference Manual Figure 14-22 Input/output channel 1 main circuit C1INSEL TMRx_CH3 edge detector input divider STCI TMRx_CH2 C1IRAW C1DF C1P/C1CP C1IDIV C1EN C1IFP1 C1IN TMRx_CH1 C2IFP1 filter Capture trigger C1DT_shadow Compare CNT counter Capture C1DT C1DT preload C1OCTRL C1OBEN Overflow event C1ORAW...
  • Page 264: Figure 14-24 Example Of Pwm Input Mode Configuration

    AT32F435/437 Series Reference Manual PWM input The PWM input mode applies to channel 1 and channel 2. To enable this mode, map the C1IN and C2IN to the same TMRx_CHx, and configure the CxIFPx of channel 1/2 to trigger slave timer controller reset. The PWM input mode can be used to measure the period and duty cycle of input signal.
  • Page 265: Figure 14-26 Capture/Compare Channel Output Stage (Channel 1 To 4)

    AT32F435/437 Series Reference Manual Figure 14-26 Capture/compare channel output stage (channel 1 to 4) Output mode CNT_value controller Polarity CNT_value=CxDT Output enable selection TMRx_CM1 Compare CxORAW /CM2 CNT_value>CxDT CxEN CxOUT CxDT To the master mode controller Output mode Write CxC[1 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this case, the counter value is compared with the value in the TMRx_CxDT register, and the intermediate signal CxORAW is generated according to the output mode selected by CxOCTRL[2: 0], which is sent to IO after being processed by the output control circuit.
  • Page 266: Figure 14-27 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F435/437 Series Reference Manual Figure 28 gives an example of the combination between upcounting mode and PWM mode A. The output signal behaves when PR=0x32 but CxDT is configured with a different value. Figure 29 gives an example of the combination between up/down counting mode and PWM mode A. The output signal behaves when PR=0x32 but CxDT is configured with a different value.
  • Page 267: Figure 14-30 One-Pulse Mode

    AT32F435/437 Series Reference Manual Figure 14-30 One-pulse mode COUNTER PR[15:0] C1DT[15:0] TRGIN C1ORAW C1OUT Master timer event output When TMR is selected as the master timer, the following signal sources can be selected as TRGOUT signal to output to the slave timer, by setting the PTOS bit in the TMRxCTRL2 register. PTOS=3’b000, TRGOUT outputs software overflow event (OVFSWTR bit in the TMRx_SWEVT register);...
  • Page 268: Figure 14-32 Example Of Reset Mode

    AT32F435/437 Series Reference Manual Slave mode: Reset mode The counter and its prescaler can be reset by a selected trigger signal. An overflow event is generated when OVFS=0. Figure 14-32 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2:0] SMSEL[2:0] CI1F1 OVFIF TRGIF...
  • Page 269: Figure 14-35 Master/Slave Timer Connection

    AT32F435/437 Series Reference Manual Master/slave timer interconnection Both Master and slave timer can be configured in different master and slave modes respectively. The combination of both them can be used for various purposes. The figure below provides an example of interconnection between master timer and slave timer.
  • Page 270: Figure 14-37 Starting Master And Slave Timers Synchronously By An External Trigger

    AT32F435/437 Series Reference Manual Starting master and slave timers synchronously by an external trigger: In this example, configure the master timer as master/slave mode synchronously and enable its slave timer synchronization function. This mode is used for synchronization between master timer and slave timer.
  • Page 271 AT32F435/437 Series Reference Manual TMRx_PR 0x2C 0x0000 TMRx_C1DT 0x34 0x0000 TMRx_C2DT 0x38 0x0000 TMRx_C3DT 0x3C 0x0000 TMRx_C4DT 0x40 0x0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000 TMR2_RMP 0x50 0x0000 TMR5_RMP 0x50 0x0000 14.2.4.1 TMR2 to TMR5 control register1 (TMRx_CTRL1) Register Reset value Type Description Bit 15: 11...
  • Page 272 AT32F435/437 Series Reference Manual 0: Counter overflow, setting the OVFSWTR bit or overflow event generated by slave timer controller 1: Only counter overflow generates an overflow event Overflow event enable Bit 1 OVFEN 0: Enabled 1: Disabled TMR enable Bit 0 TMREN 0: Disabled 1: Enabled...
  • Page 273 AT32F435/437 Series Reference Manual 1010: f /16, N=5 ���������������� ������ 1011: f /16, N=6 ���������������� ������ 1100: f /16, N=8 ���������������� ������ 1101: f /32, N=5 ���������������� ������ 1110: f /32, N=6 ���������������� ������ 1111: f /32, N=8 ���������������� ������ Subordinate TMR synchronization If enabled, master and slave timer can be synchronized.
  • Page 274 AT32F435/437 Series Reference Manual 0: Disabled 1: Enabled Kept at its default value Bit 5 Reserved resd Channel 4 interrupt enable Bit 4 C4IEN 0: Disabled 1: Enabled Channel 3 interrupt enable Bit 3 C3IEN 0: Disabled 1: Enabled Channel 2 interrupt enable Bit 2 C2IEN 0: Disabled...
  • Page 275 AT32F435/437 Series Reference Manual 0: No overflow event occurs 1: Overflow event is generated. If OVFEN=0 and OVFS=0 in the TMRx_CTRL1 register: − An overflow event is generated when OVFG= 1 in the TMRx_SWEVE register; − An overflow event is generated when the counter CVAL is reinitialized by a trigger event.
  • Page 276 AT32F435/437 Series Reference Manual 14.2.4.6 TMR2 to TMR5 software event register (TMRx_SWEVT) Register Reset value Type Description Kept at its default value. Bit 15: 7 Reserved 0x000 resd Trigger event triggered by software This bit is set by software to generate a trigger event. Bit 6 TRGSWTR 0: No effect...
  • Page 277 AT32F435/437 Series Reference Manual – OWCDIR=0, C1ORAW is low once TMRx_ C1DT >TMRx_CVAL, else high; – OWCDIR=1, C1ORAW is high once TMRx_ C1DT <TMRx_CVAL, else low. Note: In the configurations other than 000’, the C1OUT is connected to C1ORAW. The C1OUT output level is not only subject to the changes of C1ORAW, but also the output polarity set by CCTRL.
  • Page 278 AT32F435/437 Series Reference Manual 0111: f /4, N=8 ���������������� ������ 1111: f /32, N=8 ���������������� ������ Channel 1 input divider This field defines Channel 1 input divider. 00: No divider. An input capture is generated at each active edge. Bit 3: 2 C1IDIV 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges...
  • Page 279: Table 14-6 Standard Cxout Channel Output Control Bit

    AT32F435/437 Series Reference Manual Bit 3: 2 C3IDIV Channel 3 input divider Channel 3 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: Bit 1:0 00: Output 01: Input, C3IN is mapped on C3IFP3 10: Input, C3IN is mapped on C4IFP3...
  • Page 280 AT32F435/437 Series Reference Manual 14.2.4.11 TMR2 to TMR5 division value (TMRx_DIV) Register Reset value Type Description Divider value The counter clock frequency f /(DIV[15: CK_CNT TMR_CLK Bit 15: 0 0x0000 0]+1). DIV contains the value written at an overflow event. 14.2.4.12 TMR2 to TMR5 period register (TMRx_PR) Register...
  • Page 281 AT32F435/437 Series Reference Manual Whether the written value takes effective immediately depends on the C3OBEN bit, and the corresponding output is generated on C3OUT as configured. 14.2.4.16 TMR2 to TMR5 channel 4 data register (TMRx_C4DT) Register Reset value Type Description Channel 4 data register When TMR2 or TMR5 enables plus mode (the PMEN bit Bit 31: 16...
  • Page 282: Figure 14-38 Block Diagram Of General-Purpose Tmr9/12

    AT32F435/437 Series Reference Manual 01: Internal clock LICK 10: Internal clock LEXT 11: ERTC wakeup interrupt Bit 5: 0 Reserved 0x00 resd Kept at its default value. 14.3 General-purpose timer (TMR9 to TMR14) 14.3.1 TMR9 to TMR14 introduction The general-purpose timer (TMR9 to TMR14) consists of a 16-bit counter supporting upcounting mode. These timers can be synchronized.
  • Page 283: Figure 14-39 Block Diagram Of General-Purpose Tmr10/11/13/14

    AT32F435/437 Series Reference Manual Figure 14-39 Block diagram of general-purpose TMR10/11/13/14 Capture Compare CNT counter OUT MODE IN MODE CH1 edge Output1 C1IFP1(C1IN) C1IN DIV C1C 0 C1DT C1C=0 C1DT C1ORAW TMRx_CH1 control C1OUT detector CH1 filter C1IRAW TMRx_CH1 preload TMRx_DIV Overflow event DIV counter...
  • Page 284: Figure 14-42 Block Diagram Of External Clock Mode A

    AT32F435/437 Series Reference Manual The counter clock can be provided by TRGIN signal. SMSEL=3’b111: External clock mode A is selected. Select an external clock source TRGIN signal by setting the STIS[2:0] bit to drive the counter to start counting. The external clock sources include: C1INC (STIS=3’b100, channel 1 rising edge and falling edge), C1IFP1 (STIS=3’b101, channel 1 signal with filtering and polarity selection) and C2IFP2 (STIS=3’b110, channel 2 signal with filtering and polarity selection).
  • Page 285: Figure 14-44 Counter Timing With Prescaler Value Changing From 1 To 4

    AT32F435/437 Series Reference Manual can be adjusted by setting the value of the TMRx_DIV register. The prescaler value can be modified at any time, but it takes effect only when the next overflow event occurs. The internal trigger input is configured as follows: Set the TMRx_PR register to set the counting period;...
  • Page 286: Figure 14-45 Counter Structure

    AT32F435/437 Series Reference Manual 14.3.3.2 Counting mode The general-purpose timer only supports upcounting mode, and it consists of a 16-bit counter. The TMRx_PR register issued to set the counting period. The value in the TMRx_PR is immediately moved to the shadow register by default. When the periodic buffer is enabled (PRBEN=1), the value in the TMRx_PR register is transferred to the shadow register only at an overflow event.
  • Page 287: Figure 14-46 Overflow Event When Prben=0

    AT32F435/437 Series Reference Manual Figure 14-46 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-47 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear 14.3.3.3 TMR input function Each timer of TMR9 and TMR12 has two independent channels, while each of TMR10, TMR11, TMR13 and TMR14 has an independent channel.
  • Page 288: Figure 14-48 Input/Output Channel 1 Main Circuit

    AT32F435/437 Series Reference Manual Figure 14-48 Input/output channel 1 main circuit edge detector input divider STCI C1DF C1P/C1CP C1IRAW TMRx_CH1 C1IFP1 C1IN C1IDIV C1EN C2IFP1 filter Capture trigger C1DT_shadow Compare CNT counter Capture C1DT C1DT preload C1OCTRL C1OBEN Overflow event C1ORAW C1EN polarity select...
  • Page 289: Figure 14-50 Example Of Pwm Input Mode Configuration

    AT32F435/437 Series Reference Manual edge of channel 1 input signal triggers capture and saves captured values to the C2DT register. The period and duty of channel 1 input signal can be calculated through C1DT and C2DT respectively. Figure 14-50 Example of PWM input mode configuration C1C(2'b01) edge detector STCI...
  • Page 290: Figure 14-52 Capture/Compare Channel Output Stage (Channel 1)

    AT32F435/437 Series Reference Manual 14.3.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. Figure 14-52 Capture/compare channel output stage (channel 1) Output mode CNT_value controller...
  • Page 291: Figure 14-53 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F435/437 Series Reference Manual Figure 53 gives an example of output compare mode (toggle) with C1DT=0x3. When the counter value is equal to 0x3, C1OUT toggles. Figure 54 gives an example of the combination between upcounting mode and PWM mode A. The output signal behaves when PR=0x32 but CxDT is configured with a different value.
  • Page 292: Figure 14-56 Example Of Reset Mode

    AT32F435/437 Series Reference Manual 14.3.3.5 TMR synchronization TMR9 and TMR12 are linked together internally for timer synchronization. Slave timer is selected by setting the SMSEL[2: 0] bit. Slave mode: Reset mode The counter and its prescaler can be reset by a selected trigger signal. An overflow event is generated when OVFS=0.
  • Page 293: Figure 14-58 Example Of Trigger Mode

    AT32F435/437 Series Reference Manual Figure 14-58 Example of trigger mode TMR_CLK CI1F1 TMR_EN COUNTER PR[15:0] DIV[15:0] STIS[2:0] SMSEL[2:0] OVFIF 14.3.3.6 Debug mode ® When the microcontroller enters debug mode (Cortex -M4F core halted), the TMRx counter stops counting by setting the TMRx_PAUSE in the DEBUG module. Refer to Chapter 30.2 for more information.
  • Page 294 AT32F435/437 Series Reference Manual One cycle mode enable This bit is use to select whether to stop counting at an update event Bit 3 OCMEN 0: The counter does not stop at an update event 1: The counter stops at an update event Overflow event source This bit is used to select overflow event or DMA request sources.
  • Page 295 AT32F435/437 Series Reference Manual 0: Disabled 1: Enabled Overflow interrupt enable Bit 0 OVFIEN 0: Disabled 1: Enabled 14.3.4.4 TMR9 and TMR12 interrupt status register (TMRx_ISTS) Register Reset value Type Description Bit 15: 11 Reserved resd Kept at its default value. Channel 2 recapture flag Bit 10 C2RF...
  • Page 296 AT32F435/437 Series Reference Manual 14.3.4.6 TMR9 and TMR12 channel mode register1 (TMRx_CM1) The channel can be used in input (capture mode) or output (compare mode). The direction of a channel is defined by the corresponding CxC bits. All the other bits of this register have different functions in input and output modes.
  • Page 297 AT32F435/437 Series Reference Manual 1: No need to compare the CVAL and C1DT. An output is generated immediately when a trigger event occurs. Channel 1 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C1EN=’0’: Bit 1: 0 00: Output...
  • Page 298: Table 14-9 Standard Cxout Channel Output Control Bit

    AT32F435/437 Series Reference Manual 14.3.4.7 TMR9 and TMR12 channel control register (TMRx_CCTRL) Register Reset value Type Description Bit 15: 6 Reserved resd Kept at its default value. Channel 2 polarity Bit 5 Please refer to C1P description. Channel 2 enable Bit 4 C2EN Please refer to C1EN description.
  • Page 299: Table 14-10 Tmrx Register Map And Reset Value

    AT32F435/437 Series Reference Manual 14.3.4.12 TMR9 and TMR12 channel 2 data register (TMRx_C2DT) Register Reset value Type Description Bit 31: 16 C2DT 0x0000 resd Kept at its default value. Channel 2 data register When the channel 2 is configured as input mode: The C2DT is the CVAL value stored by the last channel 2 input event (C1IN) Bit 15: 0...
  • Page 300 AT32F435/437 Series Reference Manual 0: Counter overflow, setting the OVFSWTR bit or overflow event generated by slave timer controller 1: Only counter overflow generates an overflow event Overflow event enable 0: Enabled Bit 1 OVFEN 1: Disabled TMR enable 0: Enabled Bit 0 TMREN 1: Disabled...
  • Page 301 AT32F435/437 Series Reference Manual 14.3.5.5 TMR10, TMR11, TMR13 and TMR14 channel mode register1 (TMRx_CM1) The channel can be used in input (capture mode) or output (compare mode). The direction of a channel is defined by the corresponding CxC bits. All the other bits of this register have different functions in input and output modes.
  • Page 302 AT32F435/437 Series Reference Manual Input capture mode: Register Reset value Type Description Bit 15: 8 Reserved resd Kept at its default value. Channel 1 digital filter This field defines the digital filter of the channel 1. N stands for the number of filtering, indicating that the input edge can pass the filter only after N sampling events.
  • Page 303: Table 14-11 Standard Cxout Channel Output Control Bit

    AT32F435/437 Series Reference Manual Table 14-11 Standard CxOUT channel output control bit CxEN bit CxOUT output state Output disabled (CxOUT=0) CxOUT = CxORAW + polarity Note: The state of the external I/O pins connected to the standard CxOUT channel depends on the CxOUT channel state and the GPIO and IOMUX registers.
  • Page 304: Figure 14-59 Block Diagram Of Advanced-Control Timer

    AT32F435/437 Series Reference Manual 14.4 Advanced-control timers (TMR1, TMR8 and TMR20) 14.4.1 TMR1, TMR8 and TMR20 introduction Each of the advanced-control timer (TMR1, TMR8 and TMR20) consists of a 16-bit counter supporting up and down counting modes, four capture/compare registers, and four independent channels to achieve embedded dead-time, input capture and programmable PWM output.
  • Page 305: Figure 14-60 Count Clock

    AT32F435/437 Series Reference Manual Figure 14-60 Count clock Encoder mode (SMSEL=3'b001/010/011) CK_INT(form CRM) CI1FP1/CI2FP2 STIS[1:0] External clock mode A (SMSEL=3'b111) STIS[2] Internal trigger DIV_counter CK_CNT CNT_counter STIS[1:0] TRGIN C1INC C1IFP1 polarity edge External trigger External clock mode B detector C2IPF2 (ECMBEN=1) TMRx_EXT ESDIV...
  • Page 306: Figure 14-62 Block Diagram Of External Clock Mode A

    AT32F435/437 Series Reference Manual (C2DF[3:0] in TMRx_CM1 register) and channel 2 input polarity (C2P/C2CP in TMRx_CCTR register); If the TMRx_EXT is used as a source of TRGIN, it is necessary to configure the external signal polarity (ESP in TMRx_STCTRL register), external signal frequency division (ESDIV[1:0] in TMRx_STCTRL) and external signal filter (ESF[3:0] in TMRx_STCTRL register).
  • Page 307: Figure 14-64 Block Diagram Of External Clock Mode B

    AT32F435/437 Series Reference Manual Figure 14-64 Block diagram of external clock mode B polarity and edge detector TMRx_EXT ECMBEN=1 CK_CNT DIV_counter CNT_counter ESDIV prescaler External clock mode B filter enable Note: The delay between the signal on the input side and the actual clock of the counter is due to the synchronization circuit.
  • Page 308: Figure 14-66 Counter Timing With Prescaler Value Changing From 1 To 4

    AT32F435/437 Series Reference Manual Figure 14-66 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER DIV[15:0] PR[15:0] OVFIF Clear 14.4.3.2 Counting mode The advanced-control timer consists of an internal 16-bit counter supporting up, down, up/down counting modes to meet different application scenarios.
  • Page 309: Figure 14-68 Overflow Event When Prben=0

    AT32F435/437 Series Reference Manual Figure 14-68 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-69 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode Set CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1 register to enable downcounting mode. In this mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed in the TMRx_PR register, and generates a counter underflow event.
  • Page 310: Figure 14-71 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32

    AT32F435/437 Series Reference Manual Figure 14-71 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32 TMR_CLK COUNTER PR[15:0] DIV[15:0] TWCMSEL [1:0] OVFIF Clear Clear Clear Repetition counter mode The TMRx_RPR register is used to set the counting period of repetition counter. The repetition counter mode is enabled when the repetition counter value is not equal to 0.
  • Page 311: Figure 14-73 Encoder Mode Structure

    AT32F435/437 Series Reference Manual Encoder interface mode To enable the encoder interface mode, write SMSEL[2: 0]= 3’b001/3’b010/3’b011. In this mode, the two inputs (C1IN/C2IN) are required. Depending on the level on one input, the counter counts up or down on the edge of the other input. The OWCDIR bit indicates the direction of the counter. Figure 14-73 Encoder mode structure SMSEL=3'b001/010/011 encoder mode...
  • Page 312: Figure 14-74 Example Of Encoder Interface Mode C

    AT32F435/437 Series Reference Manual Figure 14-74 Example of encoder interface mode C DOWN CI1RAW CI2RAW COUNTER TWCMSEL [1:0] 14.4.3.3 TMR input function Each timer of TMR1, TMR8 and TMR20 has four independent channels. Each channel can be configured as input or output. As input, each channel input signal is handled as follows: −...
  • Page 313: Figure 14-76 Channel 1 Input Stage

    AT32F435/437 Series Reference Manual Figure 14-76 Channel 1 input stage STIS edge detector C1INC input divider STCI C1IPS C1P/C1CP C1IDIV C1EN CNT counter Capture C1DT C1IFP1 C1IN TMRx_CH3 C1INSEL C2IFP1 C1SWTR C1IF TMRx_CH2 C1IRAW C1DF TMRx_CH1 filter C2IRAW C2DF C2IF C2P/C2CP filter edge detector...
  • Page 314: Figure 14-77 Example Of Pwm Input Mode Configuration

    AT32F435/437 Series Reference Manual Figure 14-77 Example of PWM input mode configuration C1C(2'b01) edge detector STCI C1P=0 C1DF C1IRAW C1IF C1IFP1(pos) C1IN C1EN Capture C1DT Capture trigger C1CP=0 filter C2IFP1 (CH1 period) SMSEL(3'b110) STIS(3'b101) Trigger mode C1INC Hang CNT counter mode reset Reset...
  • Page 315: Figure 14-80 Channel 4 Output Stage

    AT32F435/437 Series Reference Manual Figure 14-80 Channel 4 output stage Output mode CNT_value controller Polarity CNT_value=C4DT Output enable selection Compare TMRx_CM2 C4ORAW CNT_value>C4DT C4EN C4OUT C4DT To the master mode controller Output mode Write CxC[1: 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this case, the counter value is compared with the value in the TMRx_CxDT register, and the intermediate signal CxORAW is generated according to the output mode selected by CxOCTRL[2: 0], which is sent to IO after being processed by the output control circuit.
  • Page 316: Figure 14-81 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F435/437 Series Reference Manual Figure 14-82 gives an example of the combination between upcounting mode and PWM mode A. The output signal behaves when PR=0x32 but CxDT is configured with a different value. Figure 14-83 gives an example of the combination between up/down counting mode and PWM mode A. The output signal behaves when PR=0x32 but CxDT is configured with a different value.
  • Page 317: Figure 14-83 Up/Down Counting Mode And Pwm Mode A

    AT32F435/437 Series Reference Manual Figure 14-83 Up/down counting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2:0] C1DT[15:0] C1ORAW CIDT[15:0] C1ORAW ≥32 C1DT[15:0] C1ORAW Figure 14-84 One-pulse mode COUNTER PR[15:0] C1DT[15:0] TRGIN C1ORAW C1OUT Master timer event output When TMR is selected as the master timer, the following signal sources can be selected as TRGOUT signal to output to the slave timer, by setting the PTOS bit in the TMRxCTRL2 register.
  • Page 318: Figure 14-85 Clearing Cxoraw(Pwm Mode A) By Ext Input

    AT32F435/437 Series Reference Manual Figure 14-85 Clearing CxORAW(PWM mode A) by EXT input COUNTER CxDT CxOSEN CxORAW Dead-time insertion The channel 1 to 3 of the advanced-control timers contains a set of reverse channel output. This function is enabled by the CxCEN bit and its polarity is defined by CxCP. Refer to Table 14-15 for more information about the output state of CxOUT and CxCOUT.
  • Page 319: Figure 14-87 Tmr Output Control

    AT32F435/437 Series Reference Manual BRKV bit. When a break event occurs, there are the following actions:  The OEN bit is cleared asynchronously, and the channel output state is selected by setting the FCSODIS bit. This function works even if the MCU oscillator is off. ...
  • Page 320: Figure 14-88 Example Of Tmr Break Function

    AT32F435/437 Series Reference Manual Figure 14-88 Example of TMR break function AOEN CxORAW CxEN CxCEN CxIOS CxCIOS CxOUT Delay CxCOUT Delay Delay 14.4.3.6 TMR synchronization The timers are linked together internally for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit;...
  • Page 321: Figure 14-90 Example Of Suspend Mode

    AT32F435/437 Series Reference Manual Figure 14-90 Example of suspend mode TMR_CLK CI1F1 TMR_EN CNT_CLK COUNTER PR[15:0] DIV[15:0] STIS[2:0] SMSEL[2:0] Slave mode: Trigger mode The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1) Figure 14-91 Example of trigger mode TMR_CLK CI1F1 TMR_EN...
  • Page 322: Table 14-14 Tmr1 And Tmr8 Register Map And Reset Value

    AT32F435/437 Series Reference Manual 14.4.4 TMR1, TMR8 and TM20 registers These peripheral registers must be accessed by word (32 bits). TMR1 and TMR8 register are mapped into a 16-bit addressable space. Table 14-14 TMR1 and TMR8 register map and reset value Register Offset Reset value...
  • Page 323 AT32F435/437 Series Reference Manual alternately, the output flag bit is set only when the counter counts down 10: Two-way counting mode2, count up and down alternately, the output flag bit is set only when the counter counts up 11: Two-way counting mode3, count up and down alternately, the output flag bit is set when the counter counts up / down One-way count direction...
  • Page 324 AT32F435/437 Series Reference Manual DMA request source Bit 3 0: Capture/compare event 1: Overflow event Channel control bit flash selection This bit only acts on channels that have complementary output. If the channel control bits are buffered: Bit 2 CCFS 0: Control bits are updated by setting the HALL bit 1: Control bits are updated by setting the HALL bit or a rising edge on TRGIN.
  • Page 325 AT32F435/437 Series Reference Manual 100: C1IRAW input detector (C1INC) 101: Filtered input 1 (C1IF1) 110: Filtered input 2 (C1IF2) 111: External input (EXT) Please refer to Table 14-3 and 14-5 for more information on ISx for each timer. Bit 3 Reserved resd Kept at its default value.
  • Page 326 AT32F435/437 Series Reference Manual 1: Enabled Channel 2 interrupt enable Bit 2 C2IEN 0: Disabled 1: Enabled Channel 1 interrupt enable Bit 1 C1IEN 0: Disabled 1: Enabled Overflow interrupt enable Bit 0 OVFIEN 0: Disabled 1: Enabled 14.4.4.5 TMR1, TMR8 and TMR20 interrupt status register (TMRx_ISTS) Register Reset value...
  • Page 327 AT32F435/437 Series Reference Manual Overflow interrupt flag This bit is set by hardware on an overflow event. It is cleared by software. 0: No overflow event occurs 1: Overflow event is generated. If OVFEN=0 and Bit 0 OVFIF rw0c OVFS=0 in the TMRx_CTRL1 register: −...
  • Page 328 AT32F435/437 Series Reference Manual 01: Input, C2IN is mapped on C2IFP2 10: Input, C2IN is mapped on C1IFP2 11: Input, C2IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS register. Channel 1 output switch enable 0: C1ORAW is not affected by EXT input.
  • Page 329 AT32F435/437 Series Reference Manual This field is used to define the direction of the channel 2 (input or output), and the selection of input pin when C2EN=’0’: 00: Output 01: Input, C2IN is mapped on C2IFP2 10: Input, C2IN is mapped on C1IFP2 11: Input, C2IN is mapped on STCI.
  • Page 330 AT32F435/437 Series Reference Manual 00: Output 01: Input, C4IN is mapped on C4IFP4 10: Input, C4IN is mapped on C3IFP4 11: Input, C4IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS. Bit 7 C3OSEN Channel 3 output switch enable...
  • Page 331: Table 14-15 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function

    AT32F435/437 Series Reference Manual Please refer to C1EN description. Channel 2 polarity Bit 5 Please refer to C1P description. Channel 2 enable Bit 4 C2EN Please refer to C1EN description. Channel 1 complementary polarity Bit 3 C1CP 0: C1COUT is active high. 1: C1COUT is active low.
  • Page 332 AT32F435/437 Series Reference Manual Asynchronously: CxOUT=CxP, Cx_EN=0, CxCOUT=CxCP, CxCEN=0; If the clock is present: after a dead-time, CxOUT=CxIOS, CxCOUT=CxCIOS, assuming that CxIOS and CxCIOS do not correspond to CxOUT and CxCOUT active level. CxEN=CxCEN=0: output disabled (the corresponding IO disconnected from timer, IO floating) Other: Off-state (the corresponding channel outputs inactive level) Asynchronously: CxOUT =CxP, Cx_EN=1,...
  • Page 333 AT32F435/437 Series Reference Manual 14.4.4.15 TMR1, TMR8 and TMR20 channel 2 data register (TMRx_C2DT) Register Reset value Type Description Channel 2 data register When the channel 2 is configured as input mode: The C2DT is the CVAL value stored by the last channel 2 input event (C1IN) Bit 15: 0 C2DT...
  • Page 334 AT32F435/437 Series Reference Manual This bit acts on the channels that have complementary output. It is used to set the channel state when the timer is inactive and OEN=1. 0: CxOUT/CxCOUT outputs are disabled. 1: CxOUT/CxCOUT outputs are enabled. Output inactive level.
  • Page 335 AT32F435/437 Series Reference Manual 14.4.4.20 TMR1, TMR8 and TMR20 DMA data register (TMRx_DMADT) Register Reset value Type Description DMA data register A write/read operation to the DMADT register accesses Bit 15: 0 DMADT 0x0000 any TMR register located at the following address: TMRx peripheral address + ADDR*4 to TMRx peripheral address + ADDR*4 + DTB*4 14.4.4.21...
  • Page 336: Figure 15-1 Window Watchdog Block Diagram

    AT32F435/437 Series Reference Manual 15 Window watchdog timer (WWDT) 15.1 WWDT introduction The window watchdog downcounter must be reloaded in a limited time window to prevent the watchdog circuits from generating a system reset. The window watch dog is used to detect the occurrence of system malfunctions.
  • Page 337: Figure 15-2 Window Watchdog Timing Diagram

    AT32F435/437 Series Reference Manual Table 15-1 Minimum and maximum timeout value when PCLK1=72 MHz Prescaler Min. Timeout value Max. Timeout value 56.5μs 3.64ms 113.5μs 7.28ms 227.5μs 14.56ms 455μs 29.12ms Figure 15-2 W indow watchdog timing diagram CNT[6:0] 55 54 52 51 50 4F 4E 4D 4C 4B 4A 41 40 3F 55...
  • Page 338 AT32F435/437 Series Reference Manual 10: PCLK1 divided by 16384 11: PCLK1 divided by 32768 Window value If the counter is reloaded while its value is greater than the Bit 6: 0 0x7F window register value, a reset is generated. The counter must be reloaded between 0x40 and WIN[6: 0].
  • Page 339 AT32F435/437 Series Reference Manual 16 Watchdog timer (WDT) 16.1 WDT introduction The WDT is driven by a dedicated low-speed clock (LICK). Due to the lower clock accuracy of LICK, the WDT is best suited to the applications that have lower timing accuracy and can run independently outside the main application.
  • Page 340: Figure 16-1 Wdt Block Diagram

    AT32F435/437 Series Reference Manual Figure 16-1 W DT block diagram power domain 1.2 V power domain Prescaler register 8-bit SYNC WDT_DIV prescaler Reload register 12-bit reload 12-bit SYNC WDT_RLD value downcounter Compare CNT=0 reset Windows register 12-bit windows SYNC WDT_WIN value reset reload at CNT>WIN...
  • Page 341 AT32F435/437 Series Reference Manual 16.5.1 Command register (WDT_CMD) (Reset in Standby mode) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. Command register 0xAAAA: Reload counter Bit 15: 0 0x0000 0x5555: Unlock write-protected WDT_DIV and WDT_RLD 0xCCCC: Enable WDT.
  • Page 342: Figure 17-1 Ertc Block Diagram

    AT32F435/437 Series Reference Manual 17 Enhanced real-time clock (ERTC) 17.1 ERTC introduction The real-time clock provides a calendar clock function. The time and date can be modified by modifying the ERTC_TIME and ERTC_DATE register. The RTC module is in battery powered domain, which means that it keeps running and free from the influence of system reset and VDD power off as long as VBAT is powered.
  • Page 343: Table 17-1 Rtc Register Map And Reset Values

    AT32F435/437 Series Reference Manual 17.3 ERTC function overview 17.3.1 ERTC clock ERTC clock source (ERTC_CLK) is selected via clock controller from a LEXT, LICK, and a divided HEXT clock (By setting the ERTCSEL[1: 0] in the CRM_BPDC register). The HEXT divider value is configured through the ERTC_DIV[4: 0] bit in the CRM_CFG register.
  • Page 344 AT32F435/437 Series Reference Manual ERTC_WP ERTC_SBS Configurable ERTC_TADJ when TADJF=0 ERTC_TSTM ERTC_TSDT ERTC_TSSBS Configurable ERTC_SCAL when CALUPDF=0 ERTC_TAMP Configurable ERTC_ALASBS when ALAWF =1 Configurable ERTC_ALBSBS when ALBWF=1 ERTC_BPRx Clock and calendar initialization After the register write protection is unlocked, follow the procedure below for clock and calendar initialization: 1.
  • Page 345 AT32F435/437 Series Reference Manual time synchronization. In this mode, the UPDF flag is cleared by hardware. To ensure the data is correct when reading clock and calendar, the software must read the clock and calendar registers twice, and compare the results of two read operations. If the result is not aligned, read again until that the results of two read accesses are consistent.
  • Page 346 AT32F435/437 Series Reference Manual 17.3.4 ERTC calibration Two calibration methods are available: coarse and fine calibration. But the two calibration methods cannot be used together. Coarse digital calibration: Coarse digital calibration can be used to advance or delay the calendar updates by increasing or decreasing ck_a cycles.
  • Page 347 AT32F435/437 Series Reference Manual 17.3.5 Reference clock detection The calendar update can be synchronized (not used in low-power modes) to a reference clock (usually the mains 50 or 60 Hz) with a higher precision. This reference clock is used to calibrate the precision of the calendar update frequency (1 Hz) When it is enabled, the reference clock edge detection is performed during the first 7 ck_a periods around each of the calendar updates.
  • Page 348 AT32F435/437 Series Reference Manual 4. According to your needs, enable tamper detection pull-up (setting TPPU=1). When TPPU=1 is asserted, tamper detection pre-charge time must be configured through the TPPR bit 5. According to your needs, configure whether to activate a time stamp on a tamper event (TPTSEN=1) 6.
  • Page 349: Table 17-2 Ertc Low-Power Mode Wakeup

    AT32F435/437 Series Reference Manual Table 17-2 ERTC low-power mode wakeup Wake Clock sources Events Wake up Sleep Wakeup Standby Deepsleep Alarm clock A √ × × Alarm clock B √ × × Periodic automatic HEXT √ × × wakeup Time stamp √...
  • Page 350 AT32F435/437 Series Reference Manual ERTC_TSSBS 0x38 0x0000 0000 ERTC_SCAL 0x3C 0x0000 0000 ERTC_TAMP 0x40 0x0000 0000 ERTC_ALASBS 0x44 0x0000 0000 ERTC_ALBSBS 0x48 0x0000 0000 ERTC_BPRx 0x50-0x9C 0x0000 0000 17.4.1 ERTC time register (ERTC_TIME) Register Reset value Type Description Bit 31: 23 Reserved 0x000 resd...
  • Page 351 AT32F435/437 Series Reference Manual 01: Alarm clock A 10: Alarm clock B 11: Wakeup events Output polarity Bit 20 OUTP 0: High 1: Low Calibration output selection Bit 19 CALOSEL 0: 512Hz 1: 1Hz Battery powered domain data register This bit in the battery powered domain is not affected by a Bit 18 system reset.
  • Page 352 AT32F435/437 Series Reference Manual 1: Reference clock detection enabled Timestamp trigger edge Bit 3 TSEDG 0: Rising edge 1: Falling edge Wakeup timer clock selection 000: ERTC_CLK/16 001: ERTC_CLK/8 010: ERTC_CLK/4 011: ERTC_CLK/2 Bit 2: 0 WATCLK 10x: ck_b 11x: ck_b is selected. 2 is added to the wakeup counter value, and wakeup time =ERTC_WAT+2 Note: The write access to this field is supported when...
  • Page 353 AT32F435/437 Series Reference Manual 1: Initialization mode enabled When an initialization mode is entered, the calendar stops running. Enter initialization mode flag 0: Initialization mode is not entered 1: Initialization mode is entered Bit 6 The ERTC_TIME, ERTC_DATE and ERTC_DIV registers can be modified only when an initialization mode is enabled (INITEN=1) and entered (INITEF=1).
  • Page 354 AT32F435/437 Series Reference Manual 00000: +0 ppm 00001: +4 ppm 00010: +8 ppm 11111: +126 ppm Negative calibration 00000: -0 ppm 00001: -2 ppm 00010: -4 ppm … 11111: - 63 ppm 17.4.8 ERTC alarm clock A register (ERTC_ALA) Register Reset value Type Description...
  • Page 355 AT32F435/437 Series Reference Manual Bit 19: 16 Hour units Minute mask Bit 15 MASK2 0: No minute mask 1: Alarm clock doesn’t care about minutes Bit 14: 12 Minute tens Bit 11: 8 Minute units Second mask Bit 7 MASK1 0: No second mask 1: Alarm clock doesn’t care about seconds Bit 6: 4...
  • Page 356 AT32F435/437 Series Reference Manual 17.4.14 ERTC time stamp date register (ERTC_TSDT) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value Bit 15: 13 WK Week day Bit 12 Month tens Bit 11: 8 Month units Bit 7: 6 Reserved...
  • Page 357 AT32F435/437 Series Reference Manual 1: Tamper detection pull-up disabled Tamper detection pre-charge time 0: 1 ERTC_CLK cycle Bit 14: 13 TPPR 1: 2 ERTC_CLK cycles 2: 4 ERTC_CLK cycles 3: 8 ERTC_CLK cycles Tamper detection filter time 0: No filter Bit 12: 11 TPFLT 1: Tamper is detected after 2 consecutive samples...
  • Page 358 AT32F435/437 Series Reference Manual 17.4.18 ERTC alarm clock A subsecond register (ERTC_ ALASBS) Register Reset value Type Description Bit 31: 28 Reserved resd Kept at its default value Sub-second mask 0: No comparison. Alarm A doesn’t care about subseconds. 1: SBS[0] is compared 2: SBS[1: 0] are compared Bit 27: 24 SBSMSK 3: SBS[2: 0] are compared...
  • Page 359 AT32F435/437 Series Reference Manual 18 Analog-to-digital converter (ADC) 18.1 ADC introduction The ADC is a peripheral that converts an analog input signal into a 12-bit/10-bit/8-bit/6-bit digital signal. Its sampling rate is as high as 5.33 MSPS. Each ADC has up to 19 channels for sampling and conversion, totaling 24 channel source for three ADCs.
  • Page 360: Figure 18-1 Adc1 Block Diagram

    AT32F435/437 Series Reference Manual Figure 18-1 ADC1 block diagram OCTESEL[4:0] ADCDIV TMR1_CH1 TMR1_CH2 TMR1_CH3 TMR2_CH2 ADC prescaler TMR2_CH3 HCLK ADCCLK TMR2_CH4 OCTEN TMR2_TRGOUT [1:0] TMR3_CH1 TMR3_TRGOUT TMR4_CH4 TMR5_CH1 TMR5_CH2 ADCx_IN0 Trigger TMR5_CH3 detection ADCx_IN1 TMR8_CH1 GPIO TMR8_TRGOUT Ordinary EXINT11 conversion start TMR20_TRGOUT ADCx_IN15 TMR20_TRGOUT2...
  • Page 361 AT32F435/437 Series Reference Manual  ADC1_IN0 to ADC1_IN15 are referred to as the external analog input, ADC1_IN16 as an internal temperature sensor, ADC1_IN17 as an internal reference voltage, and ADC1_IN18 as a battery voltage.  ADC2_IN0 to ADC2_IN15 are referred to as the external analog input, and ADC2_IN16 and ADC2_IN17 as Vss, and ADC1_IN18 as V REF-.
  • Page 362: Figure 18-2 Adc Basic Operation Process

    AT32F435/437 Series Reference Manual Figure 18-2 ADC basic operation process Power-on Calibration Trigger conversion Read data 18.4.2.1 Power-on and calibration Power-on Set the ADCxEN bit in the CRM_APB2EN register to enable ADC clocks: PCLK2 and ADCCLK. Program the desired ADCCLK frequency by setting the ADCDIV bit in the ADC_CCTRL register. The ADCCLK is derived from HCLK frequency division.
  • Page 363: Figure 18-3 Adc Power-On And Calibration

    AT32F435/437 Series Reference Manual Figure 18-3 ADC power-on and calibration The ADCEN The ADCAL bit is set by bit is set by software. software. ADCCLK ADCEN STAB RDY flag ADCAL Trigger OCCE flag Powering up Calibration Conversion status The RDY bit The ADCAL The OCCE bit is set by...
  • Page 364: Table 18-2 Trigger Sources For Preempted Channels

    AT32F435/437 Series Reference Manual Table 18-2 Trigger sources for preempted channels PCTESEL Trigger source PCTESEL Trigger source 00000 TMR1_CH4 event 10000 TMR20_TRGOUT event 00001 TMR1_TRGOUT event 10001 TMR20_TRGOUT2 event 00010 TMR2_CH1 event 10010 TMR20_CH4 event 00011 TMR2_TRGOUT event 10011 TMR1_TRGOUT2 event 00100 TMR3_CH2 event 10100...
  • Page 365: Figure 18-4 Sequence Mode

    AT32F435/437 Series Reference Manual Sequence mode Figure 18-4 Sampling Conversion OCLEN=2, OSN1=ADC_IN5, OSN2=ADC_IN0, OSN3=ADC_IN5 Ordinary channel Ordinary channel trigger trigger ADC_IN5 ADC_IN0 ADC_IN5 ADC_IN5 ADC_IN0 ADC_IN5 OCCE flag set OCCE flag set PCLEN=2, PSN2=ADC_IN14, PSN3=ADC_IN1, PSN4=ADC_IN14 Preempted channel Preempted channel trigger trigger ADC_IN14...
  • Page 366: Figure 18-6 Repetition Mode

    AT32F435/437 Series Reference Manual Repetition mode Figure 18-6 Sampling OCLEN=1, OSN1=ADC_IN5, OSN2=ADC_IN0 Conversion PCLEN=1, PSN3=ADC_IN14, PSN4=ADC_IN1 Ordinary channel trigger ADC_IN5 ADC_IN0 ADC_IN14 ADC_IN1 ADC_IN5 ADC_IN0 ADC_IN14 OCCE flag set PCCE flag set OCCE flag set 18.4.3.4 Partition mode The partition mode of the ordinary group can be enabled by setting the OCPEN bit in the ADC_CTRL1 register.
  • Page 367: Figure 18-8 Adabrt Timing Diagram

    AT32F435/437 Series Reference Manual Figure 18-8 ADABRT timing diagram OCLEN=3, OSN1=ADC_IN5, OSN2=ADC_IN0, OSN3=ADC_IN2 ADABRT set Trigger Trigger by software ADC_IN2 ADC_IN0 ADC_IN5 conversion ADC_IN0 conversion ADC_IN5 conversion Idle Idle status conversion conversion ADABRT ADABRT cleared by software ADC_ODT ADC_IN5 ADC_IN0 ADC_IN5 18.4.5 Oversampling A single oversampling converted data can be done through multiple conversions of the same channel in...
  • Page 368: Figure 18-9 Ordinary Oversampling Restart Mode Selection

    AT32F435/437 Series Reference Manual 18.4.5.1 Oversampling of ordinary group of channels The OOSRSEL bit in the ADC_OVSP register can be used to resume ordinary oversampling mode.  OOSRSEL=0: continuous conversion mode. Ordinary group of channels, after being interrupted by preempted group of channels during oversampling, will retain the converted data and resume from the last interrupted ordinary conversion.
  • Page 369: Figure 18-10 Ordinary Oversampling Trigger Mode

    AT32F435/437 Series Reference Manual Ordinary oversampling trigger mode Figure 18-10 Sampling OCLEN=1, OSN1=ADC_IN0, OSN2=ADC_IN1 Conversion Non-triggered oversampling mode:OOSEN = 1, POSEN = 0, = 0, OOSRSEL OOSTREN Ordinary trigger Ordinary ADC_IN0 ADC_IN0 ADC_IN0 ADC_IN0 ADC_IN1 ADC_IN1 ADC_IN1 4 ADC_IN1 OCCE flag set Triggered oversampling mode:OOSEN = 1, POSEN = 0, = 0, OOSRSEL...
  • Page 370: Figure 18-12 Data Alignment

    AT32F435/437 Series Reference Manual Figure 18-12 Data alignment Ordinary channel data 12 bits Right-alignment DT[11] DT[10] DT[9] DT[8] DT[7] DT[6] DT[5] DT[4] DT[3] DT[2] DT[1] DT[0] Left-alignment DT[11] DT[10] DT[9] DT[8] DT[7] DT[6] DT[5] DT[4] DT[3] DT[2] DT[1] DT[0] Ordinary channel data 6 bits Right-alignment DT[5] DT[4]...
  • Page 371: Figure 18-13 Block Diagram Of Master/Salve Mode

    AT32F435/437 Series Reference Manual When using an oversampler, voltage monitoring is based on the comparison result between the 16-bit registers (ADC_VMHB[15:0] and ADC_VMLB[15:0]) and the oversampled data. 18.4.7.1 Status flag and interrupts Each of the ADCs has its dedicated ADCx_STS registers, that is, RDY flag, OCCO flag, OCCS (ordinary channel conversion start flag), PCCS (preempted channel conversion start flag), PCCE (preempted channel conversion end flag), OCCE (ordinary channel conversion end flag) and VMOR (voltage monitor out of range).
  • Page 372: Table 18-4 Master/Slave Dma Mode

    AT32F435/437 Series Reference Manual 18.5.1 Data management In Master/Slave mode, the converted data of ordinary channels is also stored in the ADC_CODT register. The MSDMASEL bit in the ADC_CCTRL register can be used to select from five DMA transfer modes, as shown in Table 18-4. As long as the MSDMASEL is set, the ADC1 DMA channel is used to generate a DMA request each time the data is ready, and overflow detection on master/salve is also enabled.
  • Page 373: Figure 18-14 Regular Simultaneous Mode

    AT32F435/437 Series Reference Manual Figure 18-14 Regular simultaneous mode ADC1: OCLEN=2, OSN1=ADC1_IN0, OSN2=ADC1_IN1, OSN3=ADC1_IN2 Sampling ADC2: OCLEN=2, OSN1=ADC2_IN5, OSN2=ADC2_IN4, OSN3=ADC2_IN3 Conversion ADC3: OCLEN=2, OSN1=ADC3_IN7, OSN2=ADC3_IN8, OSN3=ADC3_IN9 Double slaves mode ADC1 ordinary ADC1 ordinary Single slave mode trigger trigger ADC1 ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC1_IN0...
  • Page 374: Figure 18-16 Alternate Preempted Trigger Mode

    AT32F435/437 Series Reference Manual Figure 18-16 Alternate preempted trigger mode ADC1: PCLEN=2, PSN2=ADC1_IN0, PSN3=ADC1_IN1, PSN4=ADC1_IN2 Sampling ADC2: PCLEN=2, PSN2=ADC2_IN5, PSN3=ADC2_IN4, PSN4=ADC2_IN3 Conversion ADC3: PCLEN=2, PSN2=ADC3_IN7, PSN3=ADC3_IN8, PSN4=ADC3_IN9 Double slaves mode ADC1 preempted ADC1 preempted ADC1 preempted ADC1 preempted Single slave mode trigger trigger trigger...
  • Page 375: Figure 18-18 Regular Shift Mode And Dma Mode 2

    AT32F435/437 Series Reference Manual Figure 18-18 Regular shift mode and DMA mode 2 ADC1: SQEN=1, OSN1=ADC1_IN3, RPEN=1 Sampling ADC2: SQEN=1, OSN1=ADC2_IN3, RPEN=1 ADC1 ordinary Conversion ADC3: SQEN=1, OSN1=ADC3_IN3, RPEN=1 trigger ADC1 ADC1_IN3 ADC1_IN3 ADC1_IN3 ADC2_IN3 ADC2_IN3 ADC2_IN3 ADC2 ADC3_IN3 ADC3_IN3 ADC3_IN3 ADC3 ADC1_ODT...
  • Page 376 AT32F435/437 Series Reference Manual ADC2_STS 0x100 0x0000 0000 ADC2_CTRL1 0x104 0x0000 0000 ADC2_CTRL2 0x108 0x0000 0000 ADC2_SPT1 0x10C 0x0000 0000 ADC2_SPT2 0x110 0x0000 0000 ADC2_PCDTO1 0x114 0x0000 0000 ADC2_PCDTO2 0x118 0x0000 0000 ADC2_PCDTO3 0x11C 0x0000 0000 ADC2_PCDTO4 0x120 0x0000 0000 ADC2_VMHB 0x124 0x0000 FFFF...
  • Page 377 AT32F435/437 Series Reference Manual ADC3_ODT 0x24C 0x0000 0000 ADC3_OVSP 0x280 0x0000 0000 ADC3_CALVAL 0x2B4 0x0000 0000 ADC_CSTS 0x300 0x0000 0000 ADC_CCTRL 0x304 0x0000 0000 ADC_CODT 0x308 0x0000 0000 18.6.1 ADC status register (ADC_STS) Accessed by words. Register Reset value Type Description Bit 31: 7 Reserved...
  • Page 378 AT32F435/437 Series Reference Manual 18.6.2 ADC control register1 (ADC_CTRL1) Accessed by words. Register Reset value Type Description resd Kept at its default value. Bit 31: 27 Reserved 0x00 Ordinary channel conversion overflow interrupt enable 0: Ordinary channel conversion overflow interrupt Bit 26 OCCOIE disabled...
  • Page 379 AT32F435/437 Series Reference Manual Conversion end interrupt enable on Preempted channels 0: Conversion end interrupt disabled on Preempted channels Bit 7 PCCEIEN 1: Conversion end interrupt enabled on Preempted channels Voltage monitoring out of range interrupt enable 0: Voltage monitoring out of range interrupt disabled Bit 6 VMORIEN 1: Voltage monitoring out of range interrupt enabled...
  • Page 380 AT32F435/437 Series Reference Manual Data alignment 0: Right alignment Bit 11 DTALIGN 1: Left alignment Each ordinary channel conversion OCCE flag enable) 0: Disabled 1: Enabled Bit 10 EOCSFEN Note: Overflow detection is enabled automatically when this bit is set. Ordinary channel DMA request continue enable for independent mode) 0: Disabled (After the completion of the programmed...
  • Page 381 AT32F435/437 Series Reference Manual 18.6.4 ADC sampling time register 1 (ADC_SPT1) Accessed by words. Register Reset value Type Description Bit 31: 27 Reserved 0x00 resd Kept at its default value. Sample time selection of channel ADC_IN18 000: Reserved 001: 6.5 cycles 010: 12.5 cycles 011: 24.5 cycles Bit 26: 24...
  • Page 382 AT32F435/437 Series Reference Manual Sample time selection of channel ADC_IN13 000: 2.5 cycles 001: 6.5 cycles 010: 12.5 cycles 011: 24.5 cycles Bit 11: 9 CSPT13 100: 47.5 cycles 101: 92.5 cycles 110: 247.5 cycles 111: 640.5 cycles Sample time selection of channel ADC_IN12 000: 2.5 cycles 001: 6.5 cycles 010: 12.5 cycles...
  • Page 383 AT32F435/437 Series Reference Manual Sample time selection of channel ADC_IN8 000: Reserved 001: 6.5 cycles 010: 12.5 cycles 011: 24.5 cycles Bit 26: 24 CSPT8 100: 47.5 cycles 101: 92.5 cycles 110: 247.5 cycles 111: 640.5 cycles Sample time selection of channel ADC_IN7 000: Reserved 001: 6.5 cycles 010: 12.5 cycles...
  • Page 384 AT32F435/437 Series Reference Manual Sample time selection of channel ADC_IN3 000: Reserved 001: 6.5 cycles 010: 12.5 cycles 011: 24.5 cycles Bit 11: 9 CSPT3 100: 47.5 cycles 101: 92.5 cycles 110: 247.5 cycles 111: 640.5 cycles Sample time selection of channel ADC_IN2 000: Reserved 001: 6.5 cycles 010: 12.5 cycles...
  • Page 385 AT32F435/437 Series Reference Manual 18.6.8 ADC voltage monitor low threshold register (ADC_ VWLB) Accessed by words. Register Reset value Type Description Bit 31: 16 Reserved 0x00000 resd Kept at its default value Bit 15: 0 VMLB 0xFFF Voltage monitoring low boundary 18.6.9 ADC ordinary sequence register 1 ( ADC_ OSQ1) Accessed by words.
  • Page 386 AT32F435/437 Series Reference Manual Number of 1st conversion in ordinary sequence Note: The number can be from 0 to 17. For example, if the Bit 4: 0 OSN1 0x00 number is set to 8, it means that the 1st conversion is ADC_IN17 channel.
  • Page 387 AT32F435/437 Series Reference Manual Ordinary oversampling restart mode select When the ordinary oversampling is interrupted by preempted conversions, this bit can be used to select where to resume ordinary conversions. Bit 10 OOSRSEL 0: Continuous mode (ordinary oversampling buffer will be reserved) 1: Restart mode (ordinary oversampling buffer will be cleared, that is, the previously oversampled times are...
  • Page 388 AT32F435/437 Series Reference Manual ADC3 ordinary channel conversion overflow flag Bit 21 OCCO3 This bit is the mapping bit of the OCCO bit in the ADC3_STS register. ADC3 ordinary channel conversion start flag Bit 20 OCCS3 This bit is the mapping bit of the OCCS bit in the ADC3_STS register.
  • Page 389 AT32F435/437 Series Reference Manual ADC1 ordinary channel conversion start flag Bit 4 OCCS1 This bit is the mapping bit of the OCCS bit in the ADC1_STS register. ADC1 Preempted channel conversion start flag Bit 3 PCCS1 This bit is the mapping bit of the PCCS bit in the ADC1_STS register.
  • Page 390 AT32F435/437 Series Reference Manual Ordinary channel DMA request continuation enable in master/slave mode 0: Disabled (After the completion of the programmed number of DMA transfers, no DMA request generated at the end of ordinary conversion) Bit 13 MSDRCEN 1: Enabled (Don’t care about the programmed number of DMA transfers, Each ordinary channel sends DMA request at the end of ordinary conversion) Note: This bit is applicable in master/slave mode and...
  • Page 391 AT32F435/437 Series Reference Manual 18.6.19 ADC common data register (ADC_CODT) Accessed by words. Register Reset value Type Description Ordinary conversion high halfword data in master slave mode Bit 31: 16 CODTH 0x0000 Note: The meanings of data in this field vary from DMA mode to DMA mode.
  • Page 392: Figure 19-1 Dac1/Dac2 Block Diagram

    AT32F435/437 Series Reference Manual 19 Digital-to-analog converter (DAC) 19.1 DAC introduction The DAC uses a 12-bit digital input to generate an analog output between 0 and reference voltage. The digital part of the DAC can be configured in 8-bit or 12-bit mode and can be used in conjunction with the DMA.
  • Page 393: Table 19-1 Trigger Source Selection

    AT32F435/437 Series Reference Manual  DMA underflow When the DAC DMA request is enabled, an overflow occurs if a second external trigger arrives before the acknowledgement for the first external trigger is received. In this case, no new external trigger is handled, or no new DMA request is issued, and the DxDMAUDRF bit in the DAC_SR register is set, reporting the error condition.
  • Page 394: Figure 19-2 Lfsr Register Calculation Algorithm

    AT32F435/437 Series Reference Manual Figure 19-2 LFSR register calculation algorithm The DxNBSEL [3: 0] bit in the DAC_CTRL register is set to mark partially or totally the LFSR data. The resulting value is then added up to the DHRx value without overflow and this value is loaded into the DAC_DxODT register.
  • Page 395: Table 19-2 Dac Register Map And Reset Values

    AT32F435/437 Series Reference Manual 12-bit left alignment: load data into the DAC_DDTH12L [15: 4] and DAC_DDTH12L [31: 20] 12-bit right alignment: load data into the DAC_DDTH12R [11: 0] and DAC_DDTH12R [27:16] The loaded 8-bit data corresponds to the DHRx[11:4] and the loaded 12-bit data corresponds to the DHRx[11: 0] 19.5 DAC registers These peripheral registers must be accessed by word (32 bits).
  • Page 396 AT32F435/437 Series Reference Manual 0111: Unmask LSFR bit[7: 0] /Triangle amplitude is equal to 255 1000: Unmask LSFR bit[8: 0] /Triangle amplitude is equal to 511 1001: Unmask LSFR bit[9: 0] /Triangle amplitude is equal to 1023 1010: Unmask LSFR bit[10:0] /Triangle amplitude is equal to 2047 ≥1011: Unmask LSFR bit[11: 0] /Triangle amplitude is equal to 4095...
  • Page 397 AT32F435/437 Series Reference Manual 0101: Unmask LSFR bit[5: 0]/Triangle amplitude is equal to 63 0110: Unmask LSFR bit[6: 0]/Triangle amplitude is equal to 127 0111: Unmask LSFR bit[7: 0]/Triangle amplitude is equal to 255 1000: Unmask LSFR bit[8: 0]/Triangle amplitude is equal to 511 1001: Unmask LSFR bit[9: 0]/Triangle amplitude is equal to 1023...
  • Page 398 AT32F435/437 Series Reference Manual 19.5.3 DAC1 12-bit right-aligned data holding register (DAC_ D1DTH12R) Register Reset value Type Description Bit 31: 12 Reserved 0x00000 resd Kept at its default value Bit 11: 0 D1DT12R 0x000 DAC1 12-bit right-aligned data 19.5.4 DAC1 12-bit left-aligned data holding register (DAC_ D1DTH12L) Register Reset value...
  • Page 399 AT32F435/437 Series Reference Manual 19.5.10 Dual DAC 12-bit left-aligned data holding register (DAC_ DDTH12L) Register Reset value Type Description Bit 31: 20 DD2DT12L 0x000 DAC2 12-bit left-aligned data Bit 19: 16 Reserved resd Kept at its default value Bit 15: 4 DD1DT12L 0x000 DAC1 12-bit left-aligned data...
  • Page 400: Figure 20-1 Bit Timing

    AT32F435/437 Series Reference Manual 20 CAN 20.1 CAN introduction CAN (Controller Area Network) is a distributed serial communication protocol for real-time and reliable data communication among various nodes. It supports the CAN protocol version 2.0A and 2.0B. 20.2 CAN main features ...
  • Page 401 AT32F435/437 Series Reference Manual Baud rate formula: ���������������� = Nomal Bit Timimg ���������� ������ ������������ = t ��������_������ ��������1 ��������2 where = 1 x t ��������_������ �� = (1 + BTS1[3: 0]) x t ��������1 �� = (1 + BTS2[2: 0]) x t ��������2 ��...
  • Page 402: Figure 20-2 Transmit Interrupt Generation

    AT32F435/437 Series Reference Manual Figure 20-2 Transmit interrupt generation Inter-frame Inter-frame space or Data frame (standard identifier) space overload frame 44 + 8* N Ack field Data field Arbitration field Control field CRC field 8* N Inter-frame Inter-frame space or Data frame ( extended identifier) space overload frame...
  • Page 403: Figure 20-3 Transmit Interrupt Generation

    AT32F435/437 Series Reference Manual 20.4 Interrupt management The CAN controller contains four interrupt vectors that can be used to enable or disable interrupts by setting the CAN_INTEN register. Figure 20-3 Transmit interrupt generation TCIEN = 1 TX_INT TM0TCF = 1 TM1TCF = 1 TM2TCF = 1 Figure 20-4...
  • Page 404: Figure 20-7 Can Block Diagram

    AT32F435/437 Series Reference Manual 20.5 Design tips The following information can be used as reference for CAN application development:  Debug control When the system enters the debug mode, the CAN controller stops or continues to work normally, depending on the CANx_PAUSE bit in the DEBUG_CTRL register or the PTD bit in the CAN_MCTRL register.
  • Page 405 AT32F435/437 Series Reference Manual 20.6.2 Operating modes The CAN controller has three operating modes:  Sleep mode After a system reset, the CAN controller is in Sleep mode. In this mode, the CAN clock is stopped to reduce power consumption and an internal pull-up resistance is disabled. However, the software can still access to the mailbox registers.
  • Page 406: Figure 20-8 32-Bit Identifier Mask Mode

    AT32F435/437 Series Reference Manual 20.6.4 Message filtering The received message has to go through filtering by its identifier. If passed, the message will be stored in the corresponding FIFOs. If not, the message will be discarded. The whole operation is done by hardware without using CPU resources.
  • Page 407: Figure 20-11 16-Bit Identifier List Mode

    AT32F435/437 Series Reference Manual Figure 20-11 16-bit identifier list mode CAN_FiFB1[15:8] CAN_FiFB1[7:0] CAN_FiFB1[31:24] CAN_FiFB1[23:16] CAN_FiFB2[15:8] CAN_FiFB2[7:0] CAN_FiFB2[31:24] CAN_FiFB2[23:16] SID[10:0] EID[17:15] Mapping Filter match number 28 filter banks have different filtering effects dependent on the bit width mode. For example, 32-bit identifier mask mode contains the filters numbered n while 16-bit identifier list mode contains the filters numbered n, n+1, n+2 and n+3.
  • Page 408: Figure 20-12 Transmit Mailbox Status

    AT32F435/437 Series Reference Manual Figure 20-12 Transmit mailbox status EMPTY Send request(TMSR = 1) Abort sending(TMxCT = 1) PENDING Is it the highest priority Abort sending(TMxCT = 1) SCHEDULED Is the bus idle Send success or send failed with Send failed with automatic SENDING auto retransmission forbidden retransmission...
  • Page 409: Figure 20-13 Receive Fifo Status

    AT32F435/437 Series Reference Manual 20.6.6 Message reception Register configuration The CAN_RFIx, CAN_RFCx, CAN_RFDTLx and CAN_RFDTHx registers can be used by user applications to obtain valid messages. Message reception The CAN controller boasts two FIFO with three levels to receive messages. FIFO rule is adopted. When the message is received correctly and has passed the identifier filtering, it is regarded as a valid message and is stored in the corresponding FIFO.
  • Page 410: Table 20-1 Can Register Map And Reset Values

    AT32F435/437 Series Reference Manual 20.7 CAN registers These peripheral registers must be accessed by words (32 bits). Table 20-1 CAN register map and reset values Register name Offset Reset value MCTRL 000h 0x0001 0002 MSTS 004h 0x0000 0C02 TSTS 008h 0x1C00 0000 00Ch 0x0000 0000...
  • Page 411 AT32F435/437 Series Reference Manual FACFG 21Ch 0x0000 0000 Reserved 220h~23Fh FB0F1 240h 0xXXXX XXXX FB0F2 244h 0xXXXX XXXX FB1F1 248h 0xXXXX XXXX FB1F2 24Ch 0xXXXX XXXX … … … FB27F1 318h 0xXXXX XXXX FB27F2 31Ch 0xXXXX XXXX 20.7.1 CAN control and status registers 20.7.1.1 CAN master control register (CAN_MCTRL) Register Reset value...
  • Page 412 AT32F435/437 Series Reference Manual 1: The new incoming message is discarded. Multiple message transmit sequence rule 0: The message with the smallest identifier is first Bit 2 MMSSR transmitted. 1: The message with the first request order is first transmitted. Doze mode enable 0: Sleep mode is disabled.
  • Page 413 AT32F435/437 Series Reference Manual Note: This bit is cleared by software (writing 1 to itself) Sleep mode is left when a SOF is detected on the bus. When QDZIEN=1, this bit will generate a status change interrupt. Error occur interrupt flag 0: No error interrupt or no condition for error interrupt flag 1: Error interrupt is generated.
  • Page 414 AT32F435/437 Series Reference Manual pending in the mailbox 2. Transmit mailbox 1 empty flag Bit 27 TM1EF This bit is set by hardware when no transmission is pending in the mailbox 1. Transmit mailbox 0 empty flag Bit 26 TM0EF This bit is set by hardware when no transmission is pending in the mailbox 0.
  • Page 415 AT32F435/437 Series Reference Manual request on mailbox 1. Clearing the message transmission on mailbox 1 will clear this bit. Setting by this software has no effect when the mailbox 1 is free. Bit 14: 12 Reserved resd Kept at its default value. Transmit mailbox 1 transmission error flag 0: No error 1: Mailbox 1 transmission error...
  • Page 416 AT32F435/437 Series Reference Manual This bit indicates whether the mailbox 0 transmission is successful or not. It is cleared by software writing 1. Transmit mailbox 0 transmission completed flag 0: Transmission is in progress 1: Transmission is completed Note: This bit is set by hardware when the transmission/abort Bit 0 TM0TCF rw1c...
  • Page 417 AT32F435/437 Series Reference Manual If there are more than two messages pending in the FIFO 0, the software has to release the FIFO 1 to access the second message. Receive FIFO 1 overflow flag 0: No overflow 1: Receive FIFO 1 overflow Bit 4 RF1OF rw1c...
  • Page 418 AT32F435/437 Series Reference Manual the EPF is set by hardware. Error active interrupt enable 0: Error warning interrupt disabled Bit 8 EAIEN 1: Error warning interrupt enabled Note: EOIF is set only when this interrupt is enabled and the EAF is set by hardware. Bit 7 Reserved resd...
  • Page 419 AT32F435/437 Series Reference Manual Note: This field is used to indicate the current error type. It is set by hardware according to the error condition detected on the CAN bus. It is cleared by hardware when a message has been transmitted or received successfully. If the error code 7 is not used by hardware, this field can be set by software to monitor the code update.
  • Page 420: Figure 20-14 Transmit And Receive Mailboxes

    AT32F435/437 Series Reference Manual There are three transmit mailboxes and two receive mailboxes. Each receive mailbox has 3-level depth of FIFO, and can only access to the first received message in the FIFO. Each mailbox contains four registers. Figure 20-14 Transmit and receive mailboxes CAN_RFI0 CAN_RFI1...
  • Page 421 AT32F435/437 Series Reference Manual message. A transmit message can contain from 0 to 8 data bytes. 20.7.2.3 Transmit mailbox data low register (CAN_TMDTLx) (x=0..2) All the bits in the register are write protected when the mailbox is not in empty state. Register Reset value Type...
  • Page 422 AT32F435/437 Series Reference Manual 20.7.2.7 Receive FIFO mailbox data low register (CAN_RFDTLx) (x=0..1) Note: All the receive mailbox registers are read only. Register Reset value Type Description Bit 31: 24 RFDT3 0xXX Receive FIFO data byte 3 Bit 23: 16 RFDT2 0xXX Receive FIFO data byte 2...
  • Page 423 AT32F435/437 Series Reference Manual 20.7.3.4 CAN filter FIFO association register (CAN_ FRF) Note: This register can be written only when FCS=1 in the CAN_FCTRL register (The filter is in configuration mode) Register Reset value Type Description Bit 31: 28 Reserved 0x00000 resd Kept at its default value...
  • Page 424: Figure 21-1 Block Diagram Of Otgfs Structure

    AT32F435/437 Series Reference Manual 21 Universal serial bus full-seed device interface (OTGFS) As a full-speed dual-role device, the OTGFS is fully compliant with the Universal Serial Bus Specification Revision2.0. 21.1 USBFS structure Figure 21-1 shows the block diagram of the OTGFS structure. The OTGFS module is connected to the AHB and has a dedicated SRAM of 1280 bytes.
  • Page 425: Table 21-1 Otgfs Input/Output Pins

    AT32F435/437 Series Reference Manual The OTGFS supports SOF and OE pulse features: a SOF pulse generates at a SOF packet, the pulse can output to pins and the timer 2; an OE pulse generates when the OTGFS outputs data, the pulse can output to pins.
  • Page 426: Figure 21-2 Otgfs Interrupt Hierarchy

    AT32F435/437 Series Reference Manual as 0xC, and set PWRDOWN=1 Enable OTG2 in CRM, and configure PC9 multiplexed function OTGFS2_OE register as 0xB 21.4 OTGFS interrupts Figure 21-2 shows the OTGFS interrupt hierarchy. Refer to the OTGFS interrupt register (OTGFS_GINTSTS) and OTGFS interrupt mask register (OTGFS_GINTMSK). Figure 21-2 OTGFS interrupt hierarchy CORE Interrupt...
  • Page 427: Table 21-2 Otgfs Transmit Fifo Sram Allocation

    AT32F435/437 Series Reference Manual 1. Program the following fields in the global AHB configuration register:  Global interrupt mask bit = 0x1  Non-periodic transmit FIFO empty level  Periodic transmit FIFO empty level 2. Program the following fields in the global AHB configuration register: ...
  • Page 428 AT32F435/437 Series Reference Manual 1. OTGFS receive FIFO size register (OTGFS_GRXFSIZ) OTGFS_GRXFSIZ.RXFDEP = rx_fifo_size  2. Endpoint 0 TX FIFO size register (OTGFS_DIEPTXF0)  OTGFS_DIEPTXF0.INEPT0TXDEP = tx_fifo_size[0]  OTGFS_DIEPTXF0.INEPT0TXSTADDR = rx_fifo_size 3. Device IN endpoint transmit FIFO#1 size register (OTGFS_DIEPTXF1) ...
  • Page 429: Table 21-3 Otgfs Internal Storage Space Allocation

    AT32F435/437 Series Reference Manual (3) Internal storage space allocation Table 21-3 OTGFS internal storage space allocation FIFO Name Data SRAM Size Receive FIFO rx_fifo_size Non-periodic transmit FIFO tx_fifo_size[0] Periodic transmit FIFO tx_fifo_size[1] Configure the following registers according to the above mentioned: 1.
  • Page 430 AT32F435/437 Series Reference Manual 10. Configure the HFIR register according to the selected PHY clock value 11. Select the size of the receive FIFO by setting the OTGFS_GRXFSIZ register 12. Select the start address and size of the non-periodic transmit FIFO by setting the OTGFS_GNPTXFSIZ register 13.
  • Page 431: Figure 21-3 Writing The Transmit Fifo

    AT32F435/437 Series Reference Manual 21.5.3.4 Queue depth Up to 8 interrupt and synchronous transfer requests are supported in the periodic hardware transfer request queue; while up to 8 control and bulk transfer requests are allowed in the non-periodic hardware transfer request queue. ...
  • Page 432: Figure 21-4 Reading The Receive Fifo

    AT32F435/437 Series Reference Manual Figure 21-4 Reading the receive FIFO Start RXFLVL interrupt? Unmask RXFLVL Unmask RXFLVL Mask RXFLVL interrupt interrupt interrupt Read the received packet from the Read Receive FIFO GRXSTSP PKTSTS=0x2 ? BCNT > 0? 21.5.3.5 Special cases (1) Handling babble conditions The OTGFS controller handles two cases of babble: packet babble and port babble.
  • Page 433: Figure 21-5 Hfir Behavior When Hfirrldctrl=0X0

    AT32F435/437 Series Reference Manual Figure 21-5 shows the HFIR behavior when the HFIRRLDCTRL is set to 0x0 in the OTGFS_HFIR register. Figure 21-5 HFIR behavior when HFIRRLDCTRL=0x0 (3)SOF Lost Synchronization Due to HFIR Reload HFIR DN 0 400 399 0 400 ******************** 1 ******************** ********************...
  • Page 434: Figure 21-6 Hfir Behavior When Hfirrldctrl=0X1

    AT32F435/437 Series Reference Manual Figure 21-6 HFIR behavior when HFIRRLDCTRL=0x1 (3)SOF Lost Synchronization NOT Lost Due to HFIR Reload HFIR DN 0 400 399 0 400 ******************** 1 ******************** ******************** Counter Application Load Of HFIR HFIR (6)SOF back in (2)HFIR Reloaded Synchronization (5)New HFIR Value (1)Old HFIR Value...
  • Page 435 AT32F435/437 Series Reference Manual receive FIFO 7. The application must read the receive packet status, and ignore it when the receive packet status is not an IN data packet 8. The controller generates the XFERC interrupt as soon as the receive packet is read 9.
  • Page 436 AT32F435/437 Series Reference Manual Mask ACK else if (DATATGLERR) Reset Error Count 21.5.3.8 Initialize bulk and control OUT/SETUP transfers Figure 21-7 shows a typical bulk or control transfer OUT/SETUP transfer operation. Refer to channel 1 (ch_1) for more information. It is necessary to send two bulk transfer OUT packets. The control transfer SETUP operation is the same, just the fact that it has only one packet.
  • Page 437: Figure 21-7 Example Of Common Bulk/Control Out/Setup And Bulk/Control In Transfer

    AT32F435/437 Series Reference Manual Figure 21-7 Example of common Bulk/Control OUT/SETUP and Bulk/Control IN transfer Application Host Device init_reg(ch_1) Non-periodic Request init_reg(ch_2) Queue write_tx_fifo Assume that this queue can (ch_1) hold 4 entries. set_ch_en(ch_2) write_tx_fifo (ch_1) ch_1 set_ch_en(ch_2) ch_2 ch_1 ch_2 DATA0 set_ch_en(ch_2)
  • Page 438 AT32F435/437 Series Reference Manual Unmask CHHLTD Disable Channel if (XactErr) Increment Error Count Unmask ACK else Reset Error Count else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (Do ping protocol for HS) else if (ACK) Reset Error Count Mask ACK...
  • Page 439 AT32F435/437 Series Reference Manual 4. The OTGFS host attempts to send an IN token in the next frame (odd) 5. The OTGFS host generates a RXFLVL interrupt as soon as an IN packet is received and written to the receive FIFO 6.
  • Page 440 AT32F435/437 Series Reference Manual Increment Error Count Unmask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) Reset Error Count Mask ACK The application can only write a request to the same channel when the remaining space in the request queue reaches the number defined in the MC field, before switching to other channels (if any).
  • Page 441: Figure 21-8 Example Of Common Interrupt Out/In Transfers

    AT32F435/437 Series Reference Manual Figure 21-8 Example of common interrupt OUT/IN transfers Application Host Device init_reg(ch_1) Periodic Request Queue init_reg(ch_2) Assume that this queue write_tx_fifo can hold 4 entries. (ch_1) set_ch_en(ch_2) ch_1 ch_2 Odd (micro) frame DATA0 XFERC interrupt init_reg(ch_1) write_tx_fifo 1 MPS (ch_1)
  • Page 442 AT32F435/437 Series Reference Manual Reset Error Count Mask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) Reset Error Count Mask ACK Before switching to other channels (if any), the application can only write packets based on the number defined in the MC filed to the transmit FIFO and request queue when the transmit FIFO has free spaces.
  • Page 443 AT32F435/437 Series Reference Manual not an IN packet (GRXSTSR.PKTSTS!= 0x0010) 8. The controller generates an XFERC interrupt as soon as the receive packet is read 9. To handle the XFERC interrupt, read the PKTCN bit in the OTGFS_HCTSIZ2 register. If the PKTCNT bit in the OTGFS_HCTSIZ2 is not equal to 0, disable the channel before re-initializing the channel for the next transfer.
  • Page 444: Figure 21-9 Example Of Common Synchronous Out/In Transfers

    AT32F435/437 Series Reference Manual 1. Initialize channel 1 (according to OTGFS channel initialization requirements). The application must set the ODDFRM bit in the OTGFS_HCCHAR2 register 2. Write the first packet to the channel 1 3. Along with the last WORD write of each packet, the host writes a request to the periodic request queue 4.
  • Page 445 AT32F435/437 Series Reference Manual else if (CHHLTD) Mask CHHLTD De-allocate Channel 21.5.4 OTGFS device mode 21.5.4.1 Device initialization The application must perform the following steps to initialize the controller during power-on or after switching a mode from host to device: 1.
  • Page 446 AT32F435/437 Series Reference Manual  OTGFS_DOEPTSIZ0.SUPCNT = 0x3(to receive up to 3 consecutive SETUP packets) At this point, all initialization required to receive SETUP packets is done. 21.5.4.3 Endpoint initialization on enumeration completion This section describes the operations required for the application to perform when an enumeration completion interrupt signal is detected: ...
  • Page 447 AT32F435/437 Series Reference Manual 2. Once the endpoint is activated, the controller starts decoding the tokens issued to this endpoint and sends out a valid handshake for each valid token received for the endpoint 21.5.4.7 USB endpoint deactivation This section describes how to deactivate an existing endpoint. Disable the suspended transfer before performing endpoint deactivation.
  • Page 448 AT32F435/437 Series Reference Manual  The application can receive up to 64-byte data for a single IN data transfer of control endpoint 0. If the application expects to receive more than 64-byte data during data IN stage, it must re-enable the endpoint to receive another 64-byte data, and it must continue this operation until the completion of all data transfers in data stage ...
  • Page 449: Figure 21-10 Read Receive Fifo

    AT32F435/437 Series Reference Manual endpoint, and the start of the data stage. After this request is popped from the receive FIFO, the controller triggers a Setup interrupt on the specified control OUT endpoint  Data OUT packet mode: PKTSTS = DataOUT, BCnt =size of the received data OUT packet (0 ≤ BCNT ≤...
  • Page 450 AT32F435/437 Series Reference Manual of the NAK status bit and EPENA bit in the OTGFS_DOEPCTLx register. The SUPCNT bit is decremented each time the control endpoint receives a SETUP packet. If the SUPCNT bit is not programmed to a proper value before receiving a SETUP packet, the controller still receives the SETUP packet and decrements the SUPCNT bit, but the application may not be able to determine the exact number of SETUP packets received in the SETUP stage of a control transfer.
  • Page 451: Figure 21-11 Setup Data Packet Flowchart

    AT32F435/437 Series Reference Manual Figure 21-11 SETUP data packet flowchart Waiting for DOEPINTn.SETUP B2BSTUP Interrupt bit set? rem_supcnt = setup_addr = rd_reg(DOEPTSIZn) rd_reg(DOEPDMAn) setup_cmd[31:0] = mem[4-2* rem_supcnt] setup_cmd[31:0] = mem[setup_addr-8] setup_cmd[63:32] = mem[5-2* rem_supcnt] setup_cmd[63:32] = mem[setup_addr-4] Find setup cmd type Read Write ctrl-rd/wr/2 stage...
  • Page 452 AT32F435/437 Series Reference Manual application can first write into the endpoint control register before writing the data into the data FIFO. Normally, except for setting the endpoint enable bit, the application must do a read modify write on the OTGFS_DIEPCTLx register to avoid modifying the contents of the register. If the space is enough, the application can write multiple data packets for the same endpoint into the transmit FIFO.
  • Page 453 AT32F435/437 Series Reference Manual 6. If there are no data in the FIFO on a received IN token and the packet count for the endpoint is 0, the controller generates an “IN token received when FIFO is empty” interrupt, and the NAK bit for the endpoint is not set.
  • Page 454 AT32F435/437 Series Reference Manual  If there is no space in the receive FIFO, synchronous or non-synchronous data packets are ignored and not written to the receive FIFO. Besides, the non-synchronous OUT tokens receive a NAK handshake response.  In all the above-mentioned cases, the packet count is not decremented because no data is written to the receive FIFO.
  • Page 455: Figure 21-12 Bulk Out Transfer Block Diagram

    AT32F435/437 Series Reference Manual Figure 21-12 BULK OUT transfer block diagram Host Device Application XFERSIZE = 512bytes int_out_ep PKTCNT = 1 wr_reg(DOEPTSIZn) EPENA = 1 CNAK = 1 wr_reg(DOEPCTLn) 512 bytes xact_1 idle until intr On new xfer or RXFIFO not rcv_out_pkt() empty idle until intr...
  • Page 456 AT32F435/437 Series Reference Manual 2. For synchronous OUT data transfers, the transfer size and packet count must be set to the number of the largest-packet-size packets that can be received in a single frame and not exceed this size. Synchronous OUT data transfer cannot span more than one frame. ...
  • Page 457 AT32F435/437 Series Reference Manual endpoint of the frame before the frame to be transmitted. For example, to send data on the frame n, enable the endpoint of the frame n-1. Additionally, the OTGFS controller schedules the synchronous transfers by setting Even/Odd frame bits. [Synchronous IN transfer interrupt] The following interrupts must be processed to ensure successful scheduling of the synchronous transfers.
  • Page 458 AT32F435/437 Series Reference Manual The INCOMPISOIN interrupt in the OTGFS_GINTSTS register is a global interrupt. Therefore, when more than one synchronous endpoints are in active state, the application must determine which one of the synchronous IN endpoints has not yet completed data transfers. To achieve this, read the DSTS and DIEPCTLx bits of all synchronous endpoints.
  • Page 459 AT32F435/437 Series Reference Manual 6. Wait for the endpoint disable interrupt in the OTGFS_DOEPINTx register, and enable the endpoint to receive new data in the next frame by following the steps listed in “SETUP/Data IN/Status OUT”. Because the controller can take some time to disable the endpoint, the application may not be able to receive the data in the next frame after receiving wrong synchronous data.
  • Page 460 AT32F435/437 Series Reference Manual  The application cannot transmit a zero-length data packet at the end of a transfer. But it can transmit a single zero-length data packet in itself, provided packet count [epnum] = 1, mc[epnum] = packet count [epnum] 2.
  • Page 461: Figure 21-13 Csr Memory Map

    AT32F435/437 Series Reference Manual are transmitted on the USB line. 8. The assertion of the XFERC interrupt in the OTGFS_DIEPINTx register, with or without the INTKNTXFEMP interrupt, indicates the successful completion of an interrupt IN transfer. When reading the OTGFS_DIEPTSIZx register, only transfer size =0 and packet count =0 indicate that all data are transmitted on the USB line.
  • Page 462: Table 21-4 Otgfs Register Map And Reset Values

    AT32F435/437 Series Reference Manual The OTGFS control and status registers contain OTGFS global register, host mode register, device mode register, data FIFO register, power and clock control register. 1. OTGFS global registers: They are active in both host and device modes. The register acronym is G. 2.
  • Page 463 AT32F435/437 Series Reference Manual OTGFS_HPTXSTS 0x410 0x0008 0100 OTGFS_HAINT 0x414 0x0000 0000 OTGFS_HAINTMSK 0x418 0x0000 0000 OTGFS_HPRT 0x440 0x0000 0000 OTGFS_HCCHAR0 0x500 0x0000 0000 OTGFS_HCINT0 0x508 0x0000 0000 OTGFS_HCINTMSK0 0x50C 0x0000 0000 OTGFS_HCTSIZ0 0x510 0x0000 0000 OTGFS_HCCHAR1 0x520 0x0000 0000 OTGFS_HCINT1 0x528 0x0000 0000...
  • Page 464 AT32F435/437 Series Reference Manual OTGFS_HCINT9 0x628 0x0000 0000 OTGFS_HCINTMSK9 0x62C 0x0000 0000 OTGFS_HCTSIZ9 0x630 0x0000 0000 OTGFS_HCCHAR10 0x640 0x0000 0000 OTGFS_HCINT10 0x648 0x0000 0000 OTGFS_HCINTMSK10 0x64C 0x0000 0000 OTGFS_HCTSIZ10 0x650 0x0000 0000 OTGFS_HCCHAR11 0x660 0x0000 0000 OTGFS_HCINT11 0x668 0x0000 0000 OTGFS_HCINTMSK11 0x66C 0x0000 0000...
  • Page 465 AT32F435/437 Series Reference Manual OTGFS_DIEPTSIZ1 0x930 0x0000 0000 OTGFS_DTXFSTS1 0x938 0x0000 0200 OTGFS_DIEPCTL2 0x940 0x0000 0000 OTGFS_DIEPINT2 0x948 0x0000 0080 OTGFS_DIEPTSIZ2 0x950 0x0000 0000 OTGFS_DTXFSTS2 0x958 0x0000 0200 OTGFS_DIEPCTL3 0x960 0x0000 0000 OTGFS_DIEPINT3 0x968 0x0000 0080 OTGFS_DIEPTSIZ3 0x970 0x0000 0000 OTGFS_DTXFSTS3 0x978 0x0000 0200...
  • Page 466 AT32F435/437 Series Reference Manual OTGFS_DOEPCTL5 0xBA0 0x0000 0000 OTGFS_DOEPINT5 0xBA8 0x0000 0080 OTGFS_DOEPTSIZ5 0xBB0 0x0000 0000 OTGFS_DOEPCTL6 0xBC0 0x0000 0000 OTGFS_DOEPINT6 0xBC8 0x0000 0080 OTGFS_DOEPTSIZ6 0xBD0 0x0000 0000 OTGFS_DOEPCTL7 0xBE0 0x0000 0000 OTGFS_DOEPINT7 0xBE8 0x0000 0080 OTGFS_DOEPTSIZ7 0xBF0 0x0000 0000 OTGFS_PCGCCTL 0xE00 0x0000 0000...
  • Page 467 AT32F435/437 Series Reference Manual 1: PTXFEMP (GINTSTS) interrupt indicates that the periodic TxFIFO is fully empty Accessible in both host mode and device modes Non-Periodic TxFIFO empty level In host mode, this bit indicates when the non-periodic TxFIFO empty interrupt (NPTXFEMP in GINTSTS) is triggered.
  • Page 468 AT32F435/437 Series Reference Manual Bit 9: 3 Reserved 0x00 resd Kept at its default value. Accessible in both host mode and device modes FS Timeout calibration The number of PHY clocks that the application programs in these bits is added to the full-speed interpacket timeout duration in order to compensate for any additional latency introduced by the PHY.
  • Page 469 AT32F435/437 Series Reference Manual bit, but must first ensure that the controller is not in the process of a transaction. The application must only write to this bit after checking that the controller is neither reading from nor writing to the RxFIFO. The application must wait until the controller clears this bit, before performing other operations.
  • Page 470 AT32F435/437 Series Reference Manual 21.6.3.6 OTGFS interrupt register (OTGFS_GINTSTS) This register interrupts the application due to system-level events in the current mode (device or host mode), as shown in Figure 21-2. Some of the bits in this register are valid only in host mode, while others are valid in device mode only. Besides, this register indicates the current mode.
  • Page 471 AT32F435/437 Series Reference Manual indicate that there is at least one synchronous OUT endpoint with incomplete transfers in the current frame. This interrupt is generated along with the End of Periodic Frame Interrupt bit in this register. Accessible in device mode only Incomplete Isochronous IN Transfer The controller sets this interrupt to indicate that there is at Bit 20...
  • Page 472 AT32F435/437 Series Reference Manual Accessible in device mode only Early suspend Bit 10 ERLYSUSP rw1c The controller sets this bit to indicate that the idle state has been detected on the USB bus for 3 ms. Bit 9: 8 Reserved resd Kept at its default value.
  • Page 473 AT32F435/437 Series Reference Manual Mode mismatch interrupt The controller sets this bit when the application is attempting to access: A host-mode register, when the controller is running in device mode A device-mode register, when the controller is running in host mode An OKAY response occurs when the register access is completed on the AHB, but it is ignored by the controller internally, and does not affect the operation of the...
  • Page 474 AT32F435/437 Series Reference Manual USB suspend interrupt mask Accessible in device mode only Bit 10 ERLYSUSPMSK Early suspend interrupt mask Bit 9: 8 Reserved resd Kept at its default value. Accessible in device mode only Bit 7 GOUTNAKEFFMSK Global OUT NAK effective mask Accessible in device mode only Bit 6 GINNAKEFFMSK...
  • Page 475 AT32F435/437 Series Reference Manual Packet status Indicates the status of the received data packet. 0001: Global OUT NAK (triggers an interrupt) 0010: OUT data packet received Bit 20: 17 PKTSTS 0011: OUT transfer completed (triggers an interrupt) 0100: SETUP transaction completed (triggers an interrupt) 0110: SETUP data packet received Others: Reserved...
  • Page 476 AT32F435/437 Series Reference Manual 21.6.3.11 OTGFS non-periodic Tx FIFO size/request queue status register (OTGFS_GNPTXSTS) This register is valid in host mode only. It is a read-only register that contains the available space information for the Non-periodic TxFIFO and the Non-periodic Transmit Request Queue. Register Reset value Type...
  • Page 477 AT32F435/437 Series Reference Manual USB communication. 0: Power down enable 1: Power down disable (Transceiver active) Bit 15: 0 Reserved 0x0000 resd Kept at its default value. 21.6.3.13 OTGFS controller ID register (OTGFS_GUID) This is a read-only register containing the production ID. Register Reset value Type...
  • Page 478 AT32F435/437 Series Reference Manual 1: FS/LS-only, even if the connected device supports high-speed. FS/LS PHY clock select When the controller is in FS host mode: 01: PHY clock is running at 48MHz Others: Reserved When the controller is in LS host mode: Bit 1: 0 FSLSPCLKSEL 00: Reserved...
  • Page 479 AT32F435/437 Series Reference Manual 21.6.4.4 OTGFS host periodic Tx FIFO/request queue register (OTGFS_HPTXSTS) This is a ready-only register containing the free space information of the periodic Tx FIFO and the periodic transmit request queue. Register Reset value Type Description Top of the periodic transmit request queue) Indicates that the MAC is processing the request from the periodic transmit request queue.
  • Page 480 AT32F435/437 Series Reference Manual 21.6.4.7 OTGFS host port control and status register ( OTGFS_HPRT) This register is valid only in host mode. Currently, the OTG host supports only one port. This register contains USB port-related information such as USB reset, enable, suspend, resume, connect status and test mode, as show in Figure 21-2.
  • Page 481 AT32F435/437 Series Reference Manual resume/remote wakeup detected interrupt disconnect detected interrupt bit in the controller interrupt register. The controller can still clear this bit, even if the device is disconnected with the host. 0: Port not in suspend mode 1: Port in suspend mode Port resume The application sets this bit to drive resume signaling on the port.
  • Page 482 AT32F435/437 Series Reference Manual that channel is complete. The application must wait for the generation of the channel disabled interrupt before treating the channel as disabled. Odd frame This bit is set / cleared by the application to indicate that the OTG host must perform a transfer in an odd frame.
  • Page 483 AT32F435/437 Series Reference Manual bus: CRC check failure Timeout Bit stuffing error EOP error This bit can only be set by the controller. The application must write 1 to clear this bit. Bit 6 Reserved resd Kept at its default value. ACK response received/Transmitted interrupt Bit 5 rw1c...
  • Page 484 AT32F435/437 Series Reference Manual indicate normal completion of the transfer. Transfer size For an OUT transfer, this field indicates the number of data bytes the host sends during a transfer. For an IN transfer, this field indicates the buffer size that Bit 18: 0 XFERSIZE 0x00000...
  • Page 485 AT32F435/437 Series Reference Manual Writing 1 to this bit clears the global OUT NAK. Set global OUT NAK Writing to this bit sets the global OUT NAK. The application uses this bit to send a NAK handshake on Bit 9 SGOUTNAK all OUT endpoints.
  • Page 486: Table 21-5 Minimum Duration For Software Disconnect

    AT32F435/437 Series Reference Manual Table 21-5 Minimum duration for software disconnect Operating speed Device state Minimum duration Full speed Suspend 1ms + 2.5us Full speed Idle 2.5us No idle or suspend Full speed 2.5us (performing transfers) 21.6.5.3 OTGFS device status register (OTGFS_DSTS) This register indicates the status of the controller related to OTGFS events.
  • Page 487 AT32F435/437 Series Reference Manual IN endpoint NAK effective mask Bit 6 INEPTNAKMSK 0: Interrupt masked 1: Interrupt unmasked IN token received with EP mismatch mask Bit 5 INTKNEPTMISMSK 0: Interrupt masked 1: Interrupt unmasked IN token received when TxFIFO empty mask Bit 4 INTKNTXFEMPMSK 0x0 0: Interrupt masked...
  • Page 488 AT32F435/437 Series Reference Manual 21.6.5.6 OTGFS device all endpoints interrupt mask register (OTGFS_DAINT) When an event occurs on an endpoint, The IN/OUT endpoint interrupt bits in the OTGS_DAINT register can be used to interrupt the application. There is one interrupt pit per endpoint, up to 8 interrupt bits for OUT endpoints and 8 bits for IN endpoints.
  • Page 489 AT32F435/437 Series Reference Manual – Endpoint disabled – Transfer completed. Endpoint disable The application sets this bit to stop data transmission on an endpoint. The application must wait for the endpoint Bit 30 EPTDIS disabled interrupt before treating the endpoint as disabled.
  • Page 490 AT32F435/437 Series Reference Manual 21.6.5.10 OTGFS device IN endpoint-x control register (OTGFS_DIEPCTLx) (x=x=1… 7, where x is endpoint number) The application uses this register to control the behavior of the endpoints other than endpoint 0. Register Reset value Type Description Endpoint enable The application sets this bit to start transmitting data on an endpoint.
  • Page 491 AT32F435/437 Series Reference Manual 0: Stall all invalid tokens 1: Stall all valid tokens Bit 20 Reserved resd Kept at its default value. Endpoint type This is the transfer type supported by this logical endpoint. 00: Control Bit 19: 18 EPTYPE 01: Synchronous 10: Bulk...
  • Page 492 AT32F435/437 Series Reference Manual 21.6.5.11 OTGFS device control OUT endpoint 0 control register (OTGFS_DOEPCTL0) This section describes the control OUT endpoint 0 control register. Non-zero control endpoints use registers for endpoints 1-7. Register Reset value Type Description Endpoint enable The application sets this bit to start transmitting data on endpoint 0.The controller clears this bit before setting any Bit 31 EPTENA...
  • Page 493 AT32F435/437 Series Reference Manual 21.6.5.12 OTGFS device control OUT endpoint-x control register (OTGFS_DOEPCTLx) (x= x=1… 7, where x if endpoint number) This application uses this register to control the behavior of all endpoints other than endpoint 0. Register Reset value Type Description Endpoint enable...
  • Page 494 AT32F435/437 Series Reference Manual this bit, but the controller never. Snoop mode This bit configures the endpoint to Snoop mode. In this Bit 20 mode, the controller does not check the correctness of OUT packets before transmitting OUT packets to the application memory.
  • Page 495 AT32F435/437 Series Reference Manual 21.6.5.13 OTGFS device IN endpoint-x interrupt register (OTGFS_DIEPINTx) (x=0… 7, where x if endpoint number) This register indicates the status of an endpoint when USB and AHB-related events occurs, as shown in Figure 21-2 When the IEPINT bit of the OTGFS_GINTSTS register is set, the application must first read the OTGFS_DAINT register to get the exact endpoint number in which the event occurs, before reading the endpoint interrupt registers.
  • Page 496 AT32F435/437 Series Reference Manual received. SETUP phase done Applies to control OUT endpoints only. Indicates that the SETUP stage for the control endpoint is Bit 3 SETUP rw1c complete and no more back-to-back SETUP packets were received for the current control transfer. Upon this interrupt, the application can decode the received SETUP data packets.
  • Page 497 AT32F435/437 Series Reference Manual from the external memory is written to the transmit FIFO. The controller decrements this field every time a packet from the receive FIFO is written to the external memory. 21.6.5.17 OTGFS device IN endpoint-x transfer size register (OTGFS_DIEPTSIZx) (x=1…...
  • Page 498 AT32F435/437 Series Reference Manual 21.6.5.19 OTGFS device OUT endpoint-x transfer size register (OTGFS_DOEPTSIZx) (x=1… 7, where x is endpoint number) The application must set this register before enabling endpoint x. Once the endpoint x is enabled using the endpoint enable pin in the device endpoint x control register, the controller modifies this register. The application can only read this register as long as the controller clears the endpoint enable bit.
  • Page 499: Figure 22-1 Acc Interrupt Mapping Diagram

    AT32F435/437 Series Reference Manual 22 HICK auto clock calibration (ACC) 22.1 ACC introduction HICK auto clock calibration (HICK ACC), which uses the SOF signal (1 ms of period) generated as a reference signal, implements the sampling and calibration for the HICK clocks. The main purpose of this module is to provide a clock of 48MHz±0.25% for the USB device.
  • Page 500: Figure 22-2 Acc Block Diagram

    AT32F435/437 Series Reference Manual  CRM_HICKCAL: the HICKCAL bit in the CRM module. This signal is used to calibrate the HICK in bypass mode. The value is defined by the HICKCAL[7: 0] in the CRM_CTRL register.  CRM_HICKTRIM: the HICKTRIM bit in the CRM module. This signal is used to calibrate the HICK in bypass mode.
  • Page 501: Figure 22-3 Cross-Return Algorithm

    AT32F435/437 Series Reference Manual 0.5 steps from the target frequency (8MHz) Figure 22-3 Cross-return algorithm C3 = 8020 C2 = 8000 C1 = 7980 From the above figure, auto calibration function will adjust the HICKCAL or HICKTRIM according to the specified step as soon as the condition for triggering auto calibration is reached.
  • Page 502: Table 22-2 Acc Register Map And Reset Values

    AT32F435/437 Series Reference Manual 22.6.1 ACC register map Table 22-2 ACC register map and reset values Register name Offset Reset value ACC_STS 0x00 0x0000 000 ACC_CTRL1 0x04 0x0000 0100 ACC_CTRL2 0x08 0x0000 2080 ACC_C1 0x0C 0x0000 1F2C ACC_C2 0x10 0x0000 1F40 ACC_C3 0x14 0x00000 1F54...
  • Page 503 AT32F435/437 Series Reference Manual 0: Interrupt generation disabled 1: ACC interrupt is generated when CALRDY=1 in the ACC_STS register RSLOST error interrupt enable This bit is set or cleared by software. Bit 4 EIEN 0: Interrupt generation disabled 1: ACC interrupt is generated when RSLOST=1 in the ACC_STS register Bit 3: 2 Reserved...
  • Page 504 AT32F435/437 Series Reference Manual 22.6.6 Compare value 2 (ACC_C2) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Forced to 0 by hardware Compare 2 This value defines the number of clocks sampled for 8MHz (ideal frequency) clock in 1ms period , and its default value is 8000 (theoretical value).
  • Page 505: Figure 23-1 Irtmr Block Diagram

    AT32F435/437 Series Reference Manual 23 Infrared timer (IRTMR) The IRTMR (Infrared Timer) is used to generate the IR_OUT signal that drives the infrared LED so as to achieve infrared control. The IR_OUT signals consists of a low-frequency modulation envelope and high-frequency carrier signals. The low-frequency modulation envelope signal selects from TMR10_C1OUT, USART1 and USART through the IR_SRC_SEL[1: 0] bit in the SCFG_CFG1 register, while the high-frequency carrier signal is provided by the TMR11_C1OUT register.
  • Page 506 AT32F435/437 Series Reference Manual 24 External memory controller (XMC) 24.1 XMC introduction XMC peripheral block can translate the AHB signals into the external memory signals and vice versa. It boasts two chip-select signals for interfacing up to external memories at a time. The supported external memories include a NAND Flash and a static memory device featuring multiplexed signals or additional address latch function.
  • Page 507 AT32F435/437 Series Reference Manual  Multi-memory area ping-pong access Automatic refresh operation of software-programmable refresh rate   Supports self-refresh mode  Supports power-down mode  SDRAM power-on initialization through software  CAS latency can be configured 1/2/3 SDRAM clock cycles ...
  • Page 508: Figure 24-1 Xmc Block Diagram

    AT32F435/437 Series Reference Manual 24.3 XMC architecture 24.3.1 Block diagram Figure 24-1 XMC block diagram Address/Data bus XMC registers AHB XMC memory AHB interface interface Central memory XMC_A[25:0] controller XMC_D[15:0] XMC_NOE NOR/PSRAM memory interface XMC_NWE XMC_NWAIT XMC_NE[4:1] XMC_NADV NAND bank2 memory interface XMC_LB XMC_UB XMC_CLK...
  • Page 509: Table 24-2 Nand Pins

    AT32F435/437 Series Reference Manual XMC_A[x] Output Address bus XMC_NOE Output Output enable signal XMC_NWE Output Write enable signal XMC_LB and XMC_UB Output Byte select signal XMC_D[15: 0] Read input/write output Data bus/multiplexed address data XMC_NWAIT Input Wait signal Table 24-2 NAND pins Pin name Description XMC_NCE[2]...
  • Page 510: Figure 24-2 Xmc Memory Banks

    AT32F435/437 Series Reference Manual Figure 24-2 XMC memory banks Memory Address Memory banks chip select signals 6000 0000h NOR/PSRAM bank1 64 MB XMC_NE[1] 63FF FFFFh 6400 0000h NOR/PSRAM bank2 64 MB XMC_NE[2] 67FF FFFFh 6800 0000h NOR/PSRAM bank3 64 MB XMC_NE[3] 6BFF FFFFh 6C00 0000h...
  • Page 511: Table 24-5 Memory Bank Selection

    AT32F435/437 Series Reference Manual Some HADDR bits are used to select which bank to access to, as shown in Table 24-3. Table 24-5 Memory bank selection HADDR[31: 28] HADDR[27: 26] 00: bank1 0110: NOR/PSRAM 11: bank4 HADDR[31: 28] HADDR[27] HADDR[17: 16] 00: Data area 01: Command area 0: Regular space...
  • Page 512: Table 24-7 16-Bit Sdram Address Mapping

    AT32F435/437 Series Reference Manual Table 24-7 16-bit SDRAM address mapping HADDR (AHB address line) Row size 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank Reserved Row[10:0]...
  • Page 513: Table 24-9 Address Translation Between Haddr And External Memory

    AT32F435/437 Series Reference Manual Table 24-9 Address translation between HADDR and external memory External memory data Accessible maximum memory Address connection width space (bits) HADDR[25: 0] is linked to XMC_A[25: 0]. In multiplexed and synchronous mode, 8-bit 64 Mbyte x8 =512 Mbit HADDR[15: 0] is connected to XMC_D[15: 0] during address latch period.
  • Page 514: Table 24-11 Nor/Psram Parameter Registers

    AT32F435/437 Series Reference Manual Table 24-11 NOR/PSRAM parameter registers Parameter Function Access mode Unit register ADDRST Address set-up time 1, 2, A, B, C, D and multiplexed HCLK cycle ADDRHT Address-hold time D and multiplexed HCLK cycle DTST Data set-up time 1, 2, A, B, C, D and multiplexed HCLK cycle DTLAT...
  • Page 515: Figure 24-3 Nor/Psram Mode 1 Read Access

    AT32F435/437 Series Reference Manual Figure 24-3 NOR/PSRAM mode 1 read access t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal Address signals XMC_A[25:0] Memory address XMC_NOE High XMC_NWE Data signals XMC_LB XMC_UB Data from external memory High-Z XMC_D[15:0] XMC capture data Figure 24-4 NOR/PSRAM mode 1 write access...
  • Page 516: Figure 24-5 Nor/Psram Mode 2 Read Access

    AT32F435/437 Series Reference Manual Bit 14 RWTD: Read-write timing different NWSEN: NWAIT synchronous Bit 13 transfer enable Bit 12 WEN: Write enable Configure according to needs. Bit 11 NWTCFG: NWAIT timing configuration Bit 10 WRAPEN: Wrapped enable Bit 9 NWPOL: NWAIT polarity Configure according to memory specifications.
  • Page 517: Figure 24-6 Nor/Psram Mode 2 Write Access

    AT32F435/437 Series Reference Manual Figure 24-6 NOR/PSRAM mode 2 write access t care DTST+1 ADDRST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals Memory address XMC_A[25:0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB XMC_D[15:0] Data from XMC High-Z 24.4.2.2 Read/write operation with different timings The timing of read operation in mode A/B/C/D is based on the SRAM/NOR Flash chip select timing register (XMC_BK1TMG).
  • Page 518: Figure 24-7 Nor/Psram Mode A Read Access

    AT32F435/437 Series Reference Manual Table 24-17 Mode A— SRAM/NOR Flash chip select timing register Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x0 (Mode A) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16 BUSLAT: Bus latency...
  • Page 519: Figure 24-8 Nor/Psram Mode A Write Access

    AT32F435/437 Series Reference Manual Figure 24-8 NOR/PSRAM mode A write access Don t care DTST+1 ADDRST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_A[23:16] Address signals Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB XMC_D[15:0] Data from XMC High-Z Mode B As configured in Table 24-19, Table 24-20, and Table 24-21, the XMC uses mode B to access the external...
  • Page 520: Figure 24-9 Nor/Psram Mode B Read Access

    AT32F435/437 Series Reference Manual Table 24-20 Mode B— SRAM/NOR Flash chip select timing register Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x1 (Mode B) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16 BUSLAT: Bus latency...
  • Page 521: Figure 24-10 Nor/Psram Mode B Write Access

    AT32F435/437 Series Reference Manual Figure 24-10 NOR/PSRAM mode B write access t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals Memory address XMC_A[25:0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15:0] High-Z Mode C As configured in Table 24-22,...
  • Page 522: Figure 24-11 Nor/Psram Mode C Read Access

    AT32F435/437 Series Reference Manual Table 24-23 Mode C—SRAM/NOR Flash chip select timing register Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x2 (Mode C) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16 BUSLAT: Bus latency...
  • Page 523: Figure 24-12 Nor/Psram Mode C Write Access

    AT32F435/437 Series Reference Manual Figure 24-12 NOR/PSRAM mode C write access Don t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23:16] Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB XMC_D[15:0] Data from XMC High-Z Mode D As configured in Table 24-25, Table 24-26, and Table 24-27, the XMC uses mode D to access the...
  • Page 524: Figure 24-13 Nor/Psram Mode D Read Access

    AT32F435/437 Series Reference Manual Table 24-26 Mode D—SRAM/NOR Flash chip select timing register Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x3 (Mode D) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16 BUSLAT: Bus latency...
  • Page 525: Figure 24-14 Nor/Psram Mode D Write Access

    AT32F435/437 Series Reference Manual Figure 24-14 NOR/PSRAM mode D write access Don t care ADDRST+1 ADDRHT+1 DTST+1 HCLK HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals Memory address XMC_A[25:0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15:0] High-Z 24.4.2.3 Multiplexed mode...
  • Page 526: Figure 24-15 Nor/Psram Multiplexed Mode Read Access

    AT32F435/437 Series Reference Manual Table 24-29 Multiplexed mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) configuration Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16 BUSLAT: Bus latency falling edge.
  • Page 527: Figure 24-16 Nor/Psram Multiplexed Mode Write Access

    AT32F435/437 Series Reference Manual Figure 24-16 NOR/PSRAM multiplexed mode write access t care ADDRST+1 ADDRHT+1 DTST+2 HCLK HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[25:16] Memory address[25:16] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Address data Data from XMC XMC_D[15:0] Memory address[15:0] multiplex signal...
  • Page 528: Figure 24-17 Nor/Psram Synchronous Multiplexed Mode Read Access

    AT32F435/437 Series Reference Manual Bit 0 EN: Memory bank enable Table 24-31 Synchronous mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode Bit 27: 24 DTLAT: Data latency Refer to Figure 24-17 Figure 24-18 XMC_CLK cycle is HCLK cycle*(CLKPSC+1).
  • Page 529: Figure 24-18 Nor/Psram Synchronous Multiplexed Mode Write Access

    AT32F435/437 Series Reference Manual Figure 24-18 NOR/PSRAM synchronous multiplexed mode write access DTLAT+1 t care XMC_CLK Clock XMC_CLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[25:16] Memory address[25:16] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Wait signal XMC_NWAIT Address data XMC_D[15:0] Memory address[15:0] multiplex signal...
  • Page 530: Figure 24-19 Nand Read Access

    AT32F435/437 Series Reference Manual modes supported by XMC. Table 24-33 Data access width vs. external memory data width Memory Mode AHB data width Memory width Description 8-bit NAND Split into 2 XMC accesses Split into 4 XMC accesses 16-bit NAND Split into 4 XMC accesses 24.4.5 Access timings The XMC access the NAND Flash according to the timing parameters, as shown in Table 24-34 and...
  • Page 531: Figure 24-20 Nand Wait Functionality

    AT32F435/437 Series Reference Manual The user has to configure the time duration during which the NAND Flash shifts from the rising edge of the XMC_NWE to the falling edge of the XMC_NWAIT into a SPHT register, and write the last address byte into a special memory address section so that the XMC can perform write operations based on the timings of the special memory timing register, as shown in Address 3 in Figure 24-20.
  • Page 532: Table 24-36 Typical Pin Signals For Pc Card

    AT32F435/437 Series Reference Manual Table 24-36 Typical pin signals for PC card Pin name PC card XMC_NCE4_1 Chip-select 1 (CE1) XMC_NCE4_2 Chip-select 2 (CE2) XMC_A[10:0] Address bus XMC_NOE Output enable for common and attribute spaces XMC_NWE Write enable for common and attribute spaces XMC_NIORD Output enable for IO space XMC_NIOWR...
  • Page 533: Figure 24-21 Pc Card Read/Write

    AT32F435/437 Series Reference Manual Figure 24-21 PC card read/write ATST+1 HCLK ATWT+1 ATHT ATDHIZT HCLK HCLK HCLK XMC_NCE4_1 Chip select XMC_NCE4_2 signals XMC_NREG Address signals XMC_A[10:0] If write XMC_NOE High Data XMC_NWE signals XMC_D[15:0] Data from XMC High-Z If read XMC_NOE High Data...
  • Page 534: Figure 24-22 Sdram Write Access Waveforms (Trcd=2, 9 Consecutive Write Access)

    AT32F435/437 Series Reference Manual After the initialization, the SDRAM is ready to accept commands. If a system reset occurs during an on- going SDRAM access, the SDRAM device has to be reset after re-initialization in order to issue a new access to the SDRAM.
  • Page 535: Figure 24-23 Sdram Read Access Without Using Read Fifo (Trcd=2,Cl=3, And 4 Consecutive Read Accesses)

    AT32F435/437 Series Reference Manual Figure 24-23 SDRAM read access without using read FIFO (Trcd=2,CL=3, and 4 consecutive read accesses) XMC_ SDCLK XMC_ SDCS XMC_ Row 1 Col1 Col2 Col3 Col4 A[12:0] XMC_ NRAS XMC_ NCRS XMC_ SDNWE XMC_A 2'b00 [15:14] XMC_ DQ1 DQ2 DQ3 DQ4 D[15:0]...
  • Page 536: Table 24-39 Xmc Register Address Mapping

    AT32F435/437 Series Reference Manual 24.6.2 Self-refresh mode and Power-down mode The SDRAM controller supports two low-power modes: self-refresh mode and power-down mode. Self-refresh mode This mode is selected by setting CMD=101 and by configuring the Target Bank bits (BK1 and/or BK2) in the SDRAM_CMD register.
  • Page 537 AT32F435/437 Series Reference Manual XMC_BK4TMGCM 0x0A8 0xFCFC FCFC XMC_BK4TMGAT 0x0AC 0xFCFC FCFC XMC_BK4TMGIO 0xB0 0xFCFC FCFC XMC_BK1TMGWR1 0x104 0x0FFF FFFF XMC_BK1TMGWR2 0x10C 0x0FFF FFFF XMC_BK1TMGWR3 0x114 0x0FFF FFFF XMC_BK1TMGWR4 0x11C 0x0FFF FFFF XMC_EXT1 0x220 0x0000 0808 XMC_EXT2 0x224 0x0000 0808 XMC_EXT3 0x228 0x0000 0808...
  • Page 538 AT32F435/437 Series Reference Manual 1: NWAIT signal is enabled Write enable Bit 12 0: Disabled 1: Enabled NWAIT timing configuration It is valid only in synchronous mode. 0: NWAIT signal is active one data cycle before the wait Bit 11 NWTCFG state 1: NWAIT signal is active one data cycle during the wait...
  • Page 539 AT32F435/437 Series Reference Manual 100: 1024 bytes Others: Reserved. NWAIT enable during asynchronous transfer Bit 15 NWASEN 0: NWAIT signal is disabled 1: NWAIT signal is enable Read-write timing different Different timings are used for read and write operations, Bit 14 RWTD that is, the XMC_BK1TMGWR register is enabled.
  • Page 540 AT32F435/437 Series Reference Manual 24.7.1.3 SRAM/NOR Flash chip select timing register x (x=1,2,3,4) Accessed by words. Register Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value. Asynchronous mode This field is valid only when the RWTD bit is enabled. 00: Mode A Bit 29: 28 ASYNCM...
  • Page 541 AT32F435/437 Series Reference Manual bus after one read operation in multiplexed or synchronous mode. 0000: 1 HCLK cycle is inserted 0001: 2 HCLK cycles are inserted …… 1111: 16 HCLK cycles are inserted Data setup time 0000: 0 HCLK cycle is inserted Bit 15: 8 DTST 0xFF...
  • Page 542 AT32F435/437 Series Reference Manual 24.7.2 NAND Flash control registers 24.7.2.1 NAND Flash control register x (XMC_BKxCTRL) (x=2,3) Accessed by words. Register Reset value Type Description Bit 31: 20 Reserved 0x000 resd Kept at its default value. ECC page size 000: 256 bytes 001:512 bytes Bit 19: 17 ECCPGS...
  • Page 543 AT32F435/437 Series Reference Manual 0: High-level interrupt disabled 1: High-level interrupt enabled Rising edge interrupt enable Bit 3 REIEN 0: Rising edge interrupt disabled 1: Rising edge interrupt enabled Falling edge status This bit is set by hardware and cleared by software. Bit 2 0: No falling edge interrupt generated 1: Falling edge interrupt generated...
  • Page 544 AT32F435/437 Series Reference Manual This field defines the databus hold time when access to NAND Flash in a special memory. 00000000: Reserved 00000001: 1 HCLK cycle is inserted …… 11111111: 255 HCLK cycles are inserted Special memory wait time Specifies the special memory wait time when the XMC_NWE and XMC_NOE is low.
  • Page 545 AT32F435/437 Series Reference Manual Falling edge status This bit is set by hardware and cleared by software. Bit 2 0: No falling edge interrupt generated 1: Falling edge interrupt generated High-level status This bit is set by hardware and cleared by software. Bit 1 0: No high level interrupt generated 1: High level interrupt generated...
  • Page 546 AT32F435/437 Series Reference Manual Attribute memory wait time Specifies the attribute memory wait time when the XMC_NWE and XMC_NOE is low. Bit 15: 8 ATWT 0xFC 00000000: 0 HCLK cycle is inserted 00000001: 1 additional HCLK cycle is inserted …… 11111111: 255 additional HCLK cycles are inserted Attribute memory setup time This field defines the address setup time when access to...
  • Page 547 AT32F435/437 Series Reference Manual When this bit is set, it indicates that single AHB requests (single or burst) are processed as bursts. Several data will be prefetched and stored into the FIFO. 0: Single read requests are not processed as bursts 1: ingle read requests are always processed as bursts Note: The corresponding bits in the CTRL2 register are “don’t care bit”...
  • Page 548 AT32F435/437 Series Reference Manual cycles. 0000: 1 cycle 0001: 2 cycles ..1111: 16 cycles Write Recovery delay This field defines the delay between a write command and a precharge command in number of clock cycles. Bit 19: 16 0000: 1 cycle 0001: 2 cycles ..
  • Page 549 AT32F435/437 Series Reference Manual 24.7.4.3 SDRAM command register (SDRAM_CMD) Register Reset value Type Description Bit 31: 22 Reserved 0x000 resd Kept at its default value. Mode Register data Bit 22: 9 0x0000 Refer to the SDRAM specifications for details. Auto-refresh times This field defines the number of consecutive auto-refresh commands issued when MODE =“011”.
  • Page 550 AT32F435/437 Series Reference Manual Note: The programmed COUNT value must not be equal to the sum of the following timings: TWR+TRP+TRC+TRCD+4 memory clock cycles. 24.7.4.5 SDRAM status register (SDRAM_STS) Register Reset value Type Description Bit 31: 6 Reserved 0x0000000 resd Kept at its default value.
  • Page 551 AT32F435/437 Series Reference Manual 25 SDIO interface 25.1 SDIO introduction The SD/SDIO MMC card host interface (SDIO) provides an interface between the AHB peripheral bus and MultiMediaCards (MMC), SD memory cards and SDIO cards. SD memory card and SDI/O card system specifications are available through the SD card association website www.sdcard.org.
  • Page 552: Figure 25-1 Sdio "No Response" And "Response" Operations

    AT32F435/437 Series Reference Manual Figure 25-1 SDIO “no response” and “response ” operations From From From host host card to card to card to host SDIO_CMD Command Command Response SDIO_D Operation (No response) Operation (No data) Figure 25-2 SDIO multiple block read operation Data from card From From...
  • Page 553: Figure 25-4 Sdio Sequential Read Operation

    AT32F435/437 Series Reference Manual Figure 25-4 SDIO sequential read operation From From host card to card to host Stop command stops data Data from card transfer to host SDIO_CMD Command Response Command Response SDIO_D Data stream Data stop operation Data transfer operation Figure 25-5 SDIO sequential write operation From...
  • Page 554 AT32F435/437 Series Reference Manual The card identification process is described as follows: The bus is activated to confirm whether the card is connected or not. The clock frequency is at 0- 400kHz during the card identification process. The SDIO host sends a SD card, SDI/O card or MMC card. Card Initialization SD card: The SDIO host sends CMD2 (ALL_SEND_CID) to obtain its unique CID number.
  • Page 555 AT32F435/437 Series Reference Manual Data blocks will keep transferring until the host sends CMD12(STOP_TRANSMISSION). The stop command has an execution delay due to the serial command transmission and the data transfers stops after the end bit of the stop command. Data block write During block write (CMD24-27), one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block.
  • Page 556: Table 25-1 Lock/Unlock Command Structure

    AT32F435/437 Series Reference Manual bit in the CSD, part of the data can be protected, and the write protection can be changed by the application. The SET_WRITE_PROT commands set the write protection of the addressed group. The CLR_WRITE_PROT commands clear the write protection of the addressed group. The SEND_WRITE_PROT command is similar to a single block read command.
  • Page 557 AT32F435/437 Series Reference Manual When the old password is matched, the new password and its size are saved into the PWD and PWD_LEN fields, respectively. When the old password sent is not correct (in size and/or content), the LOCK_UNLOCK_FAILED error bit is set in the SDIO_STS register, and the old password is not changed.
  • Page 558: Table 25-2 Commands

    AT32F435/437 Series Reference Manual Forcing erase If the user forgot the password (PWD content), it is possible to access the card after clearing all the data on the card. This forced erase operation will erase all card data and all password data. Select a card using CMD7 (SELECT/DESELECT_CARD), if none is selected previously Define the block length with CMD16(SET_BLOCKLEN) to send in the 8-bit card lock/unlock mode, 8-bit PWD_LEN, and the number of bytes of the new password.
  • Page 559: Table 25-3 Data Block Read Commands

    AT32F435/437 Series Reference Manual [31: 26] set to 0 [25: 24] access Used only for the MMC card to switch the [23: 16] index CMD6 SWITCH operation modes modify [15: 8] value EXT_CSD register [7: 3] set to 0 [2: 0] command set This command is used to switch a card between the standby state and the send SELECT/DESEL...
  • Page 560: Table 25-4 Data Stream Read/Write Commands

    AT32F435/437 Series Reference Manual Table 25-4 Data stream read/write commands Response CMD index Type Parameter Abbreviation Description format Read data stream form the card starting READ_DAT_ CMD11 adtc [31: 0]= data address R1 from given address until UNTIL_STOP STOP_TRANSMISSION is received. Read data stream form the host starting WRITE_DAT_ CMD20...
  • Page 561: Table 25-7 Erase Commands

    AT32F435/437 Series Reference Manual Table 25-7 Erase commands Response CMD index Type Parameter Abbreviation Description format CMD32 Reserved. These command indexes cannot be used in order to maintain backward compatibility with older … versions of the MultiMedia card. CMD34 ERASE_GROUP Sets the address of the first erase group CMD35 [31: 0]=data address R1...
  • Page 562: Table 25-10 Application-Specific Commands

    AT32F435/437 Series Reference Manual Table 25-10 Application-specific commands Response CMD index Type Parameter Abbreviation Description format Indicates to the card that the next [31: 16]=RCA command application-specific CMD55 APP_CMD [15: 0]=stuff bits command rather than standard command. Used either to transfer a data block to the card or to read a data block from the card [31: 1]=stuff bits for general-purpose/application-specific...
  • Page 563: Table 25-12 R2 Response

    AT32F435/437 Series Reference Manual Table 25-12 R2 response [ 133 : 128 ] [ 127 : 1 ] Field width Value 111111 Description Start bit Transmission bit Reserved CID or CSD register End bit 25.3.2.2.4 R3 (OCR register) Code length = 48 bits. The contents of the OCR register are sent as a response to ACMD41. Table 25-13 R3 response [45 : 40]...
  • Page 564: Table 25-17 R6 Response

    AT32F435/437 Series Reference Manual 25.3.2.2.8 R6 (interrupt request) For SD I/O card only. This is a normal response to CMD3 by a memory device. Table 25-17 R6 response [45: 40] [39: 8] [7: 1] Field width Value 000011 RCA[31:16] Description Start bit Tx bit CMD3...
  • Page 565: Figure 25-6 Sdio Block Diagram

    AT32F435/437 Series Reference Manual Figure 25-6 SDIO block diagram SDIO Adapter AHB Bus Control unit SDIO_CK Adapter DMA_req Command SDIO_CMD Interface Register Path DMA_ack SDIO_INT Data SDIO_D [ 7:0 ] Path HCLK SDIOCLK 25.3.3.1 SDIO adapter SDIO_CK is a clock to the MultiMedia/SD/SDIO car provided by the host. One bit of command or data is transferred on both command and data lines with each clock cycle.
  • Page 566: Table 25-19 Command Formats

    AT32F435/437 Series Reference Manual register where the CLKDIV bit is used to define the divider factor between the SDIOCLK and the SDIO output clock. If BYPSEN = 0, the SDIO_CK output signal is driven by the SDIOCLK divided according to the CLKDIV bit; if BYPSEN = 1, the SDIO_CK output signal is directly driven by the SDIOCLK. The HFCEN is set to enable hardware flow control feature in order to avoid the occurrence of an error at transmission underflow or reception overflow.
  • Page 567: Figure 25-7 Command Channel State Machine (Ccsm)

    AT32F435/437 Series Reference Manual Table 25-22 Command path status flags Flag Description CMDRSPCMPL A response is already received (CRC OK) CMDFAIL A command response is already received (CRC fails) CMDCMPL A command is sent (does not require a response) CMDTIMEOUT Command response timeout (64 SDIO_CK cycles) DOCMD Command transfer is in progress...
  • Page 568: Figure 25-8 Sdio Command Transfer

    AT32F435/437 Series Reference Manual Figure 25-8 SDIO command transfer At least 8 SDIO_CK cycles SDIO_CMD Response CPSM status Idle Send Wait Receive Idle Send Data channel The data path subunit transfers data between the host and the cards. The databus width can be configured using the BUSWS bit in the SDIO_CLKCTRL register.
  • Page 569: Table 25-23 Data Token Formats

    AT32F435/437 Series Reference Manual  Busy: The DCSM waits for the CRC flag. If the DCSM receives a correct CRC status and is not busy, it will enter the Wait_S state. If it does not receive a correct CRC status or a timeout occurs while the DCSM is in the busy state, a CRC fail flag or timeout flag is generated.
  • Page 570 AT32F435/437 Series Reference Manual and then program the SDIO data control register (SDIO_DTCTRL): TFREN=1 (enable the SDIO card host to send data), TFRDIR=0 (from the controller to the card), TFRMODE=0 (block data transfer), DMAEN=1 (enable DMA), BLKSIZE=9 (512 bytes), and wait from SDIO_STS [10]=DTBLKCMPL.
  • Page 571: Table 25-24 A Summary Of The Sdio Registers

    AT32F435/437 Series Reference Manual SDIO interrupts There is a pin with interrupt feature on the SD interface in order to enable the SD I/O card to interrupt the MultiMedia card/SD module. In 4-bit SD mode, this pin is SDIO_D1. The SD I/O interrupts are detected when the level is active.
  • Page 572 AT32F435/437 Series Reference Manual 25.4.2 SDIO clock control register (SDIO_ CLKCTRL) The SDIO_CLKCTRL register controls the SDIO_CK output clock. Register Reset value Type Description Bit 31: 17 Reserved 0x0000 resd Kept at its default value. Clock division This field is set or cleared by software. It defines the clock Bit 16: 15 CLKDIV division relations between the SDIOCLK and the...
  • Page 573 AT32F435/437 Series Reference Manual 25.4.3 SDIO argument register (SDIO_ARG) The SDIO_ARG register contains 32-bit command argument, which is sent to a card as part of a command. Register Reset value Type Description Command argument Command argument is sent to a card as part of a Bit 31: 0 ARGU 0x0000 0000...
  • Page 574: Table 25-25 Response Type And Sdio_Rspx Register

    AT32F435/437 Series Reference Manual 25.4.5 SDIO command response register (SDIO_RSPCMD) The SDIO_RSPCMD register contains the command index of the last command response received. If the command response transmission does not contain the command index (long or OCR response), the SDIO_RSPCMD field is unknown, although it should have contained 111111b (the value of the reserved field from a response) Register Reset value...
  • Page 575 AT32F435/437 Series Reference Manual 25.4.9 SDIO data control register (SDIO_DTCTRL) The SDIO_DTCTRL register controls the data channel statue machine (DCSM). Register Reset value Type Description Bit 31: 12 Reserved 0x00000 resd Kept at its default value. SD I/O enable functions This bit is set or cleared by software.
  • Page 576 AT32F435/437 Series Reference Manual 1: Enabled Data transfer enabled bit This bit is set or cleared by software. If this bit is set, data transfer starts. The DCSM enters the Wait_S or Wait_R state, depending on the direction bit TFRDIR. The DCSM goes to the read wait state if the RDWTSTART bit is set Bit 0 TFREN...
  • Page 577 AT32F435/437 Series Reference Manual Bit 4 TXERRU Transmit BUF underrun error Bit 3 DTTIMEOUT Data timeout Command response timeout Bit 2 CMDTIMEOUT The command timeout is a fixed value of 64 SDIO_CK clock periods. Bit 1 DTFAIL Data block sent/received (CRC check failed) Bit 0 CMDFAIL Command response received (CRC check failed)
  • Page 578 AT32F435/437 Series Reference Manual RxBUF empty interrupt. 0: Disabled 1: Enabled TxBUF empty interrupt enable This bit is set or cleared by software to enable/disable the Bit 18 TXBUFEIEN TxBUF empty interrupt. 0: Disabled 1: Enabled RxBUF full interrupt enable This bit is set or cleared by software to enable/disable the Bit 17 RXBUFFIEN...
  • Page 579 AT32F435/437 Series Reference Manual This bit is set or cleared by software to enable/disable the Command response received interrupt. 0: Disabled 1: Enabled RxBUF overrun error interrupt enable This bit is set or cleared by software to enable/disable the Bit 5 RXERROIEN RxBUF overrun error interrupt.
  • Page 580: Figure 26-1 Block Diagram Of Emac

    AT32F435/437 Series Reference Manual 26 Ethernet media access control (EMAC) This module applies only to AT32F437 series, not including AT32F435 series. 26.1 EMAC introduction Copyright Synopsys, Inc. All rights reserved. The Ethernet peripheral enables the AT32F437 to transmit and receive data (10/100Mbps) through Ethernet in compliance with IEEE 802.3-2002 standard.
  • Page 581 AT32F435/437 Series Reference Manual  Supports checking IPv4 header checksum and IPv4, TCP, UDP or ICMP (packaged in IPv4 or IPv6 data formats) checksum  Supports Ethernet frame time stamp as defined in IEEE 1588-2008. 64-bit time stamps are recorded in the transmit or receive status ...
  • Page 582: Figure 26-2 Smi Interface Signals

    AT32F435/437 Series Reference Manual Figure 26-2 SMI interface signals EMAC SMI MDIO Before write operation, PHY address, MII register and EMAC_MACMIIDT register must be configured first, followed by the MII MW and MB bits, and then the SMI interface will transfer the PHY address, PHY register address and data to the PHY.
  • Page 583: Figure 26-3 Mii Signals

    AT32F435/437 Series Reference Manual Figure 26-3 MII signals TX_CLK TX_EN TXD[3:0] RX_CLK RX_ER RX_DV EMAC RXD[3:0] MDIO MII_TX_CLK: Transmit data clock signal. This clock is 2.5MHz at 10Mbps speed; 25MHz at 100Mbps speed. MII_RX_CLK: Receive data clock signal. This clock is 2.5MHz at 10Mbps speed; 25MHz at 100Mbps speed.
  • Page 584: Figure 26-4 Reduced Media-Independent Interface Signals

    AT32F435/437 Series Reference Manual Table 26-2 Transmit interface signal encode MII_TX_EN MII_TXD[3: 0] Description 0000 to 1111 Normal frame interval 0000 to 1111 Normal data transfer Table 26-3 Receive interface signal encode MII_RX_DV MII_RX_ER MII_RXD[3: 0] Description 0000 to 1111 Normal frame interval 0000 Normal frame interval...
  • Page 585: Figure 26-5 Mii Clock Sources (Provided By Clkout Pin)

    AT32F435/437 Series Reference Manual Figure 26-5 MII clock sources (provided by CLKOUT pin) AT32F437 TX_CLK 25MHz RX_CLK HEXT CLKOUT 25MHz Figure 26-6 MII clock sources (provided by an external oscillator) TX_CLK AT32F437 RX_CLK 25MHZ OSC RMII clock sources As shown in Figure 26-7, both the EMAC and PHY require 50MHz clock sources, which can be done with an external crystal oscillator.
  • Page 586: Figure 26-8 Mac Frame Format

    AT32F435/437 Series Reference Manual EMAC pin allocation and multiplexing Table 26-4 Ethernet peripheral pin configuration EMAC signal RMII Pin description EMAC_MDC Multiplexed push-pull output EMAC_MII_TXD2 TXD2 Multiplexed push-pull output EMAC_MII_TX_CLK TX_CLK Floating input (reset state) EMAC_MII_CRS Floating input (reset state) EMAC_MII_RX_CLK RX_CLK REF_CLK...
  • Page 587: Figure 26-9 Tagged Mac Frame Format

    AT32F435/437 Series Reference Manual Figure 26-9 Tagged MAC frame format Preamble 7bytes 1byte 6bytes 6bytes 802.1QTag Type Qtag Prefix 4 bytes Flag control information MAC client length/type 2bytes MAC client data 46-1500bytes 4bytes EMAC frame filtering EMAC supports source and destination address filtering. Address filtering Based on frame filtering register chosen by the application, address filtering checks the source and destination addresses over all received frames using the MAC address and multicast HASH table.
  • Page 588 AT32F435/437 Series Reference Manual EMAC. In this case, the frames that pass through both SA and DA filtering can be forwarded to the application; otherwise, they will be dropped. Inverse filtering operation The DAIF and SAIF bits in the frame filter register are used to invert the filtering output result for both destination and source address filtering.
  • Page 589: Table 26-5 Destination Address Filtering

    AT32F435/437 Series Reference Manual Table 26-5 Destination address filtering Frame DAIF DA filter operation type Pass Broadcast Pass Fail Pass all frames Pass on perfect/group filter match Fail on perfect/group filter match Pass on HASH filter match Unicast Fail on HASH filter match Pass on HASH or perfect/group filter match Fail on HASH or perfect/group filter...
  • Page 590 AT32F435/437 Series Reference Manual CSMA/CD algorithm in half-duplex mode. After the EOF is transferred to the MAC core, the core completes normal transmission and then gives the status of the transmission back to the DMA. There are two modes of operation for popping data from TXFIFO to the MAC core: In threshold mode: If the number of bytes in the FIFO crosses the configured threshold (or when ...
  • Page 591 AT32F435/437 Series Reference Manual value in the EMAC_MACFCTRL register. To extend the pause time or cancel the remaining pause time, the EMAC must send another pause frame (PT=0 will cancel the remaining pause time). If flow control is enabled (EFT=1 in the EMAC_MACFCTRL register), when the RXFIFO is full, the EMAC generates and transmits a Pause time.
  • Page 592 AT32F435/437 Series Reference Manual ― The frame ends before the IPv6 header (40 bytes) or extension header (including header length field) has been completely received. Even if the checksum module detects such an IP header error, it inserts an IPv4 header checksum if the Ethernet type field indicates an IPv4 payload.
  • Page 593 AT32F435/437 Series Reference Manual CRC/pad stripping option, the EMAC sends the data of the frame to RXFIFO up to the count specified in the length/type field, then starts dropping bytes (including the FCS filed). If the length/type field is greater than 0x600, the MAC sends all received Ethernet frame data to RXFIFO, regardless of the value on the programmed auto-CRC strip option.
  • Page 594: Figure 26-10 Descriptor For Ring And Chain Structure

    AT32F435/437 Series Reference Manual 5. Excessive deferral 6. Frame overflow If a frame reception is aborted due to any of the following errors, this frame will not be counted: 1. CRC error 2. Runt frame (shorter than 64 bytes) 3. Alignment error 4.
  • Page 595 AT32F435/437 Series Reference Manual DMA AHB host burst access The DMA executes a fixed-length burst access on the AHB master interface if the FB bit is set in the EMAC_DMABM register. The maximum burst length is defined by the PBL filed (bit [13: 8] in the EMAC_DMABM register).
  • Page 596 AT32F435/437 Series Reference Manual DMA initialization 1. Configure AT32F437xx bus access parameters in the EMAC_DMABM register. 2. Mask unnecessary interrupt sources in the EMAC_DMAIE register. 3. The application generates the transmit and receive descriptor lists. Then it writes the start addresses of the descriptor lists to both the EMAC_DMARDLADDR and EMAC_DMATDLADDR registers.
  • Page 597: Figure 26-11 Transmit Descriptors

    AT32F435/437 Series Reference Manual is captured. The DMA then clears the OWN bit and closes the descriptor. If the time stamping was not enabled for the frame, the DMA will not alter the contents of TDES2 and TDES3. If enabled, the transmit interrupt bit is set. The DMA fetches the next descriptor when the status information is normal, and jumps to Step 3.
  • Page 598 AT32F435/437 Series Reference Manual when all the data in the buffer are read completely. The own bit of the frame’s first descriptor can be set only after subsequent descriptors for the same frame have been set. Interrupt on completion Bit 30 When set, this bit sets the transmit interrupt bit (EMAC_DMASTS bit [0]) after the present frame has been transmitted.
  • Page 599 AT32F435/437 Series Reference Manual TDES0[12]: IP data error Jabber timeout When set, this bit indicates that the MAC transmitter has experienced a jabber Bit 14 timeout. This bit is set only when the JAD bit is not set in the EMAC_MACCTRL register.
  • Page 600 AT32F435/437 Series Reference Manual TDES2: Transmit descriptor word2 TDES2 contains the address pointer to the first buffer of the descriptor or it contains the lower 32-bit time stamp data. Name Type Description Transmit buffer 1 address pointer / Transmit frame time stamp low This field has two functions: 1: The application indicates to the DMA the location of the Ethernet data in system TBAP1/T...
  • Page 601 AT32F435/437 Series Reference Manual The receive controller checks the latest receive descriptors, if the DMA owns the descriptor, the receive controller will return to Step 4. If the CPU owns the descriptor, the RXDMA will enter suspend state and set the receive buffer unavailable bit, and the controller will flush the received frames if the receive frame flushing feature is enabled.
  • Page 602: Figure 26-12 Rxdma Descriptor Structure

    AT32F435/437 Series Reference Manual Figure 26-12 RXDMA descriptor structure RDES 0 Status [30:0] Rers. Control Contr RDES 1 Buffer 2 byte count [28:16] Rers. Buffer 1 byte count [12:0] [30:29] [15:14] RDES 2 Buffer 1 address [31:0] RDES 3 Buffer 2 address [31:0] or next descriptor address[31:0] RDES0: Receive descriptor word0 RDES0 contains the receive frame state, the frame length and the descriptor ownership information.
  • Page 603: Table 26-7 Receive Descriptor 0

    AT32F435/437 Series Reference Manual contains the beginning of the frame. Last descriptor Bit 8 When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the frame. IPv header checksum error When set, this bit indicates an error in the IPv4 or IPv6 header. This error can be Bit 7 IPHCE due to mismatched Ethernet type filed and IP version field, IPv4 header checksum...
  • Page 604 AT32F435/437 Series Reference Manual RDES1: Receive descriptor 1 Name Type Description Disable interrupt on completion When set, this bit prevents setting the Ethernet DMA status register’s RECV bit Bit 31 (EMAC_DMASTS) for the received frame pointed to by this descriptor. As a result, this disables the interrupt triggered by the RECV bit.
  • Page 605: Figure 26-13 Wakeup Frame Filter Register

    AT32F435/437 Series Reference Manual 26.2.4 Enter and wake up EMAC power-down mode The EMAC enters power-off mode when the PD bit is enabled in the EMAC_MACPMTCTRLSTS register. In this mode, all received frames are dropped by the EMAC and they are not forwarded to the application. PMT supports the reception of remote wakeup frames and AMD Magic Packet frames and uses them to wake up the EMAC from power-off mode.
  • Page 606 AT32F435/437 Series Reference Manual same time, the RRWF bit (bit 6) is set in the EMAC_MACPMTCTRLSTS register, indicating that a remote wakeup frame is received. If a remote wakeup interrupt is enabled, an interrupt will be generated when the PMT receives the remote wakeup frame. Magic Packet detection Magic Packet detection is enabled by setting the EMP bit in the EMAC_MACPMTCTRLSTS register.
  • Page 607 AT32F435/437 Series Reference Manual Reference clock source According to IEEE158 standard, the system requires a reference time in a 64-bit format as the current time record, with the upper 32 bits time information in seconds, and the lower 32 bits time information in nanoseconds.
  • Page 608: Figure 26-14 System Time Update Using The Fine Correction Method

    AT32F435/437 Series Reference Manual Figure 26-14 System time update using the fine correction method Addend register Accumulator register Constant Incr sub sec value Sub second register Incr sec reg Second register The subsecond register update frequency requires 50 MHz to achieve 20 ns accuracy for the system clock update circuit.
  • Page 609: Figure 26-15 Ptp Trigger Output To Tmr2 Itr1 Connection

    AT32F435/437 Series Reference Manual The frequency compensation value for the addend register, FreqCompensationValue FreqCompensationValue = FreqScaleFactor ×FreqCompensationValue This algorithm comes with a self-correction feature. In theory, the frequency can be locked at a synchronized cycle. However, it may makes several cycles to synchronize the slave device. System time initialization procedure Mask the time stamp trigger interrupt by setting the bit 9 in the EMAC_MAIMR register.
  • Page 610: Figure 26-16 Pps Output

    AT32F435/437 Series Reference Manual PTP second pulse output signal Refer to the EMAC_PTPPPSCR register descriptor for more information about PTP pulse second output. The following contents are based on the fact when the emac_pps_sel bit (bit 9) is cleared in the CRM_MISC2 register.
  • Page 611: Figure 26-17 Ethernet Interrupts

    AT32F435/437 Series Reference Manual Figure 26-17 Ethernet interrupts FBEI FBEE MMCI PMTI TSTI RWTE RBUE 26.3 EMAC registers Table 26-8 shows the Ethernet register map and its reset values. The peripheral registers can be accessed by bytes (8-bit), half words (16-bit) or words (32-bit). Table 26-8 Ethernet register map and its reset values Register name Offset...
  • Page 612 AT32F435/437 Series Reference Manual EMAC_MAIMR 0x3C 0x0000 0000 EMAC_MACA0H 0x40 0x0010 FFFF EMAC_MACA0L 0x44 0xFFFF FFFF EMAC_MACA1H 0x48 0x0000 FFFF EMAC_MACA1L 0x4C 0xFFFF FFFF EMAC_MACA2H 0x50 0x0000 FFFF EMAC_MACA2L 0x54 0xFFFF FFFF EMAC_MACA3H 0x58 0x0000 FFFF EMAC_MACA3L 0x5C 0xFFFF FFFF EMAC_MMCCTRL 0x100 0x0000 0000...
  • Page 613 AT32F435/437 Series Reference Manual EMAC_DMAMFBOCNT 0x1020 0x0000 0000 EMAC_DMACTD 0x1048 0x0000 0000 EMAC_DMACRD 0x104C 0x0000 0000 EMAC_DMACTBADDR 0x1050 0x0000 0000 EMAC_DMACRBADDR 0x1054 0x0000 0000 26.3.1 Ethernet MAC configuration register (EMAC_MACCTRL) The Ethernet MAC configuration register defines the receive and transmit operation modes. A delay greater than 4μs is required for two consecutive write accesses to this register.
  • Page 614 AT32F435/437 Series Reference Manual mode. The MII receive clock input (clk_rx_i) is required for the loopback mode to work normally, for the transmit clock is not looped-back internally. Duplex Mode Bit 11 When this bit is set, the MAC operates in full-duplex mode, in which it can transmit and receive simultaneously.
  • Page 615 AT32F435/437 Series Reference Manual the deferral threshold is 155680 bit times. Deferral begins when the transmitter is ready to transmit, but is prevented when an active carrier sense signals is detected on the MII. Deferral time is not cumulative. For instance, if the transmitter is deferred for 10000 bit times because that the CRS signals is active first, but then becomes inactive, then transmits, collides, backs off because of collision, and then...
  • Page 616 AT32F435/437 Series Reference Manual When this bit is set, the address check block operates in inverse filtering mode. The frame whose source address matches the source address register is marked as failing the source address filter. When this bit is cleared, the frame whose source address does not match the source address register is marked as failing the source address filter.
  • Page 617 AT32F435/437 Series Reference Manual When the PR is set, the source address or destination address error bits in the receive status word are always 0. 26.3.3 Ethernet MAC Hash table high register (EMAC_MACHTH) The 64-bit Hash table is used for group address filtering. For Hash filtering, the contents of the destination address of the incoming frame pass through the CRC logic, and the upper 6 bits in the CRC register are used to index the Hash table.
  • Page 618 AT32F435/437 Series Reference Manual MII Write When this bit is set, it indicates that the EMAC_MACMIIDT Bit 1 register is used for a write operation to the PHY. When this bit is not set, it is a read operation, and the data is loaded to the EMAC_MACMIIDT register.
  • Page 619 AT32F435/437 Series Reference Manual The threshold values should always be less than the Pause time defined in the [31: 16] bit. For example, if PT = 100H (256 slot times), and PLT = 01, then a second Pause frame is automatically transmitted if initiated at 228 (256-28) slot times after the first Pause frame is transmitted.
  • Page 620: Figure 26-18 Ethernet Mac Remote Wakeup Frame Filter Register (Emac_Macrwff)

    AT32F435/437 Series Reference Manual 26.3.8 Ethernet MAC VLAN tag register (EMAC_MACVLT) The Ethernet MAC VLAN tag register contains the IEEE 802.1Q VLAN tag to identify the VLAN frames. The MAC compares the 13 and 14 bytes of the received frame (length/type) with 16’h8100, and the following 2 bytes are compared with the VLAN tag.
  • Page 621 AT32F435/437 Series Reference Manual 26.3.10 Ethernet MAC PMT control and status register (EMAC_MACPMTCTRLSTS) The Ethernet MAC PMT control and status register sets the request wakeup events and detects the wakeup events. Register Reset value Type Description Remote Wakeup Frame Filter Register Pointer Reset When this bit is set, it resets the remote frame filter register Bit 31 RWFFPR...
  • Page 622 AT32F435/437 Series Reference Manual EMAC_MMCRI register. This bit is cleared when all bits in the receive interrupt register are cleared. MMC Interrupt Status Bit 4 This bit is set whenever any bit of the [7: 5] bit is set high. This bit is cleared only when these bits are set low.
  • Page 623 AT32F435/437 Series Reference Manual 26.3.14 Ethernet MAC address 0 low register (EMAC_MACA0L) The Ethernet MAC address 0 low register contains the lower 32 bits of the 6-byte first MAC address. Register Reset value Type Description MAC Address0 [31: 0] This field contains the lower 16 bits of the first 6-byte MCU Bit 31: 0 MA0L 0xFFFF FFFF rw...
  • Page 624 AT32F435/437 Series Reference Manual 26.3.17 Ethernet MAC address 2 high register (EMAC_MACA2H) The Ethernet MAC address 2 high register holds the upper 16 bits of the 6-byte second MAC address. If the MAC address register is configured to be double-synchronized with the MII domain, the synchronization can be enabled only by writing the bit [31: 24] (in little endian mode) or the bit [7: 0] (in big-endian mode) in the Ethernet MAC address 2 low register (EMAC_MACA2L).
  • Page 625 AT32F435/437 Series Reference Manual When this bit is cleared, the address filter will ignore the address for filtering. Source Address When this bit is set, the MAC address 3 [47: 0] is used for comparison with the source address field of the received Bit 30 frame.
  • Page 626 AT32F435/437 Series Reference Manual This field indicates the maximum number of beats to be transferred in one Rx DMA operation. This is the maximum value that is used for a single write or read operation. The Rx DMA always attempts to perform burst transfer as specified in RPBL each time it starts a burst transfer on the host bus.
  • Page 627 AT32F435/437 Series Reference Manual Otherwise, Rx has priority over Tx. Software Reset When this bit is set, the MAC DMA controller resets all Bit 0 internal registers and MAC logic. This bit is automatically cleared after all reset operations have been completed. 26.3.22 Ethernet DMA transmit poll demand register (EMAC_DMATPD) The EMAC_DMATPD register enables the Tx DMA to check whether or not the current descriptor is...
  • Page 628 AT32F435/437 Series Reference Manual 26.3.25 Ethernet DMA transmit descriptor list address register (EMAC_DMATDLADDR) The EMAC_DMATDLADDR register points to the start of the transmit descriptor list. The descriptor list is located in the host’s physical memory and must be word-aligned. The DMA enables bus-width aligned address by making the corresponding LS bit low.
  • Page 629 AT32F435/437 Series Reference Manual This field indicates the Tx DMA FSM state. This field does not generate an interrupt. 3’b000: Stopped; Rest or Stop transmit command issued 3’b001: Running; Fetching transmit descriptor 3’b010: Running; Waiting for status 3’b011: Running; Reading data from host memory buffer and queuing it to Tx FIFO 3’b100: Time stamp write status 3’b101: Reserved for future use...
  • Page 630 AT32F435/437 Series Reference Manual This bit indicates that the frame to be transmitted was fully sent to the MTL Tx FIFO. Receive Watchdog Timeout When this bit is set, it indicates that the receive watchdog Bit 9 rw1c timer timeout occurs while receiving the current frame, and the current frame is cut off after the watchdog timeout happens.
  • Page 631 AT32F435/437 Series Reference Manual Register Reset value Type Description Bit 31: 27 Reserved 0x00 resd Kept at its default value. Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does not drop the frames that only have errors detected by the receive checksum offload engine.
  • Page 632 AT32F435/437 Series Reference Manual unavailable) is set in the statue register. Transmission command is valid only when the transmission is stopped. If the transmit command were issued before setting the transmit descriptor list address register, the DMA will show unpredictable behavior. When this bit is cleared, transmit process enters stop state after the completion of a frame transmission.
  • Page 633 AT32F435/437 Series Reference Manual the reception command were issued before setting the receive descriptor list address register, the DMA will show unpredictable behavior. When this bit is cleared, Rx DMA operation is stopped after the completion of a frame reception. The next descriptor position in the receive list is saved, and becomes the current position when reception process is restarted.
  • Page 634 AT32F435/437 Series Reference Manual Receive Buffer Unavailable Enable When this bit is set with the abnormal interrupt summary Bit 7 RBUE enable bit, the receive buffer unavailable interrupt is enabled. When this bit is cleared, the receive buffer unavailable interrupt is disabled. Receive Interrupt Enable When this bit is set with the normal interrupt summary Bit 6...
  • Page 635 AT32F435/437 Series Reference Manual In this case, the missed frame counter is reset to all zero, and this bit indicates that a toggle has occurred. Missed Frame Counter This field indicates the number of frames missed by the Bit 15: 0 0x0000 controller due to the host receive buffer being unavailable.
  • Page 636 AT32F435/437 Series Reference Manual Stop Counter Rollover Bit 1 When this bit is set, the counter does not roll over to 0 after it reaches the maximum value. Reset Counter Bit 0 When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle.
  • Page 637 AT32F435/437 Series Reference Manual 26.3.37 Ethernet MMC receive interrupt register (EMAC_MMCRIM) The EMAC_MMCRIM contains the masks for interrupts generate when the receive statistic counters reach half their maximum values or their maximum values. This register is a 32-bit register. Register Reset value Type Description...
  • Page 638 AT32F435/437 Series Reference Manual 26.3.40 Ethernet MMC transmitted good frame more than a single collision counter register (EMAC_MMCTFMSCC) This register maintains the number of successfully transmitted frames after more than a single collision in half-duplex mode. Register Reset value Type Description Transmitted Good Frame More Than a Single Collision Counter...
  • Page 639 AT32F435/437 Series Reference Manual messages relevant to slave. Enable Timestamp Snapshot For Event Messages When this bit is set, it enables time stamp snapshots for event messages only (SYNC, Delay_Req, Pdelay_Req, or Bit 14 ETSFEM Pdelay_Resp). When this bit is cleared, time stamp snapshots are applicable to all the messages except Announce, Management and Signaling.
  • Page 640 AT32F435/437 Series Reference Manual This bit must be read as 0 before being updated. This bit is cleared after the initialization. Time stamp high word register (if enabled) is not updated. Timestamp Fine or Coarse Update When this bit is set, it indicates that the system time is Bit 1 TFCU updated using a fine update method.
  • Page 641 AT32F435/437 Series Reference Manual 26.3.48 Ethernet PTP time stamp low register (EMAC_PTPTSL) This register contains the lower 32 time bits. It is a read-only register containing the subsecond system time value. Register Reset value Type Description Add or Subtract Time When this bit is set, the time value is subtracted from the Bit 31 value of the update register.
  • Page 642 AT32F435/437 Series Reference Manual 26.3.52 Ethernet PTP target time high register (EMAC_PTPTTH) Target time second register and target time subsecond register are used to schedule an interrupt event when the system time exceeds the value programmed in these registers. Register Reset value Type Description...
  • Page 643 AT32F435/437 Series Reference Manual rollover, 1hz (digital rollover is not recommended) 0010: For binary rollover, 4hz, duty cycle 50%; For digital rollover, 2hz (digital rollover is not recommended) 0011: For binary rollover, 8hz, duty cycle 50%; For digital rollover, 4hz (digital rollover is not recommended) 1111: For binary rollover, 32.768khz, duty cycle 50%;...
  • Page 644: Figure 27-1 Dvp Block Diagram

    AT32F435/437 Series Reference Manual 27 Digital Video parallel interface (DVP) 27.1 Introduction The digital video parallel interface (DVP) is able to capture parallel data output on the CMOS video camera. It is possible to perform frame/line synchronization in either hardware or embedded synchronization code.
  • Page 645: Figure 27-2 Cmos Video Camera Output In Frame Start Type

    AT32F435/437 Series Reference Manual data (DVP_D) output from the CMOS video camera. The DVP_PCLK is provided by the CMOS video camera. Data can be captured on either the rising or the falling edge of the DVP_PCLK by setting the CKP bit in the DVP_CTR register. The captured data can be divided into two parts: valid pixel data and blanking period data.
  • Page 646: Figure 27-4 Fs/Fe/Ls/Le Frame Composition

    AT32F435/437 Series Reference Manual Table 27-1 lists the physical signals used by DVP in hardware synchronization mode. The use of the pixel parallel data (DVP_D) depends on the configurations of parallel data bits and alignment. Refer to Section 27.3.3 for details. Those unused signals may not be configured with the multiplexed function of the corresponding pins.
  • Page 647: Figure 27-5 Sav/Eav Frame Composition

    AT32F435/437 Series Reference Manual SAV/EAV type In this mode, the CMOS camera also uses four embedded synchronization codes to deliver synchronization information. The line within a frame uses the active SAV code to indicate the end of blanking area and the start of a valid pixel. At the end of the last valid pixel data of each line, the active SAV code is embedded signaling that the data following this are vertical blanking.
  • Page 648: Figure 27-6 Block Diagram In Single Frame Capture Mode

    AT32F435/437 Series Reference Manual Table 27-3 DVP register configuration and DVP_D pin use CMOS video camera parallel pin count CMOS video camera parallel data bits CMOS video camera data alignment [13] Bit 13 [12] Bit 12 [11] Bit 7 Bit 9 Bit 11 Bit 11 [10]...
  • Page 649: Figure 27-7 Block Diagram In Continuous Capture Mode

    AT32F435/437 Series Reference Manual Figure 27-7 Block diagram in continuous capture mode DVP_VSYNC Captured Captured DVP_D blanking blanking blanking blanking frame frame set 1 to CAP set 0 to CAP 27.4 DMA access interface and data output packing 27.4.1 DMA access interface The captured data can be transferred to memory unit using DMA interface without needing to occupy CPU resources.
  • Page 650: Figure 27-8 Pdl Configuration And Data Output Packing

    AT32F435/437 Series Reference Manual packs two captured data into a word data. The word data is made up of two half words. The first captured data is placed in the 12 least significant bits of the least significant half word, and the last captured data is placed in the 12 least significant bits of the most significant half word, and the remaining are cleared to zero.
  • Page 651: Figure 27-9 Block Diagram Of Frame Rate Control Feature

    AT32F435/437 Series Reference Manual output data FIFO becomes full for the reason that the DMA is unable to capture data in time and transfer them to memory unit, in this case, the captured data will be discarded, and an output data overrun error interrupt is generated.
  • Page 652: Figure 27-10 Crop Window Block Diagram

    AT32F435/437 Series Reference Manual Figure 27-10 Crop window block diagram CHNUM+1 (CHSTR,CVSTR) CVNUM+1 Image Image Note: As the DVP packs the captured data into a 32-bit word for DMA access, the CHNUM bit has the following limits while using crop feature: for 8-bit data (PDL=0), CHNUM+1 must be a multiple of 4; for 10-bit, 12-bit or 14-bit data (PDLǂ0), CHNUM+1 must be a multiple of 2.
  • Page 653: Figure 27-12 Lcdc/Lcds And Frame Structure

    AT32F435/437 Series Reference Manual Figure 27-12 LCDC/LCDS and frame structure LCDC = 0 LCDC = 1, PCDS = 0 LCDC = 1, PCDS = 1 Captured line Dropped line 2023.08.02 Page 653 Rev 2.05...
  • Page 654: Figure 27-13 Pcdc/Pcds And Line Structure

    AT32F435/437 Series Reference Manual Figure 27-13 PCDC/PCDS and line structure ..N -4 N -3 N -2 N -1 PCDC = 0 ..N -4 N -3 N -2 N -1 PCDC = 1, PCDS = 0 .
  • Page 655: Figure 27-14 Rgb565-Format Data Capture And Packing

    AT32F435/437 Series Reference Manual 27.6.4 Grayscale image binarization conversion The grayscale image binarization conversion unit is used to convert the luminance into one-bit format. To enable this feature, set EFDM=1, and program the EFDF bit based on the output format of CMOS video camera.
  • Page 656: Figure 27-15 Rgb555-Format Data Capture And Packing

    AT32F435/437 Series Reference Manual Figure 27-15 RGB555-format data capture and packing 2 1 0 G[4:3 B[4:0] G[2:0] R[4:0] 1514 10 9 3130 26 25 2120 RGB555 (RGB) 2 1 0 G[4:3 R[4:0] G[2:0] B[4:0] 3130 26 25 2120 1514 10 9 RGB555 (BGR) YUV422 format In this format, one half-word data pixel (16 bit) is output every two pixel clocks.
  • Page 657: Figure 27-17 Y8 (Y-Only)-Format Data Capture And Packing

    AT32F435/437 Series Reference Manual Y8 (Y-only) format In this format, one-byte pixel (8-bit) Y (luminance) is output every pixel clock, which is encoded in 8-bit format. There is no chroma output. Figure 27-17 gives an example of DVP data capture and packing in Y8 (Y-only) format.
  • Page 658: Figure 27-18 Yuv422 Format To Y8 (Y-Only) Format

    AT32F435/437 Series Reference Manual Figure 27-18 YUV422 format to Y8 (Y-only) format PCDC = 1, PCDS = 0 For YUV422 (YUYV) to Y8 PCDC = 1, PCDS = 1 For YUV422 (UYVY) to Y8 27.8 Registers Table 27-5 shows the DVP register map and its reset values. The peripheral registers can be accessed by words (32-bit).
  • Page 659 AT32F435/437 Series Reference Manual lines Basic pixel capture/drop selection 0: Capture the first group of data (one or two pixel data) and drop the next group Bit 18 PCDS 1: Drop the first group of data (one or two pixel data) and capture the next group This register is valid when the PCDC=1/2/3 is asserted.
  • Page 660 AT32F435/437 Series Reference Manual This feature is valid only when SM=0 is asserted. Cropping window function enable Bit 2 0: Cropping window function disabled 1: Cropping window function enabled Capture function mode Bit 1 0: Continuous capture mode 1: Single frame capture mode Capture function enable 0: Capture function disabled 1: Capture function enabled...
  • Page 661 AT32F435/437 Series Reference Manual It is cleared by writing 1 to the CFDIC bit in the DVP_ICLR register. 27.8.4 DVP interrupt enable register (DVP_IENA) Register Reset value Type Description Bit 30: 5 Reserved 0x0000000 resd Kept at its default value. Horizontal synchronization interrupt enable Bit 4 HSIE...
  • Page 662 AT32F435/437 Series Reference Manual Writing 1 to this bit clears the ESEES bit in the DVP_ESTS register, and clears the ESEIS bit in the DVP_ISTS register. Output data FIFO overrun interrupt clear Writing 1 to this bit clears the OVRES bit in the DVP_ESTS Bit 1 OVRIC register, and clears the OVRIS bit in the DVP_ISTS...
  • Page 663 AT32F435/437 Series Reference Manual PDL=1, set bit N =0 in the LNSU, the bit N+2 is masked PDL=2, set bit N =0 in the LNSU, the bit N+4 is masked PDL=2, set bit N =0 in the LNSU, the bit N+6 is masked Frame start synchronization code unmask This field specifies the mask to be applied to the code of the line end synchronization.
  • Page 664 AT32F435/437 Series Reference Manual 1: DMA burst transaction enabled. The EDMA’s peripheral transfer must be programmed as INCR4 (PBURST=1). This configuration is enabled only when the EDMA is used for data transfer. If the DMA is used, this configuration must be disabled. Bit 11 Reserved resd...
  • Page 665 AT32F435/437 Series Reference Manual 27.8.13 DVP enhanced horizontal scaling factor register (DVP_HSCF) Register Reset value Type Description Bit 30: 29 Reserved resd Kept at its default value. Horizontal scaling resize target factor Bit 28: 16 HSRTF 0x00 When EISRE=1, this register must not be 0, or greater than HSRSF value.
  • Page 666: Figure 28-1 Function Block Diagram

    AT32F435/437 Series Reference Manual 28 Qud-SPI interface (QSPI) 28.1 Introduction The QSPI interface consists of a command-based slave port, an XIP port (direct address mapping access) and QSPI interface controller used for SPI Flash command execution. The command-based slave port is used to access registers and data ports, and the XIP slave port reads data from direct address mapping.
  • Page 667: Figure 28-2 Dma Handshake Mode

    AT32F435/437 Series Reference Manual The DMA mode can also be used to access data ports. The DMA controller register must be programmed as DMA handshake mode. In this mode, the host controller sends a DMA request when the receive/transmit FIFO threshold is reached. The threshold values are in terms of words. The DMA request is still sent when the last data transfer is less than the threshold.
  • Page 668: Figure 28-3 Write Enable

    AT32F435/437 Series Reference Manual Figure 28-3 Write enable Data capture Mode3 (SCK idle high) Mode3 Mode0 Mode0 (SCK idle low) Instruction (06h) High Impedance To execute page programming command, set instruction code to 02h, address register, address size, write enable and set instruction length to 1. Figure 28-4 Page programming Mode3 Mode0...
  • Page 669: Figure 28-7 Quick Read Dual Output Command

    AT32F435/437 Series Reference Manual To execute a quick read dual output command, set instruction code/length to 1, address/address size to 3 bytes, set the second dummy cycle to 8, and enable dual mode. Refer to Figure 28-7 for details. Figure 28-7 Quick read dual output command Mode3 Mode0 Instruction (3Bh)
  • Page 670: Figure 28-10 Quick Read Quad I/O Command

    AT32F435/437 Series Reference Manual Mode3 Mode0 Instruction (6Bh) 24-Bit Address Dummy Clocks IO Switches from Input to Output Byte 4 Byte 1 Byte 2 Byte 3 Quad I/O (1-4-4) mode To execute a quick read quad I/I command, set instruction code/length, address/address size, the second dummy period, enable performance enhancement mode and enable quad I/O mode.
  • Page 671 AT32F435/437 Series Reference Manual Mode3 Mode0 INS7-0 A23-16 A15-8 A7-0 Dummy IO Switches from Input to Output Byte 1 Byte 2 Byte 3 If quad DPI (4-4-4) mode is to be used, it is necessary to set code/length, address/address length, the second dummy cycle and operation command of quad DPI mode.
  • Page 672 AT32F435/437 Series Reference Manual Mode3 Mode0 Byte N INS7-0 A23-16 A15-8 A7-0 Byte 1 Byte 2 Byte 3 Dummy XIP read/write T mode If XIP read/write T mode is to be used, it is necessary to set code/length, address/address length, the second dummy cycle, select serial/two-line/two-line IO/four-line/four-line IO or DPI/QPI mode, and to set read/write T mode and T mode upper limit counter.
  • Page 673: Table 28-1 Spi Register Map And Reset Values

    AT32F435/437 Series Reference Manual 28.4 QSPI registers These registers must be accessed by bytes (8-bit), half-words (16-bit) or words (32-bit). Table 28-1 SPI register map and reset values Register Offset Reset value CMD_W0 0x0000 0000 CMD_W1 0x0100 0003 CMD_W2 0x0000 0000 CMD_W3 0x0000 0000 CTRL...
  • Page 674 AT32F435/437 Series Reference Manual Instruction code length Instruction code is required for SPI Flash command execution. The instruction code length varies from SPI Flash supplier to SPI Flash supplier. Thus this register can be used to program the desired instruction code length. Typically, the instruction code is one-byte length.
  • Page 675 AT32F435/437 Series Reference Manual Bit 15: 10 Reserved resd Kept at its default value. SPI Operation mode 000: Serial mode (1-1-1) 001: Dual mode (1-1-2) 010: Quad mode (1-1-4) Bit 7: 5 OPMODE 011: Dual I/O mode (1-2-2) 100: Quad I/O mode (1-4-4) 101: DPI mode (2-2-2) 110: QPI mode (4-4-4) Others: Reserved...
  • Page 676 AT32F435/437 Series Reference Manual Busy bit of SPI status The host polls this busy bit and remains in hardware read Bit 18: 16 BUSY state. 000~111: bit 0~bit7 Bit 15: 9 Reserved 0x00 resd Kept at its default value. Refresh all commands/FIFOs and reset state machine When an Abort even occurs, this bit must be written (This Bit 8 ABORT...
  • Page 677 AT32F435/437 Series Reference Manual TxFIFO ready status When the TxFIFO is ready, it indicates that the TxFIFO will Bit 0 TXFIFORDY get empty so that data can be transmitted into it until it becomes full. 28.4.8 Control register 2 (CTRL2) No-wait states, accessible by bytes, half-words and words.
  • Page 678 AT32F435/437 Series Reference Manual 28.4.11 Flash size register (FSIZE) No-wait states, accessible by bytes, half-words and words. Register Reset value Type Description SPI Flash Size In direct address map mode, system address is always Bit 31: 0 SPIFSIZE 0xF000 0000 greater than that of SPI Flash.
  • Page 679 AT32F435/437 Series Reference Manual XIP write operation mode 000: Serial mode (1-1-1) 001: Dual mode (1-1-2) 010: Quad mode (1-1-4) Bit 10: 8 XIPW_OPMODE 011: Dual IO mode (1-2-2) 100: Quad IO mode (1-4-4) 101: DPI mode (2-2-2) 110: QPI mode (4-4-4) 111: Reserved XIP Write second dummy cycle The second dummy state is located between the address...
  • Page 680 AT32F435/437 Series Reference Manual This indicates the time counter that is used to judge time interval in mode T. Bit 14: 8 XIPR_TCNT 0x0F Value is in terms of sck_out period. This counter is valid when mode T is selected. Bit 7: 6 Reserved resd...
  • Page 681: Figure 29-1 Block Diagram

    AT32F435/437 Series Reference Manual 29 EDMA controller (EDMA) 29.1 Introduction Enhanced direct memory access (EDMA) controller is designed for 32-bit MCU applications with the goal of enhancing system performance and reducing the generation of interrupts. This controller offers 8 DMA channels to guarantee data transfers between peripheral-to-memory, memory-to-peripheral, and memory-to-memory.
  • Page 682 AT32F435/437 Series Reference Manual 29.3 Functional overview 29.3.1 Flow configuration 1. Set the peripheral address in the DMA_CxPADD register The initial peripheral address for data transfer remains unchanged during transmission. 2. Set the memory address in the DMA_CxMADDR register The initial memory address for data transfer remains unchanged during transmission. 3.
  • Page 683: Figure 29-2 Channel Select And Synchronizer

    AT32F435/437 Series Reference Manual 6. Enable DMA transfer through the SEN bit in the DMA_SxCTRL register 29.3.2 Channel selection and synchronizer The clocks between a peripheral and DMA may be asynchronous. The user can choose whether the synchronizer of the dma_chx_req is needed. Figure 29-2 shows the block diagram of channel selection and synchronizer.
  • Page 684: Figure 29-3 Re-Arbitrate After Request/Acknowledge

    AT32F435/437 Series Reference Manual Figure 29-3 Re-arbitrate after Request/Acknowledge One single/ burst Antother single/ burst transfer transfer dma_req dma_ack Re-arbitrate Re-arbitrate In non-incrementing mode (PINCM = 0 or MINCM = 0), burst transfers of 4, 8 or 16 beats are translated into 4, 8 or 16 single transfers.
  • Page 685: Figure 29-5 Example Of Unpacking Mechanism

    AT32F435/437 Series Reference Manual Figure 29-5 Example of unpacking mechanism 4-word FIFO AHB Read Sequence AHB Write Sequence HW3 HW2 HW HW0 B7 B6 B1 B0 word2 word0 word3 word1 Figure 29-6 Example of PINCOS Perpheral Address Field PINCOS = 0 PINCOS = 1 0x10 0x10...
  • Page 686: Figure 29-7 Descriptor Format

    AT32F435/437 Series Reference Manual CNT = PBURST×PWIDTH×N = MBURST×MWIDTH×M  MBURST/PBURST (data transfer size) = 1 (single) or 4, 8 or 16 burst  MWIDTH/PWIDTH (data transfer width) = 1 (byte), 2 (half-word) or 4 (word) M, N, CNT are positive integers ...
  • Page 687: Figure 29-9 Example Of A 2D Transfer (Source Side Is Managed By A Peripheral Controller)

    AT32F435/437 Series Reference Manual 29.3.8 2D transfer mechanism The 2-dimensional (2D) transfer mechanism makes it easier to block data like images. The DMA controller offers four types of configurations for 2D transfers.  XCOUNT bit in DMA_Sx2DCNT: Data count to be transmitted before jumping to the next stride ...
  • Page 688: Figure 29-10 Example Of A 2D Transfer (Destination Side Is Managed By A Memory Controller)

    AT32F435/437 Series Reference Manual Figure 29-10 Example of a 2D transfer (destination side is managed by a memory controller) Destination Stride = +10 bytes XCOUNT = 4 beats = +4 words word address YCOUNT = iterate 8 times data no data Limits on 2D transfers ...
  • Page 689: Table 29-2 Dma Interrupts

    AT32F435/437 Series Reference Manual 29.3.10 Interrupts An interrupt can be generated on a DMA half-transfer, transfer complete, transfer error, FIFO error and direct mode error. Each channel has its specific interrupt flag, clear and enable bits, as shown in the table below.
  • Page 690: Figure 29-11 Dmamux Block Diagram

    AT32F435/437 Series Reference Manual Figure 29-11 DMAMUX block diagram DMAMUX ADC1 TMR2 Stream x ADC2 TMR3 ADC3 TMR4 Stream 2 DAC1 TMR5 Stream 1 DMAMUX_SEL DAC2 TMR6 TMR7 I2S2_EXT TMR8 REQID I2S3_EXT TMR20 chx_mux_req I2C1 USART1 all req[127:5] I2C2 USART2 I2C3 USART3 SDIO1...
  • Page 691: Figure 29-12 Dmamux Synchronized Mode

    AT32F435/437 Series Reference Manual I2C3_TX TMR8_OVERFLOW 85 reserved UART7_TX reserved TMR8_TRIG TMR20_CH1 UART8_RX reserved TMR8_HALL TMR20_CH2 UART8_TX USART1_RX TMR2_CH1 TMR20_CH3 reserved USART1_TX TMR2_CH2 TMR20_CH4 reserved USART2_RX TMR2_CH3 TMR20_OVERFLOW 122 reserved USART2_TX TMR2_CH4 reserved reserved USART3_RX TMR2_OVERFLOW 92 reserved reserved USART3_TX TMR3_CH1 TMR20_TRIG reserved...
  • Page 692: Figure 29-13 Dmamux Event Generation

    AT32F435/437 Series Reference Manual DMA request served Selected all_req[n] syncx mux_syncp mux_syncx chx_mux_req mux_req_cnt mux_evtx SYNCEN = 1, EVTGEN = 1, SPOL = 01, REQCNT = 2 Figure 29-13 DMAMUX event generation Selected all_req[n] chx_mux_req SYNCEN EVTGEN mux_req_cnt mux_evtx SYNCEN = 0, EVTGEN = 1, REQCNT = 2 2023.08.02 Page 692 Rev 2.05...
  • Page 693: Table 29-5 Bpr Register Map And Reset Values

    AT32F435/437 Series Reference Manual 29.5 EDMA registers Table 29-5 shows DMA register map and reset values. These peripheral registers must be accessed by byte (8 bits), half-word (16 bits) or word (32 bits) Table 29-5 BPR register map and reset values Register Offset Reset value...
  • Page 694 AT32F435/437 Series Reference Manual EDMA_S6PADDR 0x90 0x0000 0000 EDMA_S6M0ADDR 0x94 0x0000 0000 EDMA_S6M1ADDR 0x98 0x0000 0000 EDMA_S6FCTRL 0x9c 0x0000 0000 EDMA_S7CTRL 0xa0 0x0000 0000 EDMA_S7DTCNT 0xa4 0x0000 0000 EDMA_S7PADDR 0xa8 0x0000 0000 EDMA_S7M0ADDR 0xac 0x0000 0000 EDMA_S7M1ADDR 0xb0 0x0000 0000 EDMA_S7FCTRL 0xb4 0x0000 0000...
  • Page 695 AT32F435/437 Series Reference Manual EDMA_S8STRIDE 0x134 0x0000 0000 EDMA_SYNCEN 0x138 0x0000 0000 EDMA_MUXSEL 0x13c 0x0000 0000 EDMA_MUXS1CTRL 0x140 0x0000 0000 EDMA_MUXS2TRL 0x144 0x0000 0000 EDMA_MUXS3CTRL 0x148 0x0000 0000 EDMA_MUXS4CTRL 0x14c 0x0000 0000 EDMA_MUXS5CTRL 0x150 0x0000 0000 EDMA_MUXS6CTRL 0x154 0x0000 0000 EDMA_MUXS7CTRL 0x158 0x0000 0000...
  • Page 696 AT32F435/437 Series Reference Manual FDTF2 Stream2 full data transfer complete interrupt flag Bit 11 HDTF2 Stream2 half transfer complete interrupt flag Bit 10 DTERRF2 Stream2 transfer error interrupt flag Bit 9 DMERRF2 Stream2 direct mode error interrupt flag Bit 8 Reserved Kept at its default value.
  • Page 697 AT32F435/437 Series Reference Manual HDTF6 Stream6 half data transfer complete interrupt flag Bit 10 DTERRF6 Stream6 transfer error interrupt flag Bit 9 DMERRF6 Stream6 direct mode error interrupt flag Bit 8 Reserved Kept at its default value. Bit 7 FERRF6 Stream6 fifo error interrupt flag Bit 6 FDTF5...
  • Page 698 AT32F435/437 Series Reference Manual FERRFC2 Stream2 clear fifo error interrupt flag Bit 7 Reserved resd Kept at its default value. Bit 6 FDTFC1 Stream1 clear transfer complete interrupt flag Bit 5 HDTFC1 Stream1 clear half transfer complete interrupt flag Bit 4 DTERRFC1 Stream1 clear error interrupt flag Bit 3...
  • Page 699 AT32F435/437 Series Reference Manual HDTFC5 Stream5 clear half transfer complete interrupt flag Bit 4 DTERRFC5 Stream5 clear error interrupt flag Bit 3 DMERRFC5 Steam5 clear direct mode error interrupt flag Bit 2 Reserved resd Kept at its default value. Bit 1 FERRFC5 Stream5 clear fifo error interrupt flag Bit 0...
  • Page 700 AT32F435/437 Series Reference Manual Peripheral increase offset 0: Peripheral increase offset disabled 1: Peripheral increase offset enabled If PINCOS bit is enabled, the offset size of the peripheral PINCOS address calculation is fixed to 32-bit alignment. This bit Bit 15 has no meaning if PINCM=0.
  • Page 701 AT32F435/437 Series Reference Manual Data transfer error interrupt enable DTERRIEN 0: TE interrupt disabled Bit 2 1: TE interrupt enabled Direct mode error interrupt enable DMERRIEN 0: DME interrupt disabled Bit 1 1: DME interrupt enabled Stream enable 0: Stream disabled 1: Stream enabled This bit may be cleared by hardware under the following conditions:...
  • Page 702 AT32F435/437 Series Reference Manual 29.5.8 DMA stream-x memory 0 address register (DMA_SxM0ADDR) (x= 1…8) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Memory 0 address Base address of memory area 0. M0ADDR 0x0000 0000 This field can be written only if: Bit 31: 0 ·The stream is disabled (SEN =0)
  • Page 703 AT32F435/437 Series Reference Manual 29.5.11 DMA linked table control register (DMA_SxLLCTRL) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Bit 31: 8 Reserved resd Kept at its default value. Bit 7 S8LLEN Stream8 link list enable Bit 6 S7LLEN Stream7 link list enable...
  • Page 704 AT32F435/437 Series Reference Manual 29.5.15 DMA 2D transfer stride register (DMA_STRIDE)( x = 1…8) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Destination stride This is a signed value (two’s complement). 0x0000: 0 …...
  • Page 705 AT32F435/437 Series Reference Manual 29.5.17 DMAMUX table select (DMA_MUXSEL) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Bit 31: 1 Reserved resd Kept at its default value. Multiplexer table select Bit 0 TBL_SEL 0x1: Flexible mapping table 29.5.18 DMAMUX channel-x control register (DMA_MUXSxCTRL) (x = 1…...
  • Page 706 AT32F435/437 Series Reference Manual 29.5.19 DMAMUX generator-x control register (DMA_MUXGxCTRL) (x = 1…8) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value. DMA request generation count Defines the number of DMA requests (GREQCNT + 1) Bit 23: 19 GREQCNT...
  • Page 707 AT32F435/437 Series Reference Manual 29.5.22 DMAMUX generator interrupt status register (DMA_ MUXGSTS) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Bit 31: 8 Reserved 0x0000 000 resd Kept at its default value. Trigger overrun interrupt flag Bit 7: 0 TRGOVF 0x00...
  • Page 708: Table 30-1 Debug Register Address And Reset Value

    AT32F435/437 Series Reference Manual 30 Debug (DEBUG) 30.1 Debug introduction ® Cortex -M4F core provides powerful debugging features including halt and single step support, as well as trace function that is used for checking the details of the program execution. The debug features are implemented with two interfaces: serial wire debug (SWD) and JTAG debug port.
  • Page 709 Bit 31: 0 PID 0xXXXX XXXX ro PID information PID [31: 0] AT32 part number FLASH size Packages 0x7008_4540 AT32F435ZMT7 4032KB LQFP144 0x7008_3341 AT32F435ZGT7 1024KB LQFP144 0x7008_4598 AT32F435ZDT7 448KB LQFP144 0x7008_3242 AT32F435ZCT7 256KB LQFP144 0x7008_4543 AT32F435VMT7 4032KB LQFP100 0x7008_3344 AT32F435VGT7 1024KB LQFP100 0x7008_4599...
  • Page 710 AT32F435/437 Series Reference Manual 30.4.2 DEBUG control register (DEBUG_CTRL) This register is asynchronously reset by POR Reset (not reset by system reset). It can be written by the debugger under reset. Register Reset value Type Description Bit 31:3 Reserved 0x0000 0000 resd Always 0.
  • Page 711 AT32F435/437 Series Reference Manual I2C1 pause control bit I2C1_SMBUS_TIMEO Bit 24 0: I2C1 SMBUS timeout control works normally 1: I2C1 SMBUS timeout control stops running Bit 23: 16 Reserved 0x00 resd Kept at its default value. ERTC 512Hz output clock pause control bit Bit 15 ERTC_512_PAUSE 0: ERTC 512Hz output clock works normally...
  • Page 712 AT32F435/437 Series Reference Manual Register Reset value Type Description Bit 31: 19 Reserved 0x0000 resd Kept at its default value. TMR11 pause control bit Bit 18 TMR11_PAUSE 0: TMR11 works normally 1: TMR11 stops running TMR10 pause control bit Bit 17 TMR10_PAUSE 0: TMR10 works normally 1: TMR10 stops running...
  • Page 713 AT32F435/437 Series Reference Manual 31 Revision history Document Revision History Date Version Revision Note Initial release. 2021.06.30 2.00 Updated I2C description, and revised some typos. 2021.12.01 2.01 1. Updated Section 13 Serial peripheral interface (SPI) by adding SPI timing diagram. 2.
  • Page 714 No license, express or implied, to any intellectual property rights is granted under this document. If any part of this document deals with any third party products or services, it shall not be deemed a license granted by ARTERY for the use of such third party products or services, or any intellectual property contained therein, or considered as a warranty regarding the use in any manner of such third party products or services or any intellectual property contained therein.

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