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AT32F437VDT7
ARTERY AT32F437VDT7 Manuals
Manuals and User Guides for ARTERY AT32F437VDT7. We have
1
ARTERY AT32F437VDT7 manual available for free PDF download: Reference Manual
ARTERY AT32F437VDT7 Reference Manual (714 pages)
ARM-based 32-bit Cortex-M4F MCU+FPU with 256 to 4032 KB Flash, sLib, dual QSPI, SDRAM, dual OTGFS, Ethernet, camera, 18 timers, 3 ADCs, 23 communication interfaces
Brand:
ARTERY
| Category:
Computer Hardware
| Size: 19 MB
Table of Contents
Table of Contents
2
System Architecture
44
Figure 1-1 AT32F435/437 Series Microcontrollers System Architecture
45
1.1 System Overview
46
ARM Cortex
46
M4F Processor
46
Busmatrix
46
Figure 1-2 Internal Block Diagram of Cortex ® -M4F
46
Figure 1-3 Internal Block Diagram of AHB Busmatrix
47
Bit Band
48
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image a
48
Figure 1-5 Comparison between Bit-Band Region and Its Alias Region: Image B
48
Table 1-1 Bit-Band Address Mapping in SRAM
49
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
49
Interrupt and Exception Vectors
50
Table 1-3 AT32F435/437 Series Vector Table
50
System Tick (Systick)
53
Reset
54
Figure 1-6 Reset Process
54
Figure 1-7 Example of MSP and PC Initialization
55
1.2 List of Abbreviations for Registers
56
1.3 Device Characteristics Information
56
Flash Memory Size Register
56
Device Electronic Signature
56
Table 1-4 List of Abbreviations for Registers
56
Table 1-5 List of Abbreviations for Registers
56
Memory Resources
57
2.1 Internal Memory Address Map
57
2.2 Flash Memory
57
Figure 2-1 AT32F435/437 Address Mapping
57
2.3 SRAM Memory
60
2.4 Peripheral Address Map
60
Table 2-1 Peripheral Boundary Address
60
Power Control (PWC)
63
3.1 Introduction
63
3.2 Main Features
63
3.3 Por/Lvr
63
Figure 3-1 Block Diagram of each Power Supply
63
Power Voltage Monitor (PVM)
64
3.5 Power Domain
64
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
64
Figure 3-3 PVM Threshold and Output
64
3.6 Power Saving Modes
65
3.7 PWC Registers
67
Table 3-1 PW Register Map and Reset Values
67
Power Control Register (PWC_CTRL)
68
Power Control/Status Register (PWC_CTRLSTS)
68
LDO Output Voltage Select Register (PWC_LDOOV)
69
Clock and Reset Manage (CRM)
70
4.1 Clock
70
Clock Sources
70
Figure 4-1 AT32F435/437 Clock Tree
70
System Clock
71
Peripheral Clock
71
Clock Fail Detector
72
Auto Step-By-Step System Clock Switch
72
Clock Output
72
Interrupts
72
4.2 Reset
72
System Reset
72
Battery Powered Domain Reset
74
4.3 CRM Registers
74
Figure 4-2 System Reset Circuit
74
Table 4-1 CRM Register Map and Reset Values
74
Clock Control Register (CRM_CTRL)
75
PLL Clock Configuration Register (CRM_PLLCFG)
76
Clock Configuration Register (CRM_CFG)
77
Clock Interrupt Register (CRM_CLKINT)
79
APB Peripheral Reset Register1 (CRM_APBRST1)
80
APB Peripheral Reset Register2 (CRM_APBRST2)
81
APB Peripheral Reset Register3 (CRM_APBRST3)
81
APB1 Peripheral Reset Register (CRM_APB1RST)
81
APB2 Peripheral Reset Register (CRM_APB2RST)
83
APB Peripheral Clock Enable Register1 (CRM_AHBEN1)
84
APB Peripheral Clock Enable Register2 (CRM_AHBEN2)
85
APB1 Peripheral Clock Enable Register3 (CRM_AHBEN3)
85
APB1 Peripheral Clock Enable Register (CRM_APB1EN)
85
APB2 Peripheral Clock Enable Register (CRM_AHB2EN)
87
4.3.15 APB Peripheral Clock Enable in Low Power Mode Register1
88
(Crm_Ahblpen1)
88
4.3.16 APB Peripheral Clock Enable in Low Power Mode Register2
89
(Crm_Ahblpen2)
89
4.3.17 APB Peripheral Clock Enable in Low Power Mode Register3
90
(Crm_Ahblpen3)
90
4.3.18 APB1 Peripheral Clock Enable in Low Power Mode Register
90
(Crm_Ahb1Lpen)
90
4.3.19 APB2 Peripheral Clock Enable in Low Power Mode Register
91
(Crm_Ahb2Lpen)
91
Battery Powered Domain Control Register (CRM_BPDC)
92
Control/Status Register (CRM_CTRLSTS)
93
Additional Register1 (CRM_MISC1)
94
Additional Register2 (CRM_MISC2)
95
Flash Memory Controller (FLASH)
96
5.1 FLASH Introduction
96
Table 5-1 Flash Memory Architecture (4032 K)
96
Table 5-2 Flash Memory Architecture (1024 K)
97
Table 5-3 Flash Memory Architecture (448 K)
97
Table 5-4 Flash Memory Architecture (256 K)
98
Table 5-5 User System Data Area
98
Table 5-6 Extended System Options
101
5.2 Flash Memory Operation
102
Unlock/Lock
102
Erase Operation
102
Figure 5-1 Flash Memory Sector Erase Process
103
Figure 5-2 Flash Memory Block Erase Process
104
Programming Operation
105
Figure 5-3 Flash Memory Mass Erase Process
105
Read Operation
106
5.3 User System Data Area Operation
106
Unlock/Lock
106
Figure 5-4 Flash Memory Programming Process
106
Erase Operation
107
Figure 5-5 System Data Area Erase Process
107
Programming Operation
108
Figure 5-6 System Data Area Programming Process
108
Read Operation
109
5.4 Flash Memory Protection
109
Access Protection
109
Erase/Program Protection
109
5.5 Special Functions
109
Security Library Settings
109
Table 5-7 Flash Memory Access Limit
109
5.6 Flash Memory Registers
110
Flash Performance Select Register (FLASH_PSR)
111
Table 5-8 Flash Memory Interface-Register Map and Reset Value
111
Flash Unlock Register (FLASH_UNLOCK)
112
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
112
Flash Status Register (FLASH_STS)
112
Flash Control Register (FLASH_CTRL)
112
Flash Address Register (FLASH_ADDR)
113
User System Data Register (FLASH_USD)
113
Erase/Program Protection Status Register0 (FLASH_EPPS0)
114
Erase/Program Protection Status Register1 (FLASH_EPPS1)
114
Flash Unlock Register2 (FLASH_UNLOCK2)
114
Figure 6-1 GPIO Basic Structure
119
Figure 6-2 IOMUX Structure
121
Table 6-1 Port a Multiplexed Function Configuration with GPIOA_MUX* Register
122
Table 6-2 Port B Multiplexed Function Configuration with GPIOB_MUX* Register
124
Table 6-3 Port C Multiplexed Function Configuration with GPIOC_MUX* Register
126
Table 6-4 Port D Multiplexed Function Configuration with GPIOD_MUX* Register
128
Table 6-5 Port E Multiplexed Function Configuration with GPIOE_MUX* Register
130
Table 6-6 Port F Multiplexed Function Configuration with GPIOF_MUX* Register
132
Table 6-7 Port G Multiplexed Function Configuration with GPIOG_MUX* Register
134
Table 6-8 Port H Multiplexed Function Configuration with GPIOH_MUX* Register
136
Table 6-9 Pins Owned by Hardware
136
Table 6-10 GPIO Register Map and Reset Values
137
Table 7-1 SCFG Register Map and Reset Values
141
Figure 8-1 External Interrupt/Event Controller Block Diagram
149
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
150
Figure 9-1 DMA Block Diagram
152
Figure 9-2 Re-Arbitrate after Request/Acknowledge
154
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
154
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
155
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
155
Table 9-1 DMA Error Event
155
Table 9-2 DMA Interrupt Requests
155
Figure 9-6 DMAMUX Block Diagram
156
Table 9-3 Flexible DMA1/DMA2 Request Mapping
157
Figure 9-7 DMAMUX Request Synchronized Mode
158
Table 9-4 DMAMUX EXINT LINE for Trigger Input and Synchronized Input
158
Figure 9-8 DMAMUX Event Generation
159
Table 9-5 DMA Register Map and Reset Value
159
Figure 10-1 CRC Calculation Unit Block Diagram
169
Figure 10-2 Diagram of Byte Reverse
170
Table 10-1 CRC Register Map and Reset Value
170
Figure 11-1 I C Bus Protocol
172
Figure 11-2 I C Function Block Diagram
173
Figure 11-3 Setup and Hold Time
175
Table 11-1 I C Timing Specifications
176
Table 11-2 I 2 C Configuration Table
177
Figure 11-4 I 2 C Master Transmission Flow
179
Figure 11-5 Transfer Sequence of I
180
Figure 11-6 I 2 C Master Receive Flow
180
Figure 11-7 Transfer Sequence of I
181
Figure 11-8 10-Bit Address Read Access When READH10=1
181
Figure 11-9 10-Bit Address Read Access When READH10=0
181
Figure 11-10 I 2 C Slave Transmission Flow
184
Figure 11-11 I 2 C Slave Transmission Timing
184
Figure 11-12 I 2 C Slave Receive Flow
185
Figure 11-13 I 2 C Slave Receive Timing
185
Table 11-3 Smbus Timeout Specification
187
Table 11-4 Smbus Timeout Detection Configuration
187
Table 11-5 Smbus Mode Configuration
188
Figure 11-14 Smbus Master Transmission Flow
190
Figure 11-15 Smbus Master Transmission Timing
191
Figure 11-16 Smbus Master Receive Flow
191
Figure 11-17 Smbus Master Receive Timing
192
Figure 11-18 Smbus Slave Transmission Flow
194
Figure 11-19 Smbus Slave Transmission Timing
194
Figure 11-20 Smbus Slave Receive Flow
195
Figure 11-21 Smbus Slave Receive Timing
195
Table 11-6 I 2 C Error Events
196
Table 11-7 I 2 C Interrupt Requests
198
Table 11-8 I 2 C Register Map and Reset Values
198
Figure 12-1 USART Block Diagram
205
Figure 12-2 BFF and FERR Detection in LIN Mode
208
Figure 12-3 Smartcard Frame Format
208
Figure 12-4 Irda DATA(3/16) - Normal Mode
209
Figure 12-5 Hardware Flow Control
209
Figure 12-6 Mute Mode Using Idle Line or Address Mark Detection
210
Figure 12-7 8-Bit Format USART Synchronous Mode
210
Figure 12-8 Word Length
211
Figure 12-9 Stop Bit Configuration
212
Table 12-1 Error Calculation for Programmed Baud Rate
213
Figure 12-10 TDC/TDBE Behavior When Transmitting
215
Table 12-2 Data Sampling over Start Bit and Noise Detection
216
Figure 12-11 Data Sampling for Noise Detection
217
Table 12-3 Data Sampling over Valid Data and Noise Detection
217
Figure 12-12 Tx/Rx Swap
218
Table 12-4 USART Interrupt Request
218
Figure 12-13 USART Interrupt Map Diagram
219
Table 12-5 USART Register Map and Reset Value
219
Figure 13-1 SPI Block Diagram
225
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
226
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
227
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
227
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
228
Figure 13-6 Master Full-Duplex Communications
232
Figure 13-7 Slave Full-Duplex Communications
233
Figure 13-8 Master Half-Duplex Transmit
233
Figure 13-9 Slave Half-Duplex Receive
233
Figure 13-10 Slave Half-Duplex Transmit
234
Figure 13-11 Master Half-Duplex Receive
234
Figure 13-12 TI Mode Continous Transfer
234
Figure 13-13 TI Mode Continous Transfer with Dummy CLK
235
Figure 13-14 TI Mode Continous Transfer with Dummy CLK
235
Figure 13-15 SPI Interrupts
235
Figure 13-16 I 2 S Block Diagram
236
Figure 13-17 I 2 S Full-Duplex Structure
237
Figure 13-18 I 2 S Slave Device Transmission
237
Figure 13-19 I 2 S Slave Device Reception
238
Figure 13-20 I S Master Device Transmission
238
Figure 13-21 I 2 S Master Device Reception
238
Figure 13-22 CK & MCK Source in Master Mode
240
Table 13-1 Audio Frequency Precision Using System Clock
240
Figure 13-23 Audio Standard Timings
243
Figure 13-24 I S Interrupts
244
Table 13-2 SPI Register Map and Reset Value
245
Table 14-1 TMR Functional Comparison
250
Figure 14-1 Basic Timer Block Diagram
251
Figure 14-2 Control Circuit with CK_INT Divided by 1
251
Figure 14-3 Counter Structure
252
Figure 14-4 Overflow Event When PRBEN=0
252
Figure 14-5 Overflow Event When PRBEN=1
252
Figure 14-6 Counter Timing Diagram with Internal Clock Divided by 4
252
Table 14-2 TMR6 and TMR7- Register Table and Reset Value
253
Figure 14-7 General-Purpose Timer Block Diagram
255
Figure 14-8 Count Clock
256
Figure 14-9 Use CK_INT to Drive Counter with Tmrx_Div=0X0 and Tmrx_Pr=0X16
256
Figure 14-10 Block Diagram of External Clock Mode a
257
Figure 14-11 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
257
Figure 14-12 Block Diagram of External Clock Mode B
258
Figure 14-13 Counting in External Clock Mode B, with Pr=0X32 and DIV=0X0
258
Table 14-3 Tmrx Internal Trigger Connection
258
Figure 14-14 Counter Timing with Prescaler Value Changing from 1 to 4
259
Figure 14-15 Counter Structure
259
Figure 14-16 Overflow Event When PRBEN=0
260
Figure 14-17 Overflow Event When PRBEN=1
260
Figure 14-18 Counter Timing Diagram with Internal Clock Divided by 4
260
Figure 14-19 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
261
Figure 14-20 Encoder Mode Structure
261
Figure 14-21 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
262
Table 14-4 Counting Direction Versus Encoder Signals
262
Figure 14-22 Input/Output Channel 1 Main Circuit
263
Figure 14-23 Channel 1 Input Stage
263
Figure 14-24 Example of PWM Input Mode Configuration
264
Figure 14-25 PWM Input Mode
264
Figure 14-26 Capture/Compare Channel Output Stage (Channel 1 to 4)
265
Figure 14-27 C1ORAW Toggles When Counter Value Matches the C1DT Value
266
Figure 14-28 Upcounting Mode and PWM Mode a
266
Figure 14-29 Up/Down Counting Mode and PWM Mode a
266
Figure 14-30 One-Pulse Mode
267
Figure 14-31 Clearing Cxoraw (PWM Mode A) by EXT Input
267
Figure 14-32 Example of Reset Mode
268
Figure 14-33 Example of Suspend Mode
268
Figure 14-34 Example of Trigger Mode
268
Figure 14-35 Master/Slave Timer Connection
269
Figure 14-36 Using Master Timer to Start Slave Timer
269
Figure 14-37 Starting Master and Slave Timers Synchronously by an External Trigger
270
Table 14-5 Tmrx Register Map and Reset Value
270
Table 14-6 Standard Cxout Channel Output Control Bit
279
Figure 14-38 Block Diagram of General-Purpose TMR9/12
282
Figure 14-39 Block Diagram of General-Purpose TMR10/11/13/14
283
Figure 14-40 Count Clock
283
Figure 14-41 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
283
Figure 14-42 Block Diagram of External Clock Mode a
284
Figure 14-43 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
284
Figure 14-44 Counter Timing with Prescaler Value Changing from 1 to 4
285
Table 14-7 Tmrx Internal Trigger Connection
285
Figure 14-45 Counter Structure
286
Figure 14-46 Overflow Event When PRBEN=0
287
Figure 14-47 Overflow Event When PRBEN=1
287
Figure 14-48 Input/Output Channel 1 Main Circuit
288
Figure 14-49 Channel 1 Input Stage
288
Figure 14-50 Example of PWM Input Mode Configuration
289
Figure 14-51 PWM Input Mode
289
Figure 14-52 Capture/Compare Channel Output Stage (Channel 1)
290
Figure 14-53 C1ORAW Toggles When Counter Value Matches the C1DT Value
291
Figure 14-54 Upcounting Mode and PWM Mode a
291
Figure 14-55 One-Pulse Mode
291
Figure 14-56 Example of Reset Mode
292
Figure 14-57 Example of Suspend Mode
292
Figure 14-58 Example of Trigger Mode
293
Table 14-8 Tmrx Register Map and Reset Value
293
Table 14-9 Standard Cxout Channel Output Control Bit
298
Table 14-10 Tmrx Register Map and Reset Value
299
Table 14-11 Standard Cxout Channel Output Control Bit
303
Figure 14-59 Block Diagram of Advanced-Control Timer
304
Figure 14-60 Count Clock
305
Figure 14-61 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
305
Figure 14-62 Block Diagram of External Clock Mode a
306
Figure 14-63 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
306
Figure 14-64 Block Diagram of External Clock Mode B
307
Figure 14-65 Counting in External Clock Mode B, with Pr=0X32 and DIV=0X0
307
Table 14-12 Tmrx Internal Trigger Connection
307
Figure 14-66 Counter Timing with Prescaler Value Changing from 1 to 4
308
Figure 14-67 Counter Structure
308
Figure 14-68 Overflow Event When PRBEN=0
309
Figure 14-69 Overflow Event When PRBEN=1
309
Figure 14-70 Counter Timing Diagram with Internal Clock Divided by 4
309
Figure 14-71 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
310
Figure 14-72 OVFIF in Upcounting Mode and Up/Down Counting Mode
310
Figure 14-73 Encoder Mode Structure
311
Table 14-13 Counting Direction Versus Encoder Signals
311
Figure 14-74 Example of Encoder Interface Mode C
312
Figure 14-75 Input/Output Channel 1 Main Circuit
312
Figure 14-76 Channel 1 Input Stage
313
Figure 14-77 Example of PWM Input Mode Configuration
314
Figure 14-78 PWM Input Mode
314
Figure 14-79 Channel Output Stage (Channel 1 to 3)
314
Figure 14-80 Channel 4 Output Stage
315
Figure 14-81 C1ORAW Toggles When Counter Value Matches the C1DT Value
316
Figure 14-82 Upcounting Mode and PWM Mode a
316
Figure 14-83 Up/Down Counting Mode and PWM Mode a
317
Figure 14-84 One-Pulse Mode
317
Figure 14-85 Clearing Cxoraw(PWM Mode A) by EXT Input
318
Figure 14-86 Complementary Output with Dead-Time Insertion
318
Figure 14-87 TMR Output Control
319
Figure 14-88 Example of TMR Break Function
320
Figure 14-89 Example of Reset Mode
320
Figure 14-90 Example of Suspend Mode
321
Figure 14-91 Example of Trigger Mode
321
Table 14-14 TMR1 and TMR8 Register Map and Reset Value
322
Table 14-15 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
331
Figure 15-1 Window Watchdog Block Diagram
336
Figure 15-2 Window Watchdog Timing Diagram
337
Table 15-1 Minimum and Maximum Timeout Value When PCLK1=72 Mhz
337
Table 15-2 WWDT Register Map and Reset Value
337
Figure 16-1 WDT Block Diagram
340
Table 16-1 WDT Timeout Period (Lick=40Khz)
340
Table 16-2 WDT Register and Reset Value
340
Figure 17-1 ERTC Block Diagram
342
Table 17-1 RTC Register Map and Reset Values
343
Table 17-2 ERTC Low-Power Mode Wakeup
349
Table 17-3 Interrupt Control Bits
349
Table 17-4 ERTC Register Map and Reset Values
349
Figure 18-1 ADC1 Block Diagram
360
Figure 18-2 ADC Basic Operation Process
362
Figure 18-3 ADC Power-On and Calibration
363
Table 18-1 Trigger Sources for Ordinary Channels
363
Table 18-2 Trigger Sources for Preempted Channels
364
Figure 18-4 Sequence Mode
365
Figure 18-5 Preempted Group Auto Conversion Mode
365
Figure 18-6 Repetition Mode
366
Figure 18-7 Partition Mode
366
Figure 18-8 ADABRT Timing Diagram
367
Table 18-3 Correlation between Maximum Cumulative Data, Oversampling Multiple and Shift Digits
367
Figure 18-9 Ordinary Oversampling Restart Mode Selection
368
Figure 18-10 Ordinary Oversampling Trigger Mode
369
Figure 18-11 Oversampling of Preempted Group of Channels
369
Figure 18-12 Data Alignment
370
Figure 18-13 Block Diagram of Master/Salve Mode
371
Table 18-4 Master/Slave DMA Mode
372
Figure 18-14 Regular Simultaneous Mode
373
Figure 18-15 Regular Simultaneous Mode
373
Figure 18-16 Alternate Preempted Trigger Mode
374
Figure 18-17 Regular Shift Mode
374
Figure 18-18 Regular Shift Mode and DMA Mode 2
375
Table 18-5 ADC Register Map and Reset Values
375
Figure 19-1 DAC1/DAC2 Block Diagram
392
Table 19-1 Trigger Source Selection
393
Figure 19-2 LFSR Register Calculation Algorithm
394
Figure 19-3 Triangular-Wave Generation
394
Table 19-2 DAC Register Map and Reset Values
395
Figure 20-1 Bit Timing
400
Figure 20-2 Transmit Interrupt Generation
402
Figure 20-3 Transmit Interrupt Generation
403
Figure 20-4 Receive Interrupt 0 Generation
403
Figure 20-5 Receive Interrupt 1 Generation
403
Figure 20-6 Status Error Interrupt Generation
403
Figure 20-7 CAN Block Diagram
404
Figure 20-8 32-Bit Identifier Mask Mode
406
Figure 20-9 32-Bit Identifier List Mode
406
Figure 20-10 16-Bit Identifier Mask Mode
406
Figure 20-11 16-Bit Identifier List Mode
407
Figure 20-12 Transmit Mailbox Status
408
Figure 20-13 Receive FIFO Status
409
Table 20-1 CAN Register Map and Reset Values
410
Figure 20-14 Transmit and Receive Mailboxes
420
Figure 21-1 Block Diagram of OTGFS Structure
424
Table 21-1 OTGFS Input/Output Pins
425
Figure 21-2 OTGFS Interrupt Hierarchy
426
Table 21-2 OTGFS Transmit FIFO SRAM Allocation
427
Table 21-3 OTGFS Internal Storage Space Allocation
429
Figure 21-3 Writing the Transmit FIFO
431
Figure 21-4 Reading the Receive FIFO
432
Figure 21-5 HFIR Behavior When Hfirrldctrl=0X0
433
Figure 21-6 HFIR Behavior When Hfirrldctrl=0X1
434
Figure 21-7 Example of Common Bulk/Control OUT/SETUP and Bulk/Control in Transfer
437
Figure 21-8 Example of Common Interrupt OUT/IN Transfers
441
Figure 21-9 Example of Common Synchronous OUT/IN Transfers
444
Figure 21-10 Read Receive FIFO
449
Figure 21-11 SETUP Data Packet Flowchart
451
Figure 21-12 BULK out Transfer Block Diagram
455
Figure 21-13 CSR Memory Map
461
Table 21-4 OTGFS Register Map and Reset Values
462
Table 21-5 Minimum Duration for Software Disconnect
486
Figure 22-1 ACC Interrupt Mapping Diagram
499
Table 22-1 ACC Interrupt Requests
499
Figure 22-2 ACC Block Diagram
500
Figure 22-3 Cross-Return Algorithm
501
Table 22-2 ACC Register Map and Reset Values
502
Figure 23-1 IRTMR Block Diagram
505
Figure 24-1 XMC Block Diagram
508
Table 24-1 NOR/PSRAM Pins
508
Table 24-2 NAND Pins
509
Table 24-3 PC Card Pins
509
Table 24-4 SDRAM Pins
509
Figure 24-2 XMC Memory Banks
510
Table 24-5 Memory Bank Selection
511
Table 24-6 8-Bit SDRAM Address Mapping
511
Table 24-7 16-Bit SDRAM Address Mapping
512
Table 24-8 Pin Signals for nor and PSRAM
512
Table 24-9 Address Translation between HADDR and External Memory
513
Table 24-10 Data Access Width Vs. External Memory Data Width
513
Table 24-11 NOR/PSRAM Parameter Registers
514
Table 24-12 Mode 1- SRAM/NOR Flash Chip Select Control Register (XMC_BK1CTRL) Configuration
514
Table 24-13 Mode 1- SRAM/NOR Flash Chip Select Timing Register (XMC_ BK1TMG) Configuration
514
Figure 24-3 NOR/PSRAM Mode 1 Read Access
515
Figure 24-4 NOR/PSRAM Mode 1 Write Access
515
Table 24-14 Mode 2 - SRAM/NOR Flash Chip Select Control Register
515
Figure 24-5 NOR/PSRAM Mode 2 Read Access
516
Table 24-15 Mode 2 - SRAM/NOR Flash Chip Select Timing Register
516
Figure 24-6 NOR/PSRAM Mode 2 Write Access
517
Table 24-16 Mode A- SRAM/NOR Flash Chip Select Control Register
517
Figure 24-7 NOR/PSRAM Mode a Read Access
518
Table 24-17 Mode A- SRAM/NOR Flash Chip Select Timing Register
518
Table 24-18 Mode A- SRAM/NOR Flash Write Timing Register
518
Figure 24-8 NOR/PSRAM Mode a Write Access
519
Table 24-19 Mode B- SRAM/NOR Flash Chip Select Register
519
Figure 24-9 NOR/PSRAM Mode B Read Access
520
Table 24-20 Mode B- SRAM/NOR Flash Chip Select Timing Register
520
Table 24-21 Mode B- SRAM/NOR Flash Write Timing Register
520
Figure 24-10 NOR/PSRAM Mode B Write Access
521
Table 24-22 Mode C- SRAM/NOR Flash Chip Select Register
521
Figure 24-11 NOR/PSRAM Mode C Read Access
522
Table 24-23 Mode C-SRAM/NOR Flash Chip Select Timing Register
522
Table 24-24 Mode C- SRAM/NOR Flash Write Timing Register
522
Figure 24-12 NOR/PSRAM Mode C Write Access
523
Table 24-25 Mode D- SRAM/NOR Flash Chip Select Register (XMC_BK1CTRL) Configuration
523
Figure 24-13 NOR/PSRAM Mode D Read Access
524
Table 24-26 Mode D-SRAM/NOR Flash Chip Select Timing Register
524
Table 24-27 Mode D- SRAM/NOR Flash Write Timing Register
524
Figure 24-14 NOR/PSRAM Mode D Write Access
525
Table 24-28 Multiplexed Mode - SRAM/NOR Flash Chip Select Control Register
525
Figure 24-15 NOR/PSRAM Multiplexed Mode Read Access
526
Table 24-29 Multiplexed Mode-SRAM/NOR Flash Chip Select Timing Register (XMC_BK1TMG) Configuration
526
Figure 24-16 NOR/PSRAM Multiplexed Mode Write Access
527
Table 24-30 Synchronous Mode - SRAM/NOR Flash Chip Select Control Register
527
Figure 24-17 NOR/PSRAM Synchronous Multiplexed Mode Read Access
528
Table 24-31 Synchronous Mode-SRAM/NOR Flash Chip Select Timing Register (XMC_BK1TMG)
528
Figure 24-18 NOR/PSRAM Synchronous Multiplexed Mode Write Access
529
Table 24-32 Typical Pin Signals for NAND Flash
529
Figure 24-19 NAND Read Access
530
Table 24-33 Data Access Width Vs. External Memory Data Width
530
Table 24-34 NAND Parameter Registers
530
Figure 24-20 NAND Wait Functionality
531
Table 24-35 Lists the ECC Result Bits Corresponding to the Number of Bytes
531
Table 24-36 Typical Pin Signals for PC Card
532
Table 24-37 Access Data Width and PC Card Data Width
532
Table 24-38 PC Card Parameter Register
532
Figure 24-21 PC Card Read/Write
533
Figure 24-22 SDRAM Write Access Waveforms (Trcd=2, 9 Consecutive Write Access)
534
Figure 24-23 SDRAM Read Access Without Using Read FIFO (Trcd=2,Cl=3, and 4 Consecutive Read Accesses)
535
Table 24-39 XMC Register Address Mapping
536
Figure 25-1 SDIO "No Response" and "Response" Operations
552
Figure 25-2 SDIO Multiple Block Read Operation
552
Figure 25-3 SDIO Multiple Block Write Operation
552
Figure 25-4 SDIO Sequential Read Operation
553
Figure 25-5 SDIO Sequential Write Operation
553
Table 25-1 Lock/Unlock Command Structure
556
Table 25-2 Commands
558
Table 25-3 Data Block Read Commands
559
Table 25-4 Data Stream Read/Write Commands
560
Table 25-5 Data Block Write Commands
560
Table 25-6 Block-Based Write Protect Commands
560
Table 25-7 Erase Commands
561
Table 25-8 I/O Mode Commands
561
Table 25-9 Card Lock Commands
561
Table 25-10 Application-Specific Commands
562
Table 25-11 R1 Response
562
Table 25-12 R2 Response
563
Table 25-13 R3 Response
563
Table 25-14 R4 Response
563
Table 25-15 R4B Response
563
Table 25-16 R5 Response
563
Table 25-17 R6 Response
564
Figure 25-6 SDIO Block Diagram
565
Table 25-18 SDIO Pin Definitions
565
Table 25-19 Command Formats
566
Table 25-20 Short Response Format
566
Table 25-21 Long Response Format
566
Figure 25-7 Command Channel State Machine (CCSM)
567
Table 25-22 Command Path Status Flags
567
Figure 25-8 SDIO Command Transfer
568
Figure 25-9 Data Channel State Machine (DCSM)
568
Table 25-23 Data Token Formats
569
Table 25-24 a Summary of the SDIO Registers
571
Table 25-25 Response Type and Sdio_Rspx Register
574
Figure 26-1 Block Diagram of EMAC
580
Figure 26-2 SMI Interface Signals
582
Table 26-1 Shows the Clock Range
582
Figure 26-3 MII Signals
583
Figure 26-4 Reduced Media-Independent Interface Signals
584
Table 26-2 Transmit Interface Signal Encode
584
Table 26-3 Receive Interface Signal Encode
584
Figure 26-5 MII Clock Sources (Provided by CLKOUT Pin)
585
Figure 26-6 MII Clock Sources (Provided by an External Oscillator)
585
Figure 26-7 RMII Clock Sources (Provided by an External Crystal Oscillator)
585
Figure 26-8 MAC Frame Format
586
Table 26-4 Ethernet Peripheral Pin Configuration
586
Figure 26-9 Tagged MAC Frame Format
587
Table 26-5 Destination Address Filtering
589
Table 26-6 Source Address Filtering
589
Figure 26-10 Descriptor for Ring and Chain Structure
594
Figure 26-11 Transmit Descriptors
597
Figure 26-12 RXDMA Descriptor Structure
602
Table 26-7 Receive Descriptor 0
603
Figure 26-13 Wakeup Frame Filter Register
605
Figure 26-14 System Time Update Using the Fine Correction Method
608
Figure 26-15 PTP Trigger Output to TMR2 ITR1 Connection
609
Figure 26-16 PPS Output
610
Figure 26-17 Ethernet Interrupts
611
Table 26-8 Ethernet Register Map and Its Reset Values
611
Figure 26-18 Ethernet MAC Remote Wakeup Frame Filter Register (EMAC_MACRWFF)
620
Figure 27-1 DVP Block Diagram
644
Figure 27-2 CMOS Video Camera Output in Frame Start Type
645
Figure 27-3 CMOS Video Camera Output in Frame Valid Type
645
Figure 27-4 FS/FE/LS/LE Frame Composition
646
Table 27-1 DVP Pin Use in Hardware Synchronization Mode
646
Figure 27-5 SAV/EAV Frame Composition
647
Table 27-2 DVP Pin Use in Embedded Synchronization Mode
647
Figure 27-6 Block Diagram in Single Frame Capture Mode
648
Table 27-3 DVP Register Configuration and DVP_D Pin Use
648
Figure 27-7 Block Diagram in Continuous Capture Mode
649
Figure 27-8 PDL Configuration and Data Output Packing
650
Figure 27-9 Block Diagram of Frame Rate Control Feature
651
Figure 27-10 Crop Window Block Diagram
652
Figure 27-11 Image Resizing Block Diagram
652
Figure 27-12 LCDC/LCDS and Frame Structure
653
Figure 27-13 PCDC/PCDS and Line Structure
654
Figure 27-14 RGB565-Format Data Capture and Packing
655
Figure 27-15 RGB555-Format Data Capture and Packing
656
Figure 27-16 YUV422-Format Data Capture and Packing
656
Figure 27-17 Y8 (Y-Only)-Format Data Capture and Packing
657
Table 27-4 Enhanced Features and DVP Data Formats Supported
657
Figure 27-18 YUV422 Format to Y8 (Y-Only) Format
658
Table 27-5 DVP Register Map and Reset Values
658
Figure 28-1 Function Block Diagram
666
Figure 28-2 DMA Handshake Mode
667
Figure 28-3 Write Enable
668
Figure 28-5 Status Read
668
Figure 28-6 Data Read
668
Figure 28-7 Quick Read Dual Output Command
669
Figure 28-8 Quick Read Dual-Wire I/O
669
Figure 28-9 Quick Read Quad Output
669
Figure 28-10 Quick Read Quad I/O Command
670
Table 28-1 SPI Register Map and Reset Values
673
Figure 29-1 Block Diagram
681
Figure 29-2 Channel Select and Synchronizer
683
Figure 29-3 Re-Arbitrate after Request/Acknowledge
684
Figure 29-4 Example of Packing Mechanism
684
Figure 29-5 Example of Unpacking Mechanism
685
Figure 29-6 Example of PINCOS
685
Figure 29-7 Descriptor Format
686
Figure 29-8 Linked List Pointers
686
Figure 29-9 Example of a 2D Transfer (Source Side Is Managed by a Peripheral Controller)
687
Figure 29-10 Example of a 2D Transfer (Destination Side Is Managed by a Memory Controller)
688
Table 29-1 DMA Error Events
688
Table 29-2 DMA Interrupts
689
Figure 29-11 DMAMUX Block Diagram
690
Table 29-3 EDMA Flexible Request Mapping
690
Figure 29-12 DMAMUX Synchronized Mode
691
Table 29-4 DMAMUX EXINT LINE for Trigger Input and Synchronized Input
691
Figure 29-13 DMAMUX Event Generation
692
Table 29-5 BPR Register Map and Reset Values
693
Table 30-1 DEBUG Register Address and Reset Value
708
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