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ARTERY AT32F403A Series Reference Manual

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®

ARM

-based 32-bit Cortex

USB, Ethernet, 2 CANs, 17 timers, 3 ADCs, 21 communication interfaces

Feature



®

Core: ARM

32-bit Cortex

− 240 MHz maximum frequency, with a Memory

Protection Unit (MPU), single-cycle multiplication

and hardware division

− Floating Point Unit (FPU)

− DSP instructions



Memories

− 256 to 1024 KBytes of Flash memory

− sLib: configurable part of main Flash set as a library

area with code excutable but secured, non-readable

− SPIM interface: extra interfacing up to 16 Mbytes of

external SPI Flash (as instruction/data memory)

− Up to 96 + 128 KBytes of SRAM

− External memory controller (XMC) with 2 Chip

Select, supports multiplexed SRAM/NOR/PSRAM

and NAND memories

− LCD parallel interface, 8080/6800 modes



Clock, Reset, and Power management

− 2.6 V ~ 3.6 V application suppy and I/Os

− Power on reset (POR)/ low voltage reset (LVR), and

power voltage monitor (PVM)

− 4 to 25 MHz crystal (HEXT)

− Internal 48 MHz factory-trimmed RC (accuracy 1%

at T

=25 °C, 2.5 % at T

A

automatic clock calibration (ACC)

− Internal 40 kHz RC oscillator (LICK)

− 32.768 kHz crystal oscillator (LEXT)



Low power consumption

− Sleep, Deepsleep, and Standby modes

− V

supply for RTC and 42 x 16-bit battery powered

BAT

registers (BPR)



3 x 12-bit 0.5 μs A/D converters, up to 16 channels

− Conversion range: 0 V to 3.6 V

− Triple sample and hold capability

− Temparature sensor



2 x 12-bit D/A converters



DMA: 14-channel DMA controller

− Peripherals supported: timers, ADCs, SDIOs,

I

2

Ss, SPIs, I

2

Cs, and USARTs



Debug Mode

−

Serial wire debug

− Cortex

®

-M4F Embedded Trace Macrocell (ETM



Up to 80 Fast I/O Interfaces

2021.12.01

AT32F403A/407 Series Reference Manual

®

-M4F MCU+FPU with 256 to 1024 KB Flash, sLib,

®

-M4F CPU with FPU

=-40 to +105 °C), with

A

(SWD) and JTAG

interface

− 37/51/80 multifunctional and bidirectional I/Os, all

mappable to 16 external interrupt vectors and almost 5

V-tolerant

− All fast I/Os, control registers accessable with f



Up to 17 Timers

− Up to 8 x 16-bit timers + 2 x 32-bit timers; each with 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input.

− Up to 2 x 16-bit motor control PWM advanced timers

with dead-time generator and emergency brake

− 2 x Watchdog timers

− SysTick timer: 24-bit downcounter

− 2 x 16-bit basic timers to drive the DAC



Up to 21 Communication Interfaces

− Up to 3 x I

− Up to 8 x USARTs (ISO7816 interface, LIN, IrDA

capability, and modem control)

− Up to 4 x SPIs (50 Mbit/s), all with I

multiplexed,. I

− Up to 2 x CAN interfaces (2.0B Active)

− USB2.0 full-speed interface supporting Crystal-less

− Up to 2 x SDIO interfaces

− 10/100M Ethernet MAC with dedicated DMA and

SRAM(4 KBytes): IEEE1588 hardware support, MII/RMII

available



CRC Calculation Unit



96-bit unique ID (UID)



Packages

− LQFP100 14x14 mm

− LQFP64 10x10 mm

− LQFP48 7x7 mm

− QFN48 6 x 6 mm

 List of Models

Internal Flash

AT32F403ACGU7, AT32F403ACGT7,

1024 KBytes

AT32F403ARGT7, AT32F403AVGT7,

AT32F407RGT7, AT32F407VGT7, AT32F407AVGT7

AT32F403ACEU7, AT32F403ACET7,

512 KBytes

AT32F403ARET7, AT32F403AVET7,

AT32F407RET7, AT32F407VET7

AT32F403ACCU7, AT32F403ACCT7,

256 KBytes

AT32F403ARCT7, AT32F403AVCT7,

TM

)

AT32F407RCT7, AT32F407VCT7, AT32F407AVCT7

Page 1

2

C interfaces (SMBus/PMBus)

2

S interface

2

2

S2/ I

S3 support full-duplex

Model

speed

AHB

Ver 2.02

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Summary of Contents for ARTERY AT32F403A Series

Page 1: Sram/Nor Flash Chip Select Control Register
AT32F403A/407 Series Reference Manual ® ® -based 32-bit Cortex -M4F MCU+FPU with 256 to 1024 KB Flash, sLib, USB, Ethernet, 2 CANs, 17 timers, 3 ADCs, 21 communication interfaces Feature  − 37/51/80 multifunctional and bidirectional I/Os, all ® ® Core: ARM 32-bit Cortex -M4F CPU with FPU...
Page 2: Table Of Contents
AT32F403A/407 Series Reference Manual Contents System architecture ..............35 System overview ................37 1.1.1 ARM Cortex -M4F processor ............37 1.1.2 Bit band ..................38 1.1.3 Interrupt and exception vectors ............ 40 1.1.4 System Tick (SysTick) ..............43 1.1.5 Reset ..................43 List of abbreviations for registers ..........
Page 3 AT32F403A/407 Series Reference Manual 4.1.1 Clock sources ................58 4.1.2 System clock ................59 4.1.3 Peripheral clock ................59 4.1.4 Clock fail detector ............... 60 4.1.5 Auto step-by-step system clock switch .......... 60 4.1.6 Internal clock output ..............60 4.1.7 Interrupts ..................60 Reset ..................
Page 4 AT32F403A/407 Series Reference Manual User system data area operation ........... 86 5.4.1 Unlock/lock ................. 86 5.4.2 Erase operation ................86 5.4.3 Programming operation..............87 5.4.4 Read operation ................88 Flash memory protection .............. 88 5.5.1 Access protection ................ 89 5.5.2 Erase/program protection............. 89 Special functions .................
Page 5 AT32F403A/407 Series Reference Manual 5.7.25 Security library unlock register (SLIB_UNLOCK) ......98 5.7.26 Flash CRC check control register (FLASH_CRC_CTRL) ....99 5.7.27 Flash CRC check result register (FLASH_CRC_CHKR) ....99 General-purpose I/Os (GPIOs) ............. 100 Introduction ................100 Function overview ..............100 6.2.1 GPIO structure ................
Page 6 AT32F403A/407 Series Reference Manual IOMUX registers ................ 108 7.3.1 Event output control register (IOMUX_EVTOUT) ......108 7.3.2 IOMUX remap register (IOMUX_REMAP) ........109 7.3.3 IOMUX external interrupt configuration register1 (IOMUX_EXINTC1) ................111 7.3.4 IOMUX external interrupt configuration reg ister2 (IOMUX_EXINTC2) ................112 7.3.5 IOMUX external interrupt configuration register3 (IOMUX_EXINTC3) ................
Page 7 AT32F403A/407 Series Reference Manual 9.3.2 Handshake mechanism ............... 125 9.3.3 Arbiter ..................125 9.3.4 Programmable data transfer width ..........126 9.3.5 Errors ..................127 9.3.6 Interrupts ................... 127 9.3.7 Fixed DMA request mapping ............127 9.3.8 Flexible DMA request mapping ............ 128 DMA registers ................
Page 8 AT32F403A/407 Series Reference Manual 11.4.3 Utilize DMA for data transfer ............151 11.4.4 SMBus ..................151 11.4.5 I C interrupt requests ..............153 11.4.6 I C debug mode ................. 153 11.5 I C registers ................154 11.5.1 Control register1 (I2C_CTRL1) ............ 154 11.5.2 Control register2 (I2C_CTRL2) ............
Page 9 AT32F403A/407 Series Reference Manual 12.9 Interrupt requests ..............168 12.10I/O pin control................169 12.11USART registers ................ 169 12.11.1 Status register (USART_STS) ..........169 12.11.2 Data register (USART_DT) ............171 12.11.3 Baud rate register (USART_BAUDR) ........171 12.11.4 Control register1 (USART_CTRL1) ........... 171 12.11.5 Control register2 (USART_CTRL2) ...........
Page 10 AT32F403A/407 Series Reference Manual 13.4 SPI registers ................190 13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I S mode) ... 190 13.4.2 SPI control register2 (SPI_CTRL2) ..........191 13.4.3 SPI status register (SPI_STS) ............. 192 13.4.4 SPI data register (SPI_DT) ............193 13.4.5 SPICRC register (SPI_CPOLY) (Not used in I S mode) ....
Page 11 AT32F403A/407 Series Reference Manual 14.2.3.5 TMR synchronization ............. 208 14.2.3.6 Debug mode ................. 211 14.2.4 TMRx registers ................211 14.2.4.1 Control register1 (TMRx_CTRL1) ........... 212 14.2.4.2 Control register2 (TMRx_CTRL2) ........... 213 14.2.4.3 Slave timer control register (TMRx_STCTRL) ......213 14.2.4.4 DMA/interrupt enable register (TMRx_IDEN) ......214 14.2.4.5 Interrupt status register (TMRx_ISTS) ........
Page 12 AT32F403A/407 Series Reference Manual 14.3.4.5 Software event register (TMRx_SW EVT) ......... 232 14.3.4.6 Channel mode register1 (TMRx_CM1) ........233 14.3.4.7 Channel control register (TMRx_CCTRL) ........ 235 14.3.4.8 Counter value (TMRx_CVAL) ..........235 14.3.4.9 Division value (TMRx_DIV) ............ 235 14.3.4.10 Period register (TMRx_PR) ..........236 14.3.4.11 Channel 1 data register (TMRx_C1DT) ........
Page 13 AT32F403A/407 Series Reference Manual 14.4.4.8 Channel mode register2 (TMRx_CM2) ........262 14.4.4.9 Channel control register (TMRx_CCTRL) ........ 263 14.4.4.10 TMR1 and TMR8 counter value (TMRx_CVAL) ....... 265 14.4.4.11 TMR1 and TMR8 division value (TMRx_DIV) ......265 14.4.4.12 TMR1 and TMR8 period register (TMRx_PR) ......265 14.4.4.13 TMR1 and TMR8 repetition period register (TMRx_RPR ) ..
Page 14 AT32F403A/407 Series Reference Manual 17.1 RTC introduction ................ 275 17.2 RTC main features ..............275 17.3 RTC structure ................275 17.4 RTC functional overview ............. 276 17.4.1 Configuring RTC registers............276 17.4.2 Reading RTC registers ............... 277 17.4.3 RTC interrupts ................277 17.5 RTC registers ................
Page 15 AT32F403A/407 Series Reference Manual 19.4.2.2 Trigger ................. 288 19.4.2.3 Sampling and conversion sequence ........289 19.4.3 Conversion sequence management ..........290 19.4.3.1 Sequence mode ..............290 19.4.3.2 Automatic preempted group conversion mode ......290 19.4.3.3 Repetition mode..............291 19.4.3.4 Partition mode ..............291 19.4.4 Data management ..............
Page 16 AT32F403A/407 Series Reference Manual 20.2 DAC main features ..............308 20.3 Design tips ................308 20.4 Function overview ..............309 20.4.1 Trigger events ................309 20.4.2 Noise/Triangular-wave generation ..........309 20.4.3 DAC data alignment ..............311 20.5 DAC registers ................311 20.5.1 DAC control register (DAC_CTRL) ..........
Page 17 AT32F403A/407 Series Reference Manual 21.6.1 General description ..............320 21.6.2 Operating modes ................ 321 21.6.3 Test modes ................321 21.6.4 Message filtering ................ 322 21.6.5 Message transmission ..............324 21.6.6 Message reception ..............326 21.6.7 Error management ..............326 21.7 CAN registers ................327 21.7.1 CAN control and status registers ..........
Page 18 AT32F403A/407 Series Reference Manual External memory controller ............342 22.1 XMC introduction ............... 342 22.2 XMC main features ..............342 22.3 XMC architecture ............... 343 22.3.1 Block diagram ................343 22.3.2 Address mapping ............... 344 22.4 NOR/PSRAM ................345 22.4.1 Operation mode ................. 345 22.4.2 Access mode ................
Page 19 AT32F403A/407 Series Reference Manual 23.1 SDIO introduction ..............375 23.2 SDIO main features ..............375 23.3 SDIO main features ..............377 23.3.1 Card functional description ............377 23.3.1.1 Card identification mode ............377 23.3.1.2 Data transfer mode ............... 378 23.3.1.3 Erase ................... 379 23.3.1.4 Protection management ............
Page 20 AT32F403A/407 Series Reference Manual 24.2 USBFS clock and pin configuration ..........404 24.2.1 USB clock configuration .............. 404 24.2.2 USB pin configuration ..............404 24.3 USBFS functional description ............404 24.3.1 USB initialization ................ 404 24.3.2 Endpoint configuration ..............405 24.3.3 USB buffer .................
Page 21 AT32F403A/407 Series Reference Manual 25.6.3 Control register 2 (ACC_CTRL2) ..........418 25.6.4 Compare value 1 (ACC_C1) ............418 25.6.5 Compare value 2 (ACC_C2) ............418 25.6.6 Compare value 3 (ACC_C3) ............419 Ethernet media access control (EMAC) ........420 26.1 EMAC introduction ..............420 26.1.1 EMAC structure ................
Page 22 AT32F403A/407 Series Reference Manual 26.3.17 Ethernet MAC address 2 high register (EMAC_MACA2H) ... 463 26.3.18 Ethernet MAC address 2 low register (EMAC_MACA2L) ..... 464 26.3.19 Ethernet MAC address 3 high register (EMAC_MACA3H) ... 464 26.3.20 Ethernet MAC address 3 low register (EMAC_MACA3L) ..... 465 26.3.21 Ethernet DMA bus mode register (EMAC_DMABM) ....
Page 23 AT32F403A/407 Series Reference Manual 26.3.42 Ethernet MMC received frames with CRC error counter register (EMAC_MMCRFCECR) ................. 479 26.3.43 Ethernet MMC received frames with alignment error counter register (EMAC_MMCRFAECNT) ............... 479 26.3.44 Ethernet MMC received good unicast frames counter register (EMAC_MMCRGUFCNT) ..............479 26.3.45 Ethernet PTP time stamp control register (EMAC_ PTPTSCTRL) .
Page 24 AT32F403A/407 Series Reference Manual List of figures Figure 1 - 1 AT32F403A/407 Series microcontrollers system architecture ..............36 ® Figure 1 - 2 Internal block diagram of Cortex -M4F ....................37 Figure 1 - 3 Comparison between bit-band region and its alias region: image A..........38 Figure 1 - 4 Comparison between bit-band region and its alias region: image B ..........38 Figure 1 - 5 Reset process ...........................43 Figure 1 - 6 Example of MSP and PC initialization ....................44...
Page 25 AT32F403A/407 Series Reference Manual Figure 11- 7 Transfer sequence of master receiver when N>2 ................ 147 Figure 11- 8 Transfer sequence of master receiver when N=2 ................ 148 Figure 11- 9 Transfer sequence of master receiver when N=1 ................ 150 Figure 12- 1 USART block diagram ........................
Page 26 AT32F403A/407 Series Reference Manual Figure 14- 17 Example of counter behavior in encoder interface mode (encoder mode C) ......204 Figure 14- 18 Input/output channel 1 main circuit .................... 204 Figure 14- 19 Channel 1 input stage ........................ 205 Figure 14- 20 Capture/compare channel output stage (channel 1 to 4) ............205 Figure 14- 21 C1ORAW toggles when counter value matches the C1DT value..........
Page 27 AT32F403A/407 Series Reference Manual Figure 14- 52 Counting in external clock mode A ..................... 243 Figure 14- 53 Block diagram of external clock mode B ..................243 Figure 14- 54 Counting in external clock mode B..................... 243 Figure 14- 55 Counter timing with prescaler value changing from 1 to 4 ............244 Figure 14- 56 Overflow event when PRBEN=0 ....................
Page 28 AT32F403A/407 Series Reference Manual Figure 19- 6 Repetition mode ........................... 291 Figure 19- 7 Partition mode ..........................291 Figure 19- 8 Data alignment ..........................292 Figure 19- 9 Block diagram of master/salve mode ................... 293 Figure 19- 10 Regular simultaneous mode ...................... 294 Figure 19- 11 Regular simultaneous mode .......................
Page 29 AT32F403A/407 Series Reference Manual Figure 22- 10 NOR/PSARM mode B write access ................... 355 Figure 22- 11 NOR/PSARM mode C read access .................... 356 Figure 22- 12 NOR/PSARM mode C write access ................... 357 Figure 22- 13 NOR/PSARM mode D read access ................... 358 Figure 22- 14 NOR/PSARM mode D write access ...................
Page 30 AT32F403A/407 Series Reference Manual Figure 26- 12 Transmit descriptors ........................436 Figure 26- 13 RXDMA descriptor structure ....................... 441 Figure 26- 14 Wakeup frame filter register ....................... 444 Figure 26- 15 System time update using the fine correction method ............... 447 Figure 26- 16 PTP trigger output to TMR2 ITR1 connection ................
Page 31 AT32F403A/407 Series Reference Manual List of tables Table 1- 1 Bit-band address mapping in SRAM ....................39 Table 1- 2 Bit-band address mapping in the peripheral area ................39 Table 1- 3 lists the vector table of AT32F403A/407/407A series.................40 Table 1- 4 List of abbreviations for registers ......................45 Table 1- 5 List of abbreviations for registers ......................45 Table 2- 1 Peripheral boundary address ......................49 Table 3- 1 PW register map and reset values ......................55...
Page 32 AT32F403A/407 Series Reference Manual Table 12- 4 USART interrupt request ........................ 168 Table 12- 5 USART register map and reset value .................... 169 Table 13- 1 Audio frequency precision using system clock ................186 Table 13- 2 SPI register map and reset value ....................190 Table 14- 1 TMR functional comparison ......................
Page 33 AT32F403A/407 Series Reference Manual Table 22- 5 Address translation between HADDR and external memory ............345 Table 22- 6 Data access width vs. external memory data width ............... 345 Table 22- 7 NOR/PSRAM parameter registers ....................346 Table 22- 8 Mode 1— SRAM/NOR Flash chip select control register (XMC_BK1CTRL) configuration ..346 Table 22- 9 Mode 1—...
Page 34 AT32F403A/407 Series Reference Manual Table 23- 8 I/O mode commands ........................385 Table 23- 9 Card lock commands ........................385 Table 23- 10 Application-specific commands ....................385 Table 23- 11 R1 response ..........................386 Table 23- 12 R2 response ..........................386 Table 23- 13 R3 response ..........................
Page 35: System Architecture
AT32F403A/407 Series Reference Manual 1 System architecture ® ® AT32F403A/407 series microcontrollers consist of 32-bit ARM Cortex -M4F processor core, multiple 16-bit and 32-bit timers, DMA controllers, RTC, communication interfaces such as SPI, I2C, USART/UART and SDIO, CANs, external memory controller (XMC), USB2.0 full-speed interfaces, Ethernet MAC, automatic clock calibration (ACC), 12-bit ADC, 12-bit DAC, programmable voltage monitor (PVM) and other peripherals.
Page 36: Figure 1 - 1 At32F403A/407 Series Microcontrollers System Architecture
AT32F403A/407 Series Reference Manual Figure 1 - 1 AT32F403A/407 Series microcontrollers system architecture HEXT 4~25MHz SWJTAG HICK 48MHz Max. 240MHz SDIO1/2 Cortex-M4 FCLK (Freq. Max. 240MHz) HCLK PCLK1 NVIC PCLK2 DMA1 7 Channel @VDD Flash DMA2 Flash POR/LVR Controller 7 Channel SRAM SRAM LDO 1.2V...
Page 37: System Overview
AT32F403A/407 Series Reference Manual 1.1 System overview 1.1.1 ARM Cortex -M4F processor Cortex ® -M4F processor is a low power consumption processor featuring low gate count, low interrupt latency, and low-cost debug. It supports DSP instruction set and FPU, and is applicable to deeply-embedded applications that require quicker response to interruption.
Page 38: Bit Band
AT32F403A/407 Series Reference Manual 1.1.2 Bit band Through bit-band operations, read and write access to a single bit can be performed using common load/store operations. The Cortex ® -M4F memory includes two bit-band regions: the least significant 1M byte of SRAM and the least significant 1M byte of peripherals. In addition to access to bit-band addresses, their respective bit-band alias area can be used to access to any bit of any address.
Page 39: Table 1- 1 Bit-Band Address Mapping In Sram
AT32F403A/407 Series Reference Manual number, then perform read-modify-write operation on bit level. The address ranges of two Flash memories supporting bit-band operations: Least significant 1 Mbyte in SRAM: 0x2000_0000~0x200F_FFFF Least significant 1 Mbyte in peripherals: 0x4000_0000~0x400F_FFFF For a bit in the SRAM bit-band region, if the byte address is A, the bit number is n (0<=n<=7), then the alias address where the bit is : AliasAddr = 0x2200_0000+ (A-0x2000_0000)*32+n*4 For a bit in the peripheral bit-band region, if the byte address is A, the bit number is n (0<=n<=7), then...
Page 40: Interrupt And Exception Vectors
AT32F403A/407 Series Reference Manual In addition, bit-band operations can also simplify jump process. When jump operation is based on a bit level, the previous steps are:  Read the whole register Mask the undesired bits   Compare and jump For now, you just need do: ...
Page 41 AT32F403A/407 Series Reference Manual Configur EXINT3 EXINT line3 interrupt 0x0000_0064 able Configur EXINT4 EXINT line4 interrupt 0x0000_0068 able Configur DMA1 channel1 DMA1 channel1 global interrupt 0x0000_006C able Configur DMA1 channel2 DMA1 channel2 global interrupt 0x0000_0070 able Configur DMA1 channel3 DMA1 channel3 global interrupt 0x0000_0074 able Configur...
Page 42 AT32F403A/407 Series Reference Manual Configur TMR8 break interrupt and TMR12 global TMR8_BRK_TMR12 0x0000_00EC able interrupt Configur TMR8 overflow interrupt and TMR13 TMR8_OVF_TMR13 0x0000_00F0 able global interrupt Configur TMR8_TRG_HALL_TMR TMR8 trigger and HALL interrupt and 0x0000_00F4 able TMR14 global interrupt Configur TMR8_CH TMR8 channel interrupt 0x0000_00F8...
Page 43: System Tick (Systick)
AT32F403A/407 Series Reference Manual Configur UART7 UART7 global interrupt 0x0000_0174 able Configur UART8 UART8 global interrupt 0x0000_0178 able Configur EMAC Ethernet global interrupt 0x0000_017C able Configur EMAC_WKUP Ethernet wakeup interrupt through EXINT 0x0000_0180 able Note: 1. USBFS module interrupt supports remap through the USBINTMAP bit in the CRM_INTMAP register. When USBINTMAP=0, use USBFS_H (19th) and USBFS_ L (20th) interrupts;...
Page 44: Figure 1 - 6 Example Of Msp And Pc Initialization
AT32F403A/407 Series Reference Manual Figure 1 - 6 Example of MSP and PC initialization Other Memory Initial SP Value 0x2000_8000 0x2000_8000 1st push data 0x2000_7FFC Stack grows 0x2000_7FF8 2nd push data downward Stack Memory 0x2000_7C00 Other Memory Code Boot Code 0x0000_0100 Other Exception Vectors...
Page 45: List Of Abbreviations For Registers
AT32F403A/407 Series Reference Manual 1.2 List of abbreviations for registers List of abbreviations for registers 1- 4 Table Register type Description Software can read and write to this bit. Software can only read this bit. Software can only write to the bit. Reading it returns its reset value. Software can read this bit.
Page 46 AT32F403A/407 Series Reference Manual Bit 31: 0 UID[95: 64] 0xXXXX XXXX UID for bit 95 to bit 64 Note: UID[95:88] is series ID, which is 0x07 for AT32F403A, and 0x8 for AT32F407. 2021.12.01 Page 46 Ver 2.02...
Page 47: Memory Resources
AT32F403A/407 Series Reference Manual 2 Memory resources 2.1 Internal memory address map Internal memory contains program memory (Flash), data memory (SRAM), peripheral registers and core registers. Their respective address mapping are shown in Figure 2-1. Figure 2- 1 AT32F403A/407address mapping 0xFFFF_FFFF Reserved 0xE010_0000...
Page 48 AT32F403A/407 Series Reference Manual Flash memory organization (1024K) The main memory is divided into bank 1 and bank 2, each with 512 Kbytes, including 256 pages per bank, and 2 Kbytes per page. External memory size can be up to 16 Mbytes, including 4096 pages, and 4 Kbytes per page. Block Name Address range...
Page 49: Sram Memory
AT32F403A/407 Series Reference Manual 2.3 SRAM memory The AT32F403A/407 series contain up to 96 KB of on-chip SRAM which starts at the address 0x2000_0000. It supports byte, half-word (16 bit) and word (32 bit) accesses. In addition, AT32F403A/407 also provide a special mode that supports dynamic switch between 96 KB and 224 KB. This is done by setting the EOPB0 bit.
Page 50 AT32F403A/407 Series Reference Manual 0x4001 2C00 - 0x4001 2FFF TMR1 timer 0x4001 2800 - 0x4001 2BFF ADC2 0x4001 2400 - 0x4001 27FF ADC1 0x4001 2000 - 0x4001 23FF Reserved 0x4001 1C00 - 0x4001 1FFF Reserved 0x4001 1800 - 0x4001 1BFF GPIO port E 0x4001 1400 - 0x4001 17FF GPIO port D...
Page 51 AT32F403A/407 Series Reference Manual 0x4000 0800 - 0x4000 0BFF TMR4 timer 0x4000 0400 - 0x4000 07FF TMR3 timer 0x4000 0000 - 0x4000 03FF TMR2 timer Note: 1.When USBBUFS = 0, USBFS buffer size is 512 bytes, its address is 0x 4000 6000 ~ 0x400063FF.
Page 52: Power Control (Pwc)
AT32F403A/407 Series Reference Manual 3 Power control (PWC) 3.1 Introduction For AT32F403A/407 series, its operating voltage supply is 2.6 V ~ 3.6 V, with a temperature range of - 40~+105 ℃. To reduce power consumption, this series provides three types of power saving modes, including Sleep, Deepsleep and Standby modes so as to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.The AT32F403A/407 series have three power domains─VDD/VDDA domain, 1.2 V domain and battery powered domain.
Page 53: Power Voltage Monitor (Pvm)
AT32F403A/407 Series Reference Manual Figure 3- 2 Power-on reset/Low voltage reset waveform hysteresis Temporization tRESTTEMPO Reset 3.4 Power voltage monitor (PVM) The PVM is used to monitor the power supply variations. It is enabled by setting the PVMEN bit in the power control register (PWC_CTRL), and the threshold value for voltage monitor is selected with the PVMSEL[2: 0].
Page 54: Power Saving Modes
AT32F403A/407 Series Reference Manual VDD/VDDA domain includes VDD domain and VDDA domain. The VDD domain contains I/O circuit, power-saving mode wakeup circuit, watchdog timer, power-on reset/low voltage reset (POR/LVR), LDO and all PAD circuits other than PC13, PC14 and PC15. The VDDA domain contains DAC/ADC (DA/AD converters), temperature sensor and so on.
Page 55: Pwc Registers
AT32F403A/407 Series Reference Manual entry/exit. Deepsleep Mode Deepsleep mode is entered by setting the SLEEPDEEP bit in the Cortex™-M4F system control register and clearing the LPSEL bit in the power control register before WFI or WFE instructions. The LDO status is selected by setting the VRSEL bit in the power control register (PWC_CTRL). When VRSEL=0, the LDO works in normal mode.
Page 56: Power Control Register (Pwc_Ctrl)
AT32F403A/407 Series Reference Manual 3.7.1 Power control register (PWC_CTRL) Name Reset value Type Description Kept at its default value. Bit 31: 9 Reserved 0x000000 resd Battery powered domain write enable 0: Disabled 1: Enabled Note: Bit 8 BPWEN If HEXT/128 is used as the RTC clock, the battery powered domain write operation is enabled.
Page 57: Power Control/Status Register (Pwc_Ctrlsts)
AT32F403A/407 Series Reference Manual 3.7.2 Power control/status register (PWC_CTRLSTS) Additional APB cycles are needed to read this register versus a standard APB read. Name Reset value Type Description resd Kept at its default value. Bit 31: 9 Reserved 0x000000 Standby wake-up pin enable 0: Disabled (this pin is used for general-purpose I/O) 1: Enabled (this pin is forced in input pull-down mode, and Bit 8...
Page 58: Clock And Reset Manage (Crm)
HICK clock is 48 MHz. Although it is less accurate, its startup time is shorter than the HEXT crystal oscillator. The HICK clock frequency of each device is calibrated by ARTERY for 1% accuracy (25°C) in factory. The factory calibration value is loaded in the HICKCAL[7: 0] bit of the clock control register. The RC oscillator speed may be affected by voltage or temperature variations.
Page 59: System Clock
AT32F403A/407 Series Reference Manual be trimmed using the HICKTRIM[5: 0] bit in the clock control register. The HICK clock signal is not released until it becomes stable.  PLL clock The HICK or HEXT clock can be used as an input clock source of PLL, and the input clock rangs from 2 M to 16 MHz.
Page 60: Clock Fail Detector
AT32F403A/407 Series Reference Manual 4.1.4 Clock fail detector The clock fail detector (CFD) is designed to respond to HEXT clock failure when the HEXT is used as the system clock ,directly or indirectly. If a failure is detected on the HEXT clock, a clock failure event is sent to the break input of TMR1 and TMR8 and an interrupt is generated.
Page 61: Battery Powered Domain Reset
AT32F403A/407 Series Reference Manual Figure 4- 2 System reset circuit Pulse generator (Min 20 µs) NRST CTRL NRST reset Filter WDT reset System WWDT reset reset CPU software reset Low-power management reset POR reset LVR reset standby return reset 4.2.2 Battery powered domain reset Battery powered domain has two specific reset sources: ...
Page 62: Clock Control Register (Crm_Ctrl)
AT32F403A/407 Series Reference Manual 4.3.1 Clock control register (CRM_CTRL) Name Reset value Type Description Kept at its default value. Bit 30: 26 Reserved 0x00 resd PLL clock stable This bit is set by hardware after PLL is ready. Bit 25 PLLSTBL 0: PLL clock is not ready.
Page 63: Clock Configuration Register (Crm_Cfg)
AT32F403A/407 Series Reference Manual High speed internal clock enable This bit is set and cleared by software. It can also be set by hardware when exiting Standby or Deepsleep mode. When a HEXT clock failure occurs. This bit can also be set. When Bit 0 HICKEN the HICK is used as the sytem clock, this bit cannot be...
Page 64 AT32F403A/407 Series Reference Manual HEXT division selection for PLL entry clock Bit 17 PLLHEXTDIV 0: HEXT is not divided 1: HEXT is divided according to the setting of HEXTDIV. PLL entry clock select Bit 16 PLLRCS 0: HICK clock divided (4MHz) to be PLL entry clock 1: HEXT clock is used as PLL entry clock ADC division PCLK division is used as ADC clock.
Page 65: Clock Interrupt Register (Crm_Clkint)
AT32F403A/407 Series Reference Manual System clock select 00: HICK Bit 1: 0 SCLKSEL 01: HEXT 10: PLL 11: Reserved, default value. 4.3.3 Clock interrupt register (CRM_CLKINT) Name Reset value Type Description resd Kept at its default value. Bit 31: 24 Reserved 0x00 Clock failure detection flag clear...
Page 66: Apb2 Peripheral Reset Register (Crm_Apb2Rst)
AT32F403A/407 Series Reference Manual LICK stable interrupt enable 0: Disabled Bit 8 LICKSTBLIEN 1: Enabled Clock Failure Detection flag This bit is set by hardware when the HEXT clock failure occurs. Bit 7 CFDF 0: No clock failure 1: Clock failure resd Kept at its default value.
Page 67 AT32F403A/407 Series Reference Manual TMR10 reset 0: No effect Bit 20 TMR10RST 1: Reset TMR9 reset 0: No effect Bit 19 TMR9RST 1: Reset Kept at its default value. Bit 18:16 Reserved resd ADC3 reset 0: No effect Bit 15 ADC3RST 1: Reset USART1 reset...
Page 68: Apb1 Peripheral Reset Register (Crm_Apb1Rst)
AT32F403A/407 Series Reference Manual 4.3.5 APB1 peripheral reset register (CRM_APB1RST) Name Reset value Type Description Kept at its default value. Bit 31:30 Reserved resd DAC reset 0: No effect Bit 29 DACRST 1: Reset PWC reset 0: No effect Bit 28 PWCRST 1: Reset Battery powered register reset...
Page 69: Apb Peripheral Clock Enable Register (Crm_Ahben)
AT32F403A/407 Series Reference Manual WWDT reset Bit 11 WWDTRST 0: No effect 1: Reset Kept at its default value. Bit 10: 9 Reserved resd TMR14 reset 0: No effect Bit 8 TMR14RST 1: Reset TMR13 reset 0: No effect Bit 7 TMR13RST 1: Reset TMR12 reset...
Page 70: Apb2 Peripheral Clock Enable Register (Crm_Ahb2En)
AT32F403A/407 Series Reference Manual SDIO1 clock enable 0: Disabled Bit 10 SDIO1EN 1: Enabled Kept at its default value. Bit 9 Reserved XMC clock enable Bit 8 XMCEN 0: Disabled 1: Enabled Kept at its default value. Bit 7 Reserved resd CRC clock enable Bit 6...
Page 71 AT32F403A/407 Series Reference Manual TMR10 clock enable 0: Disabled Bit 20 TMR10EN 1: Enabled TMR9 clock enable 0: Disabled Bit 19 TMR9EN 1: Enabled Kept at its default value. Bit 18: 16 Reserved resd ADC3 clock enable 0: Disabled Bit 15 ADC3EN 1: Enabled USART1 clock enable...
Page 72: Apb1 Peripheral Clock Enable Register (Crm_Ahb1En)
AT32F403A/407 Series Reference Manual 4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN) Name Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value. DAC clock enable 0: Disabled Bit 29 DACEN 1: Enabled Power control clock enable 0: Disabled Bit 28 PWCEN...
Page 73: Battery Powered Domain Control Register (Crm_Bpdc)
AT32F403A/407 Series Reference Manual WWDT clock enable Bit 11 WWDTEN 0: Disabled 1: Enabled Kept its default value. Bit 10：9 Reserved resd TMR14 clock enable 0: Disabled Bit 8 TMR14EN 1: Enabled。 TMR13 clock enable 0: Disabled Bit 7 TMR13EN 1: Enabled TMR12 clock enable 0: Disabled...
Page 74: Control/Status Register (Crm_Ctrlsts)
AT32F403A/407 Series Reference Manual RTC clock selection Once the RTC clock source is selected, it cannot be changed until the BPDRST bit is reset. 00: No clock Bit 9: 8 RTCSEL 01: LEXT 10: LICK 11: HEXT/128 Kept at its default value. Bit 7: 3 Reserved 0x00...
Page 75: Ahb Peripheral Reset Register (Crm_Ahbrst)
AT32F403A/407 Series Reference Manual Reset flag clear Cleared by writing 1 through software. Bit 24 RSTFC 0: No effect 1: Clear the reset flag. Kept at its default value. Bit 23：2 Reserved 0x000000 resd LICK stable 0: LICK is not ready. Bit 1 LICKSTBL 1: LICK is ready.
Page 76: Additional Register2 (Crm_Misc2)
AT32F403A/407 Series Reference Manual 4.3.13 Additional register2 (CRM_MISC2) Name Reset value Type Description Kept at its default value. Bit 31: 17 Reserved 0x0000 resd CLKOUT internally connected to timer 10 channel 1 0: Not connected Bit 16 CLK_TO_TMR 1: Connected Kept its default value.
Page 77: Interrupt Map Register (Crm_Intmap)
AT32F403A/407 Series Reference Manual 4.3.15 Interrupt map register (CRM_INTMAP) Name Reset value Type Description Kept at its default value. Bit 31: 1 Reserved 0x0000 0000 resd USBFS interrupt remap 0: USBFS uses the 19 USBFS_H and the 20 USBFS_L interrupt Bit 0 USBINTMAP 1: USBDEV uses the 73rd USBFS_MAPH and the 74th...
Page 78: Flash Memory Controller (Flash)
AT32F403A/407 Series Reference Manual 5 Flash memory controller (FLASH) 5.1 Flash memory introduction Flash memory is divided into four parts: main Flash memory, external memory, information block and Flash memory registers.  Main Flash memory is up to 1024 KB, including bank 1 and bank 2. Externa memory is up to 16 MB ...
Page 79: Figure 5- 1 Programming Process
AT32F403A/407 Series Reference Manual Main Flash memory (256 KB) has only bank 1, including 128 pages, 2 K per page. External memory size is up to 16 MB, including 4096 pages, 4 K per page. Table 5- 3 Flash memory architecture(256 K) Block Name Address range...
Page 80: Figure 5- 2 Reference Circuit For External Memory
AT32F403A/407 Series Reference Manual Figure 5- 2 Reference circuit for external memory SPIM_CS SPIM_IO1 SPIM_IO3 DO/DQ1 HOLD#/DQ3 SPIM_IO2 SPIM_SCK WP#/DQ2 SPIM_IO0 DI/DQ0 Table 5- 4 Instruction set supported by external memory FLASH_SELECT Instruction Code Description register config. Write Enable 0x06 0x1/0x2 Both 0x1 and 0x2 Flash must support 0x06 instruction Quad Page Program 0x32...
Page 81: Table 5- 5 User System Data Area
AT32F403A/407 Series Reference Manual Note: The update of the contents in the user system data area becomes effective only after a system reset. User system data area Table 5- 5 Address Description FAP[7: 0]: Flash memory access protection (Access protection enable/disable result is stored in the FLASH_USD[1] register ) [7: 0] 0xA5: Disabled...
Page 82: Flash Memory Operation
AT32F403A/407 Series Reference Manual [15: 8] nData2[7: 0]: Inverse code of Data2[7: 0] [23: 16] Data3[7: 0]: User data 3 [31: 24] nData3[7: 0]: Inverse code of Data3[7: 0] [7: 0] Data4[7: 0]: User data 4 [15: 8] nData4[7: 0]: Inverse code of Data4[7: 0] 0x1FFF_F818 [23: 16] Data5[7: 0]: User data 5...
Page 83: Erase Operation
AT32F403A/407 Series Reference Manual 5.2.2 Erase operation Erase operation must be done before programming. Flash memory erase includes mass erase and page erase. Page erase Any page in the Flash memory can be erased with page erase function. Below should be followed during page erase: ...
Page 84: Figure 5- 4 Process Of Flash Memory Mass Erase
AT32F403A/407 Series Reference Manual The following process is recommended: Check the OBF bit in the FLASH_STSx register to confirm that there is no other programming  operation in progress; Set the BANKERS and ERSTR bit in the FLASH_CTRLx register to enable mass erase; ...
Page 85: Programming Operation
AT32F403A/407 Series Reference Manual 5.2.3 Programming operation The Flash memory can be programmed with 32 bits, 16 bits or 8 bits at a time. The following process is recommended:  Check the OBF bit in the FLASH_STSx register to confirm that there is no other programming operation in progress;...
Page 86: Read Operation
AT32F403A/407 Series Reference Manual 5.2.4 Read operation Flash memory can be accessed through AHB bus of the CPU. 5.3 External memory operation External memory has the same operation method as that of Flash memory, including read, unlock, erase and programming except that the external memory only supports 32-bit and 16-bit operations, rather than 8 bits.
Page 87: Programming Operation
AT32F403A/407 Series Reference Manual Figure 5- 6 System data area erase process Start Check the OBF bit in FLASH_STS OBF = 0? Set USDERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ? Read ODF bit in FLASH_STS 5.4.3 Programming operation...
Page 88: Read Operation
AT32F403A/407 Series Reference Manual Figure 5- 7 System data area programming process Start Check the OBF bit in FLASH_STS OBF = 0? Set the USDPRGM bit = 1 in FLASH_CTRL Write word/half-word (32bits/16 bits) data Check the OBF bit in FLASH_STS OBF = 0? Read PRGMERR bit and ODF bit...
Page 89: Access Protection
AT32F403A/407 Series Reference Manual 5.5.1 Access protection When the contents in the nFAP and FAP byte are different from 0x5A and 0xA5, the Flash memory will activate access protection after a system reset. In this case, only the Flash program is allowed to read Flash memory data.
Page 90 AT32F403A/407 Series Reference Manual Advantages of security library: Security library is protected by codes so that solution providers can program core algorithm into this area; Security library cannot be read or deleted (including ISP/IAP/SWD) but only executed unless code defined by the solution provider is keyed in; The rest of the area can be used for secondary development by solution providers;...
Page 91: Flash Memory Registers
AT32F403A/407 Series Reference Manual 5.7 Flash memory registers Table 5-7 lists Flash register map and their reset values. These peripheral registers must be accessed by words (32 bits). Table 5- 7 Flash memory interface—Register map and reset value Register Offset Reset value FLASH_PSR 0x00...
Page 92: Flash User System Data Unlock Register (Flash_Usd_Unlock)
AT32F403A/407 Series Reference Manual 5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) Abbr. Reset value Type Description Bit 31: 0 USD_UKVAL 0xXXXX XXXX wo User system data Unlock key value Note: All these bits are write-only, and return 0 when being read. 5.7.4 Flash status register (FLASH_STS)
Page 93: Flash Address Register (Flash_Addr)
AT32F403A/407 Series Reference Manual User system data erase Bit 5 USDERS It indicates the user system data erase. User system data program Bit 4 USDPRGM It indicates the user system data program. Bank erase Bit 2 BANKERS It indicates bank erase operation. Page erase Bit 1 SECERS...
Page 94: Flash Status Register2 (Flash_Sts2)
AT32F403A/407 Series Reference Manual 5.7.10 Flash status register2 (FLASH_STS2) Only used in Flash memory bank 2. Register Reset value Type Description Bit 31: 6 Reserved 0x0000000 resd Kept at its default value Operation done flag This bit is set by hardware when Flash memory Bit 5 operations (program/erase) is completed.
Page 95: Flash Address Register2 (Flash_Addr2)
AT32F403A/407 Series Reference Manual 5.7.12 Flash address register2 (FLASH_ADDR2) Only used in Flash memory bank 2. Register Reset value Type Description Flash address Bit 31: 0 0x0000 0000 Select the address of the pages to be erased in page erase operation.
Page 96: Flash Address Register3 (Flash_Addr3)
AT32F403A/407 Series Reference Manual 1: Interrupt is enabled. Kept at its default value Bit 9,8 Reserved resd Operation lock This bit is set by default, indicating that Flash memory is protected against operations. This bit is cleared by Bit 7 OPLK hardware after unlock, indicating that erase/program operation to Flash memory is allowed.
Page 97: Flash Security Library Password Clear Register (Slib_Pwd_Clr)
AT32F403A/407 Series Reference Manual 1: Page 1 2: Page 2 … 511: Page 511 Security library data start page 0: Invalid page 1: Page 1 2: Page 2 Bit 21: 11 SLIB_DAT_SS 0x000 … 511: Page 511 0x7FF: No security library data area Security library start page 0: Page 0 1: Page 1...
Page 98: Security Library Password Setting Register (Slib_Set_Pwd)
AT32F403A/407 Series Reference Manual 5.7.23 Security library password setting register (SLIB_SET_PWD) Only used for Flash security library password setting. Register Reset value Type Description Security library password setting value Note: This register can be written only after unlocking security library lock. It is used to set up the startup Bit 31: 0 SLIB_PSET_VAL 0x0000 0000...
Page 99: Flash Crc Check Control Register (Flash_Crc_Ctrl)
AT32F403A/407 Series Reference Manual 5.7.26 Flash CRC check control register (FLASH_CRC_CTRL) Only used in main Flash memory. Register Reset value Type Description CRC start Set this bit to enable user code or security library code Bit 31 CRC_STRT CRC calibration. This bit is cleared automatically after the hardware enables CRC.
Page 100: General-Purpose I/Os (Gpios)
AT32F403A/407 Series Reference Manual 6 General-purpose I/Os (GPIOs) 6.1 Introduction AT32F403A/407 support up to 80 bidirectional I/O pins, which are grouped as five categories, namely PA, PB, PC, PD and PE. Each of the GPIO group provides up to 16 I/O pins that feature communication, control and data collection.
Page 101: Gpio Reset Status
AT32F403A/407 Series Reference Manual 6.2.2 GPIO reset status After power-on or system reset, all pins are configured as floating input mode except JATG-related pins. JTAG pin configuration are as follows:  PA15/JTDI, PA13/JTMS and PB4/JNTRST in pull-up input mode; PA14/JTCK in pull-down input mode; ...
Page 102: Gpio Registers
AT32F403A/407 Series Reference Manual 6.3 GPIO registers Table 6-1 lists GPIO register map and their reset values. These peripheral registers must be accessed by words (32 bits). Table 6- 1 GPIO register map and reset value s Register Offset Reset value GPIOx_CFGLR 0x00 0x4444 4444...
Page 103: Gpio Configuration Register High (Gpiox_Cfghr) (A
AT32F403A/407 Series Reference Manual 6.3.2 GPIO configuration register high (GPIOx_CFGHR) (A..E) Register Reset value Type Description GPIOx function configuration (y=8~15) In input mode (IOMCy[1：0]=00): 00: Analog mode Bit 31: 30 01: Floating input (reset state) Bit 27: 26 Bit 23: 22 10: Pull-up/pull-down input Bit 19: 18 11: Reserved...
Page 104: Gpio Set/Clear Register (Gpiox_Scr) (X=A..e
AT32F403A/407 Series Reference Manual 6.3.5 GPIO set/clear register (GPIOx_SCR) (x=A..E) Register Reset value Type Description GPIOx clear bit The corresponding ODT register bits are cleared by writing “1” to these bits. Writing 0 has no effect on the ODT register Bit 31: 16 IOCB 0x0000...
Page 105: Multiplex Function I/Os (Iomux)
AT32F403A/407 Series Reference Manual 7 Multiplex function I/Os (IOMUX) 7.1 Introduction AT32F403A/407 support up to 80 bi-directional I/O pins, which are grouped as five categories, namely PA, PB, PC, PD and PE. Each of the GPIO group provides up to 16 I/O pins that feature communication, control and data collection.
Page 106: Mux Input Configuration
AT32F403A/407 Series Reference Manual 7.2.2 MUX Input configuration When I/O ports are configured as multiplexed function input:  Get I/O pin state by reading input data registers  The pin be configured as floating input, pull-up or pull-down input  Schmitt-trigger input is activated.
Page 107: Hardware Preemption
AT32F403A/407 Series Reference Manual 7.2.5.1 Hardware preemption Certain pins are occupied by specific hardware functions regardless of the GPIO configuration. Table 7- 3 Hardware preemption Enable bit Description PWC_CTRLSTS[8] =1 Once enabled, PA0 pin acts as WKUP function of PWC. DAC_CTRL[2] =1 Once enabled, PA4 pin acts as DAC1 analog channel.
Page 108: Iomux Registers
AT32F403A/407 Series Reference Manual 7.3 IOMUX registers Table 7-5 shows IOMUX register map and their reset values, These peripheral registers must be accessed by words (32 bits). Table 7- 5 IOMUX register map and reset value Register Offset Reset value IOMUX_EVTOUT 0x00 0x0000 0000...
Page 109: Iomux Remap Register (Iomux_Remap)
AT32F403A/407 Series Reference Manual 7.3.2 IOMUX remap register (IOMUX_REMAP) Register Reset value Type Description SPI1 IO multiplexing Bit 31 SPI1_MUX Refer to bit 0 for more details. EMAC PTP PPS IO mutiplexing It indicates whether PPS_PTS is connected to PB5. 0: PTP_PPS is not connected to PB5 pin.
Page 110 AT32F403A/407 Series Reference Manual to EXINT11 1: ADC2 external trigger ordinary conversion is connected to TMR8_TRGO ADC2 external trigger preempted conversion mutiplexing Select external trigger input for ADC2 preempted conversion. Bit 19 ADC2_ETP_MUX 0: ADC2 external trigger preempted conversion is connected to EXINT15.
Page 111: Iomux External Interrupt Configuration Register1
AT32F403A/407 Series Reference Manual 01: CH1/EXT/PA15, CH2/PB3, CH3/PA2 and CH4/PA3 10: CH1/EXT/PA0, CH2/PA1, CH3/PB10 and CH4/PB11 11: CH1/EXT/PA15, CH2/PB3, CH3/PB10 and CH4/PB11 TMR1 IO multiplexing Select IO multiplexing for TMR1. 00: EXT/PA12, CH1/PA8, CH2/PA9 and CH3/PA10 CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 Bit 7: 6 TMR1_MUX...
Page 112: Iomux External Interrupt Configuration Register2
AT32F403A/407 Series Reference Manual 0000: GPIOA pin2 0001: GPIOB pin2 0010: GPIOC pin2 0011: GPIOD pin2 0100: GPIOE pin2 Others: Reserved. EXINT1 input source configuration Select the input source for EXINT1 external interrupt. 0000: GPIOA pin1 0001: GPIOB pin1 Bit 7: 4 EXINT1 0x0000 0010: GPIOC pin1...
Page 113: Iomux External Interrupt Configuration Register3
AT32F403A/407 Series Reference Manual 0000: GPIOA pin4 0001: GPIOB pin4 0010: GPIOC pin4 0011: GPIOD pin4 0100: GPIOE pin4 Others: Reserved. 7.3.5 IOMUX external interrupt configuration register3 (IOMUX_EXINTC3) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. EXINT11 input source configuration Select the input source for EXINT11 external interrupt.
Page 114: Iomux Remap Register2 (Iomux_Remap2)
AT32F403A/407 Series Reference Manual 0011: GPIOD pin15 0100: GPIOE pin15 Others: Reserved. EXINT14 input source configuration Select the input source for EXINT14 external interrupt. 0000: GPIOA pin14 0001: GPIOB pin14 Bit 11: 8 EXINT14 0x0000 0010: GPIOC pin144 0011: GPIOD pin14 0100: GPIOE pin14 Others: Reserved.
Page 115: Iomux Remap Register3 (Iomux_Remap3)
AT32F403A/407 Series Reference Manual Kept at its default value. Bit 9: 6 Reserved resd TMR9_MUX: TMR9 IO multiplexing Select IO multiplexing for TMR9. Bit 5 TMR9_MUX 0: CH1/PA2, CH2/PA3 1: CH1/PE5, CH2/PE6 Bit 4: 0 Reserved 0x00 resd Kept at its default value. 7.3.8 IOMUX remap register3 (IOMUX_REMAP3) Register...
Page 116: Iomux Remap Register5 (Iomux_Remap5)
AT32F403A/407 Series Reference Manual Others: Unused. 7.3.10 IOMUX remap register5 (IOMUX_REMAP5) Register Reset value Type Description SPI4 IO general multiplexing Select IO multiplexing for SPI4. 0000: CS/PE4 SCK/PE2 MISO/PE5 MOSI/PE6 MCK/PC8 0001: CS/PE12 SCK/PE11 MISO/PE13 MOSI/PE14 MCK/PC8 Bit 31: 28 SPI4_GMUX 0010: CS/PB6...
Page 117: Iomux Remap Register6 (Iomux_Remap6)
AT32F403A/407 Series Reference Manual Select IO multiplexing for USART5. 0000: TX/PC12 RX/PD12 0001: TX/PB9 RX/PB8 Others: Unused 7.3.11 IOMUX remap register6 (IOMUX_REMAP6) Register Reset value Type Description IO general multiplexing Select IO multiplexing for UART4. 0000: TX/PC10 RX/PC11 Bit 31: 28 UART4_GMUX 0001: TX/PA0 RX/PA1 Others: Unused...
Page 118: Iomux Remap Register7 (Iomux_Remap7)
AT32F403A/407 Series Reference Manual 7.3.12 IOMUX remap register7 (IOMUX_REMAP7) Register Reset value Type Description Bit 31: 28 Reserved resd Kept at its default value. XMC NADV IO general multiplexing Select whether to use XMC_NADV signal. 0: XMC_NADV is connected to the corresponding pin (by Bit 27 XMC_NADV_GMUX default)
Page 119: Iomux Remap Register8 (Iomux_Remap8)
AT32F403A/407 Series Reference Manual ADC1 external trigger regular conversion general multiplexing Select the input source for ADC1 external trigger regular conversion. Bit 5 ADC1_ETO_GMUX 0: ADC1 external trigger regular conversion connected to EXINT11 1: ADC1 external trigger regular conversion connected to TMR8_TRGO ADC1 External trigger preempted conversion general multiplexing Select the input source for ADC1 External trigger...
Page 120 AT32F403A/407 Series Reference Manual RX_DV/CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1 RX_DV/CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12 Note: This bit is applied to only AT32F407. Bit 15: 0 Reserved 0x0000 resd Kept at its default value. 2021.12.01 Page 120 Ver 2.02...
Page 121: External Interrupt/Event Controller (Exint)
AT32F403A/407 Series Reference Manual 8 External interrupt/Event controller (EXINT) 8.1 EXINT introduction EXINT consists of 20 interrupt lines EXINT_LINE[19:0], each of which can generate an interrupt or event by edge detection trigger or software trigger. EXINT can enable or disable an interrupt or event independenttly through software configuration, and utilizes different edge detection modes (rising edge, falling edge or both edges) as well as trigger modes (edge detection, software trigger or both tirggers) to respond to the trigger source in order to generate an interrupt or event.
Page 122: Exint Registers
AT32F403A/407 Series Reference Manual  Generate software trigger by setting EXINT_SWTRG register (This is applied to only software trigger interrupt) Interrupt clear procedure Writing “1” to the EXINT_INTSTS register to clear the interrupts generated, and the  corresponding bits in the EXINT_SWTRG register. 8.3 EXINT registers These peripheral registers must be accessed by words (32 bits).
Page 123: Software Trigger Register (Exint_ Swtrg)
AT32F403A/407 Series Reference Manual interrupt and event on line x. 0: Falling trigger on line x is disabled. 1: Falling trigger on line x is enabled. Note: Bit 19 is applied to only AT32F407 and is reserved otherwise. 8.3.5 Software trigger register (EXINT_ SWTRG) Register Reset value Type...
Page 124: Dma Controller (Dma)
AT32F403A/407 Series Reference Manual 9 DMA controller (DMA) 9.1 Introduction Direct memory access (DMA) controller is designed for 32-bit MCU applications with the aim of enhancing system performance and reducing the generation of interrupts. There are two DMA controllers in the microcontroller. Each controller contains 7 DMA channels. Each channel manages memory access requests from one or more peripherals.
Page 125: Handshake Mechanism
AT32F403A/407 Series Reference Manual 2. Set the memory address in the DMA_CxMADDR register The initial memory address for data transfer remains unchanged during transmission. 3. Configure the amount of data to be transferred in the DMA_CxDTCNT register Programmable data transfer size is up to 65535. This value is decremented after each data transfer. 4.
Page 126: Programmable Data Transfer Width
AT32F403A/407 Series Reference Manual 9.3.4 Programmable data transfer width Transfer width of the source data and destination data is programmable through the PWIDTH and MWIDTH bits in the DMA_CxCTRL register. When PWIDTH is not equal to MWIDTH, it can be aligned according to the settings of PWIDTH/ MWIDTH.
Page 127: Errors
AT32F403A/407 Series Reference Manual 9.3.5 Errors Table 9- 1 DMA error event Error event Transfer error AHB response error occurred during DMA read/write access 9.3.6 Interrupts An interrupt can be generated on a DMA half-transfer, transfer complete and transfer error. Each channel has its specific interrupt flag, clear and enable bits, as shown in the table below.
Page 128: Flexible Dma Request Mapping
AT32F403A/407 Series Reference Manual 9.3.8 Flexible DMA request mapping In flexible request mapping mode (DMA_FLEX_EN = 1), the request source of each channel is programmed by CHx_SRC [x=1~7]. For example, to specify DMA channel 1 as USART3_TX, and channel 3 as USART3_RX, and others are unused, then it is necessary that DMA_FLEX_EN=1, CH1_SRC=30, CH3_SRC=29 and CH[2/4/5/6/7]_SRC=0.
Page 129: Dma Registers
AT32F403A/407 Series Reference Manual reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Note: The request mapping mode must be identical for DMA1 and DMA2 (DMA_FLEX_EN must be set either 1 or 0 for both DMA 1 and DMA 2) 9.4 DMA registers...
Page 130: Dma Interrupt Status Register (Dma_Sts)
AT32F403A/407 Series Reference Manual DMA_C7CTRL 0x80 0x0000 0000 DMA_C7DTCNT 0x84 0x0000 0000 DMA_C7PADDR 0x88 0x0000 0000 DMA_C7MADDR 0x8C 0x0000 0000 DMA_SRC_SEL0 0xA0 0x0000 0000 DMA_SRC_SEL1 0xA4 0x0000 0000 Note: In the following registers, all bits related to channel 6 and channel 7 are not relevant for DMA 2 fixed request mapping since it has only 5 channels.
Page 131 AT32F403A/407 Series Reference Manual Channel 5 global event flag 0: No transfer error, half transfer or transfer complete event Bit 16 occurred. 1: Transfer error, half transfer or transfer complete event Channel 4 data transfer error event flag 0: No transfer error occurred. Bit 15 DTERRF4 1: Transfer error occurred.
Page 132: Dma Interrupt Flag Clear Register (Dma_Clr)
AT32F403A/407 Series Reference Manual Channel 1 global event flag 0: No transfer error, half transfer or transfer complete event Bit 0 occurred. 1: Transfer error, half transfer or transfer complete event 9.4.2 DMA interrupt flag clear register (DMA_CLR) Register Reset value Type Description 31: 28...
Page 133: Dma Channelx Configuration Register (Dma_Cxctrl) (X = 1
AT32F403A/407 Series Reference Manual Channel 4 transfer complete flag clear Bit 13 FDTFC4 rw1c 0: No effect 1: Clear the FDTF4 flag in the DMA_STS register Channel 4 global interrupt flag clear 0: No effect Bit 12 GFC4 rw1c 1: Clear the DTERRF4, HDTF4, FDTF4 and GF4 flag in the DMA_STS register Channel 7 data transfer error flag clear 0: No effect...
Page 134: Dma Channelx Number Of Data Register (Dma_Cxdtcnt)
AT32F403A/407 Series Reference Manual Channel priority level 00: Low Bit 13: 12 CHPL 01: Medium 10: High 11: Very high Memory data bit width 00: 8 bits Bit 11: 10 MWIDTH 01: 16 bits 10: 32 bits 11: Reserved Peripheral data bit width 00: 8 bits Bit 9: 8 PWIDTH...
Page 135: Dma Channelx Peripheral Address Register (Dma_Cxpaddr)
AT32F403A/407 Series Reference Manual 9.4.5 DMA channelx peripheral address register (DMA_CxPADDR) (x = 1… 7) Register Reset value Type Description Peripheral base address Base address of peripheral data register is the source or destination of data transfer. Bit 31: 0 PADDR 0x0000 0000 Note: The register can only be written when the CHEN bit...
Page 136 AT32F403A/407 Series Reference Manual CH5 source select When DMA_FLEX_EN=1, CH5_SRC selects channel Bit 7: 0 CH5_SRC 0x00 source, please refer to 9.3.8 Flexible DMA request mapping 2021.12.01 Page 136 Ver 2.02...
Page 137: Crc Calculation Unit (Crc)
AT32F403A/407 Series Reference Manual 10 CRC calculation unit (CRC) 10.1 CRC introduction The Cyclic Redundancy Check (CRC) is an independent peripheral with CRC check feature. It follows CRC32 standard. The CRC_CTRL register is used to select input data reverse (word, REVOD=1) or output data reverse (byte, REVID=01;...
Page 138: Control Register (Crc_Ctrl)
AT32F403A/407 Series Reference Manual Reset CRC calculation unit Set by software. Cleared by hardware. To reset CRC calculation unit, the data register is set as 0xFFFF FFFF. Bit 0 0: No effect 1: Reset 10.2.3 Control register (CRC_CTRL) Register Reset value Type Description Bit 31: 8...
Page 139: C Interface
AT32F403A/407 Series Reference Manual 11 I C interface 11.1 I C introduction I2C (inter-integrated circuit) bus interface manages the communication between the microcontroller and serial I C bus. It supports master and slave modes, with up to 400 kbit/s of communication speed. 11.2 I C main features ...
Page 140: I 2 C Interface
AT32F403A/407 Series Reference Manual 11.4 I C interface Figure 11-2 shows the block diagram of I C function Figure 11- 2 I2C function block diagram Comparator Data Control Shift Register APB Interface Control register Data Clock OADDR Register Control Status I2C_DMA_req_tx register Clock...
Page 141 AT32F403A/407 Series Reference Manual  In 10-bit mode ― Only match OADDR1 Support special slave address:  Broadcast call address (0b0000000x): This address is enabled when GCAEN=1.  SMBus device default address (0b1100001x): This address is enabled for SMBus address resolution protocol in SMBus device mode.
Page 142: C Slave Communication Flow
AT32F403A/407 Series Reference Manual 11.4.1 I C slave communication flow Initialization Enable I C peripheral clock, and configure the clock-related bits in the I2C_CTRL2 register for a correct timing, and then wait for I C master to send a Start condition. Transmitter 11-3 Figure...
Page 143: Figure 11- 4 Transfer Sequence Of Slave Receiver
AT32F403A/407 Series Reference Manual EV2: When the data is written to DT register, it is directly moved to the shift register, and SCL bus is released. The TDBE is still set 1 at this time. EV3: At this point, the DT register is empty but the shift register is not. Writing to the DT register will clear the TDBE bit.
Page 144: C Master Communication Flow
AT32F403A/407 Series Reference Manual EV3: After receiving the Stop condition from the master, STOPF=1. Read STS1 and then write to CTRL1 register will clear the event. End of communication. 11.4.2 I C master communication flow Initialization Porgram input clock to generate correct timing through the CLKFREQ bit in the I2C_CTRL2 register;...
Page 145: Figure 11- 5 Transfer Sequence Of Master Transmitter
AT32F403A/407 Series Reference Manual Master transmitter Figure 11- 5 Transfer sequence of master transmitter Example : I2C Master transfer N bytes to I2C Slave . 7-bit address Address Data1 Data2 DataN Stretch Stretch TDBE 10-bit address Address Head Address Stretch Stretch SCL Stretch Data1...
Page 146: Figure 11- 6 Transfer Sequence Of Master Receiver
AT32F403A/407 Series Reference Manual will clear the TDBE bit. The TDBE bit is set only after the second-to-last byte is sent. EV5: TDC=1 indicates that the byte transmission is complete. The master sends Stop condition (STOPF=1). The TDBE bit and TDC bit is cleared by hardware. End of communication.
Page 147: Figure 11- 7 Transfer Sequence Of Master Receiver When N>2
AT32F403A/407 Series Reference Manual EV5: 10-bit address head sequence is sent. Read STS1 and write to DT register can clear the ADDRHF bit. EV2: Address is matched successfully (ADDR7F=1). Read STS1 and then STS2 will clear the ADDR7F bit, and the master re-send Start condition (GENSTART=1). EV1: Start condition is ready (STARTF=1).
Page 148: Figure 11- 8 Transfer Sequence Of Master Receiver When N=2
AT32F403A/407 Series Reference Manual End of communication. 10-bit address mode:  Generate Start condition (GENSTART=1) EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register. EV5: 10-bit address head sequence is sent. Read STS1 and write to DT register can clear the ADDRHF bit.
Page 149 AT32F403A/407 Series Reference Manual  7-bit address mode: Set MACKCTRL=1 in the I2C_CTRL1 register Generate Start condition (GENSTART=1) EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register. EV2: Address is matched successfully (ADDR7F=1). Clear the ACKEN bit and read STS1 before reading STS2 and clearing ADDR7F bit, the master enters receive state at this time.
Page 150: Figure 11- 9 Transfer Sequence Of Master Receiver When N=1
AT32F403A/407 Series Reference Manual Figure 11- 9 Transfer sequence of master receiver when N=1 Example : I2C Master receive 1 bytes from I2C Slave . 7-bit address Address Data1 Stretch Stretch RDBF 10-bit address Address Head Address Head Address SCL Stretch Stretch SCL Stretch Stretch...
Page 151: Utilize Dma For Data Transfer
AT32F403A/407 Series Reference Manual 11.4.3 Utilize DMA for data transfer C data transfer can be done using DMA controller. An interrupt is generated by enabling the transfer complete interrupt bit. The DATAIEN bit in the I2C_CTRL2 register must be set 0 when using DMA for data transfer.
Page 152 AT32F403A/407 Series Reference Manual another, or even keeping STOP and other parameter monitor. There is no limit for I SMBus transmission speed ranges from 10 kHz to 100 kHz. In contrast,I2C has no minimum requirement, and its maximum speed varies from one mode to another, namely, 100 kHz in standard mode and 400 kHz in fast mode.
Page 153: C Interrupt Requests
AT32F403A/407 Series Reference Manual C(x) = x + x + 1 PEC calculation is enabled when PECEN=1 to check address and data. It becomes invalid when the arbitration is lost. PEC transmission:  Common mode: Set PECTRA=1 after the last TDBE event so that PEC is transferred after the last transmitted byte.
Page 154: I 2 C Registers
AT32F403A/407 Series Reference Manual 11.5 I C registers These peripheral registers must be accessed by half-word (16 bits) or word (32 bits). Table 11- 1 I C register map and reset value Register Offset Reset value I2C_CTRL1 0x00 0x0000 I2C_CTRL2 0x04 0x0000 I2C_OADDR1...
Page 155: Control Register2 (I2C_Ctrl2)
AT32F403A/407 Series Reference Manual The salve releases the SCL and SDA lines when this bit is set in slave mode. Generate start condition This bit is set or cleared by software. It is cleared when a Start condition is sent. Bit 8 GENSTART 0: No Start condition is generated.
Page 156: Own Address Register1 (I2C_Oaddr1)
AT32F403A/407 Series Reference Manual 0: Disabled 1: Enabled An interrupt is generated in the following conditions: – STARTF = 1 (Master mode) – ADDR7F = 1 (Master/slave mode) – ADDRHF= 1 (Master mode) – STOPF = 1 (Slave mode) – TDC = 1, but no TDBE or RDBF event –...
Page 157: Status Register1 (I2C_Sts1)
AT32F403A/407 Series Reference Manual transferred. Transmitter mode: Data transfer starts automatically when a byte is written to the DT register. Once the transfer starts (TDE=1), I C will keep a continuous data transfer flow if the next data to be transferred is written to the DT register in a timely manner.
Page 158 AT32F403A/407 Series Reference Manual 1: Arbitration lost is detected. This bit is cleared by software, or by hardware when I2CEN=0. On ARLOST even, the I C interface switches to slave mode automatically. Bus error flag 0: No Bus error occurs. 1: Bus error occurs.
Page 159: Status Register2 (I2C_Sts2)
AT32F403A/407 Series Reference Manual The TDC is set under both conditions. 0~7 bit address match flag 0: Address is not sent in host ode or received in slave mode 1: Address is sent in host mode or address is received in Bit 1 ADDR7F slave mode.
Page 160: Clock Control Register (I2C_ Clkctrl)
AT32F403A/407 Series Reference Manual 11.5.8 Clock control register (I2C_ CLKCTRL) Register Reset value Type Description Speed mode selection 0: Standard mode (up to 100 kHz) Bit 15 SPEEDMODE 1: Fast mode (up to 400 kHz) In fast mode, an accurate 400kHz clock is generated when the I C clock frequency is an integer multiple of 10MHz.
Page 161: Universal Synchronous/Asynchronous Receiver/Transmitter (Usart)
AT32F403A/407 Series Reference Manual 12 Universal synchronous/asynchronous receiver/transmitter (USART) 12.1 USART introduction The universal synchronous/asynchronous receiver/transmitter (USART) serves an interface for communication by means of various configuration and peripherals with different data formats. It supports asynchronous full-duplex and half-duplex as well as synchronous transfer. With a programmable baud rate generator, USART offers up to 7.5MBits/s of baud rate by setting the system frequency and frequency divider, which is also convenient for users to configure the required communication frequency.
Page 162 AT32F403A/407 Series Reference Manual ─ NRZ standard format (Mark/Space) ─ LIN (Local Interconnection Network): LIN master with break generation capability and LIN slave with break detection capability ─ IrDA SIR: Support 3/16 bit duration in normal mode, and configurable duration in infrared low- power mode ─Asynchronous SmartCard protocol defined in ISO7816-3 standard: Support 0.5 or 1.5 stop bits in Smartcard mode...
Page 163: Full-Duplex/Half-Duplex Selector
AT32F403A/407 Series Reference Manual 12.2 Full-duplex/half-duplex selector The full-duplex and half-duplex selector enables USART to perform data exchanges with peripherals in full-duplex or half-duplex mode, which is achieved by setting the corresponding registers. In two-wire unindirectional full-duplex mode (by default), TX pin is used for data output, while the RX pin is used for data input.
Page 164: Usart Frame Format And Configuration
AT32F403A/407 Series Reference Manual 12.4 USART frame format and configuration USART data frame consists of start bit, data bit and stop bit, with the last data bit being as a parity bit. USART idle frame size is equal to that of the data frame under current configuration, but all bits are 1. USART break frame size is the current data frame size plus its stop bit.
Page 165: Baud Rate Generation
AT32F403A/407 Series Reference Manual 12.6 Baud rate generation 12.6.1 Introduction USART baud rate generator uses an internal counter based on PCLK. The DIV (USART_BAUDR [15:0] register) represents the overflow value of the counter. Each time the counter is full, it denotes one-bit data.
Page 166: Transmitter
AT32F403A/407 Series Reference Manual 12.7 Transmitter 12.7.1 Transmitter introduction USART transmitter has its individual TEN control bit. The transmitter and receiver share the same baud rate that is programmable. There is a transmit data buffer (TDR) and a transmit shift register in the USART.
Page 167: Receiver Configuration
AT32F403A/407 Series Reference Manual 12.8.2 Receiver configuration Configuration procedure: 1. USART enalbe: UEN bit is set. 2. Full-duplex/half-duplex configuration: Refer to full-duplex/half-duplex selector for more information. 3. Mode configuration: Refer to mode selector for more information. 4. Frame format configuration: Refer to frame format for more information. 5.
Page 168: Start Bit And Noise Detection
AT32F403A/407 Series Reference Manual If RDBF=1, it indicates that the last valid data is still stored in the receive data buffer, and can be read. If RDBF=0, it indicates that the last valid data in the receive data buffer has already been read.
Page 169: I/O Pin Control
AT32F403A/407 Series Reference Manual Transmit data complete TDCIEN Receive data buffer full RDBF RDBFIEN Receiver overflow error ROERR Idle flag IDLEF IDLEIEN Parity error PERR PERRIEN Break frame flag BFIEN （） Noise error, overflow error or framing error NERR or ROERR or FERR ERRIEN Figure 12- 2 USART interrupt map diagram TDBE...
Page 170 AT32F403A/407 Series Reference Manual changes. It is cleared by software. 0: No change on the CTS status line 1: A change occurs on the CTS status line. Break frame flag This bit is set by hardware when a break frame is detected. It is cleared by software.
Page 171: Data Register (Usart_Dt)
AT32F403A/407 Series Reference Manual Parity error This bit is set by hardware when parity error occurs. It is cleared by software. USART_STS register followed by a Bit 0 PERR USART_DT read operation) 0: No parity error occurs. 1: Parity error occurs. 12.11.2 Data register (USART_DT) Register Reset value...
Page 172: Control Register2 (Usart_Ctrl2)
AT32F403A/407 Series Reference Manual 0: Interrupt is disabled. 1: Interrupt is enabled. TDC interrupt enable 0: Interrupt is disabled. Bit 6 TDCIEN 1: Interrupt is enabled. RDBF interrupt enable 0: Interrupt is disabled. Bit 5 RDBFIEN 1: Interrupt is enabled. IDLE interrupt enable 0: Interrupt is disabled.
Page 173: Control Register3 (Usart_Ctrl3)
AT32F403A/407 Series Reference Manual In synchronous mode or Smartcard mode, this bit is used to select the polarity of the clock output on the clock pin in idle state. 0: Clock output low 1: Clock output high Clock phase This bit is used to select the phase of the clock output on the clock pin in synchronous mode or Smartcard mode.
Page 174: Guard Time And Divider Register (Gdiv)
AT32F403A/407 Series Reference Manual This bit is used to send NACK when parity error occurs. 0: NACK is disabled when parity error occurs. 1: NACK is enabled when parity error occurs. Single-wire bidirectional half-duplex enable 0: Single-wire bidirectional half-duplex is disabled. Bit 3 SLBEN 1: Single-wire bidirectional half-duplex is enabled.
Page 175: Serial Peripheral Interface (Spi)
AT32F403A/407 Series Reference Manual 13 Serial peripheral interface (SPI) 13.1 SPI introduction The SPI interace supports either the SPI protocol or the I S protocoal, depending on software configuration. This chapter gives an introduction of the main features and congiruation procedure of SPI used as SPI or I 13.2 Function overview 13.2.1 SPI description...
Page 176: Full-Duplex/Half-Duplex Selector
AT32F403A/407 Series Reference Manual  Programmable data transfer order (MSB-first or LSB-first) Programmable error interrupt flags (receiver overflow error, master mode error and CRC error)   Programmable transmit data buffer empty interrupt and receive data buffer full interrupt  Support transmission and reception using DMA ...
Page 177: Figure 13- 4 Single-Wire Unidirectional Receive Only In Spi Slave Mode
AT32F403A/407 Series Reference Manual Figure 13- 4 Single-wire unidirectional receive only in SPI slave mode SPI master SPI slave MISO MISO MOSI MOSI In master mode, it is necessary to wait until the second-to-last RDBF bit is set and then another SPI_CPK period before disabling the SPI.
Page 178: Chip Select Controller
AT32F403A/407 Series Reference Manual 13.2.3 Chip select controller The Chip select controller (CS) is used to enable hardware or software control for chip select signals through software configuration. This controller is used to select master/slave device in multi-processor mode, and to avoid conflicts on the data lines by enabling the SCK signal output followed by CS signal. The hardware and software configuration procedure is detailed as follows, along with their respective input/output in master and slave mode.
Page 179: Dma Transfer
AT32F403A/407 Series Reference Manual  CRC calculation polynominal is configured by setting the SPI_CPOLY register. CRC enable: The CRC calculation is enabled by setting the CCEN bit. This operation will reset  the SPI_RCRC and SPI_TCRC registers. Select if or when the NTC bit is set, depending on DMA or CPU data register. See the following ...
Page 180: Transmitter
AT32F403A/407 Series Reference Manual  Configure the destination of DMA transfer: Configure the memory address as the destination of DMA transfer in the DMA control register. Data will be loaded from the SPI_DT register to the programmed destination after reception request is received by DMA. ...
Page 181: Interrupt
AT32F403A/407 Series Reference Manual RDBF is set, meaning that there are some data to be read in the SPI_DT register. An interrupt is generated if the RDBFIE bit is set. When the next received data is ready to be moved to the SPI_DT register, if the previous received data is still not read (RDBF=1), then the data overflow occurs.
Page 182: Precautions
AT32F403A/407 Series Reference Manual 13.2.11 Precautions The software is required to read the DT register in order to get CRC value at the end of CRC reception. 13.3 I S functional description 13.3.1 I S introduction The I2S can be configured by software as master repection/transmission, and slave reception/transmission, supporting foure kinds of audio protocols including Philips standard, MSB- aligned standard, LSB-aligned standard and PCM standard, respectively.
Page 183: I 2 S Full-Duplex
AT32F403A/407 Series Reference Manual ─ LSB-aligned standard (right-aligned) ─ PCM standard (long or short frame) S full-duplex   DMA transfer  Main peripheral clock with a fixed frequence of 256x Fs (audio sampling frequency) 13.3.2 I S full-duplex Two extra I2S modules (I2S2EXT and I2S3EXT) are used to support I2S full-duplex mode. Combine the I2S2 with the I2S2EXT, and I2S3 with I2S3EXT to support full-duplex mode.
Page 184: Audio Protocol Selector
AT32F403A/407 Series Reference Manual Figure 13- 10 I S slave device reception I2S master I2S slave Master device transmission: Set the I2SMSEL bit, and OPERSEL[1:0]=10, the I S will work in master device transmission mode. Figure 13- 11 I S master device transmission I2S master I2S slave Master device reception:...
Page 185: I2S_Clk Controller
AT32F403A/407 Series Reference Manual bits and channel bits through software configuration. Meanwhile, the audio protocol selector manages the WS controller, output or detect the WS siganal that meets the protocol requirements.  Select audio protocol by seeting the STDSEL bit STDSLE=00: Philips standard STDSLE=01: MSB-aligned standard (left-aligned) STDSLE=10: LSB-aligned standard (right-aligned)
Page 186: Figure 13- 13 Ck & Mck Source In Master Mode
AT32F403A/407 Series Reference Manual detailed as follows: When used as I2S master, the SPI can provide communication clock (CK) and main peripheral clock (MCK) shown in Figure 13-13. The CK and MCK are generated by HCLK divider, with the prescaler of the MCK determined by I2SDIV and I2SODD.
Page 187 AT32F403A/407 Series Reference Manual 22050 22084.81 0.16% 22007.04 0.19% 16000 15984.65 0.10% 16025.64 0.16% 11025 11022.93 0.02% 11042.4 0.16% 8000 8002.561 0.03% 7992.327 0.10% 192000 130208.3 32.18% 130208.3 32.18% 96000 97656.25 1.73% 97656.25 1.73% 48000 48828.13 1.73% 48828.13 1.73% 44100 43402.78 1.58% 43402.78...
Page 188: Dma Transfer
AT32F403A/407 Series Reference Manual 13.3.6 DMA transfer The SPI supports write and read operations with DMA. Whether used as SPI or I S, read/write request using DMA comes from the same peripheral. As a result, their configuration procedure are the same, described as follows.
Page 189: Interrupts
AT32F403A/407 Series Reference Manual ─ I2SDBN, I2SCBN,STDSLE combination: wait for the second-to-last RDBF=1 and one CK period before disabling the I S transmitter configuration procedure:  Configure operation mode selector  Configure audio protocol selector  Configure I2S_SCK controller  Configure DMA transfer (if necessary) Set the I2SEN bit to enable I ...
Page 190: Spi Registers
AT32F403A/407 Series Reference Manual 13.4 SPI registers These peripheral registers must be accessed by half-word (16 bits) or word (32 bits). Table 13- 2 SPI register map and reset value Register Offset Reset value SPI_CTRL1 0x00 0x0000 SPI_CTRL2 0x04 0x0000 SPI_STS 0x08 0x0002...
Page 191: Spi Control Register2 (Spi_Ctrl2)
AT32F403A/407 Series Reference Manual This bit is valid only when the SWCSEN is set. It determines the level on the CS pin. In master mode, this bit must be set. 0: Low level 1: High level LSB transmit first This bit is used to select for MST transfer first or LSB transfer first.
Page 192: Spi Status Register (Spi_Sts)
AT32F403A/407 Series Reference Manual 1: Enabled Kept at its default value Bit 4: 3 Reserved resd Hardware CS output enable This bit is valid only in master mode. When this bit is set, the I/O output on the CS pin is low; when this bit is 0, the Bit 2 HWCSOE I/O input on the CS pin must be set high.
Page 193: Spi Data Register (Spi_Dt)
AT32F403A/407 Series Reference Manual 13.4.4 SPI data register (SPI_DT) Register Reset value Type Description Data value This register controls read and write operations. When the Bit 15: 0 0x0000 data bit is set as 8 bit, only the 8-bit LSB [7: 0] is valid. 13.4.5 SPICRC register (SPI_CPOLY) (Not used in I S mode) Register...
Page 194: Spi_I2S Prescaler Register (Spi_I2Sclkp)
AT32F403A/407 Series Reference Manual 1: Long frame synchronization Kept at its default value Bit 6 Reserved resd S standard select 00: Philips standard 01: MSB-aligned standard (left-aligned) Bit 5: 4 STDSEL 10: LSB-aligned standard (right-aligned) 11: PCM standard S clock polarity This bit indicates the clock polarity on the clock pin in idle state.
Page 195: Timer
AT32F403A/407 Series Reference Manual 14 Timer AT32F403A/407 timers include basic timers, general-purpose timers, and advanced-control timers. Please refer to Section 14.1 ~ Section 14.4 for the detailed function modes. All functions of different timers are shown in the following tables. Table 14- 1 TMR functional comparison Counter Count...
Page 196: Basic Timer (Tmr6 And Tmr7)
AT32F403A/407 Series Reference Manual 14.1 Basic timer (TMR6 and TMR7) 14.1.1 TMR6 and TMR7 introduction Each of the basic timers (TMR6 and TMR7) includes a 16-bit up counter and the corresponding control logic. without being connected to external I/Os. They can be used for a basic timing and providing clocks for the digital-to-analog converter (DAC).
Page 197: Debug Mode
AT32F403A/407 Series Reference Manual 14- 3 Figure Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear 14- 4 Figure Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear 14- 5 Figure Counting timing diagram when the prescaler division is 4 TMR_CLK CNT_CLK COUNTER...
Page 198: Tmr6 And Tmr7 Control Register1 (Tmrx_Ctrl1)
AT32F403A/407 Series Reference Manual 14.1.4.1 TMR6 and TMR7 control register1 (TMRx_CTRL1) Register Reset value Type Description Kept at its default value. Bit 15: 8 Reserved 0x00 resd Period buffer enable 0: Period buffer is disabled. Bit 7 PRBEN 1: Period buffer is enabled. Kept at its default value.
Page 199: Tmr6 And Tmr7 Interrupt Status Register (Tmrx_Ists)
AT32F403A/407 Series Reference Manual Overflow interrupt enable 0: Disabled Bit 0 OVFIEN 1: Enabled 14.1.4.4 TMR6 and TMR7 interrupt status register (TMRx_ISTS) Register Reset value Type Description Kept at its default value. Bit 15: 1 Reserved 0x0000 resd Overflow interrupt flag This bit is set by hardware at an update event.
Page 200: Tmrx Main Features
AT32F403A/407 Series Reference Manual 14.2.2 TMRx main features  Source of count clock is selectable : internal clock, external clock and internal trigger  16-bit up, down, up/down and encoder mode counter (TMR2/5 can be extended to 32-bit)  4 independent channels for input capture, output compare, PWM generation and one-pulse mode output ...
Page 201: Figure 14- 8 Block Diagram Of External Clock Mode A
AT32F403A/407 Series Reference Manual 14- 8 Figure Block diagram of external clock mode A Slave mode control Filter CI1RAW C1INC CK_DIV Polarity Trigger select C1IFP2 selection C2IF_Rising Edge C1IFP1 External clock detector control C2IF_Falling Note: The delay between the signal on the input side and the actual clock of the counter is due to the synchronization circuit.
Page 202: Counting Mode
AT32F403A/407 Series Reference Manual Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer. Set the STIS[2: 0] bit to select internal trigger signal to enable counting. Each timer (TMR2 to TMR5) consists of a 16-bit prescaler, which is used to generate the CK_CNT that enables the counter to count.
Page 203: Figure 14- 13 Overflow Event When Prben=0
AT32F403A/407 Series Reference Manual 14- 13 Figure Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear 14- 14 Figure Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed, and generates a counter underflow event.
Page 204: Tmr Input Function
AT32F403A/407 Series Reference Manual Encoder interface mode To enble the encoder interface mode, write SMSEL[2: 0]= 3’b001/3’b010/3’b011. In this mode, the two inputs (C1IN/C2IN) are required. Depending on the level on one input, the counter counts up or down on the edge of the other input. The OWCDIR bit indicates the direction of the counter, as shown in the table below: Table 14- 4 Couting direction versus encoder signals C1INFP1 signal...
Page 205: Tmr Output Function
AT32F403A/407 Series Reference Manual 14- 19 Figure Channel 1 input stage Filter C2IFP1 Downcounter C1IRAW Capture/ Polarity C1IPS C1IFP1 C1IN compare divider selection select C1IF_rising Edge detector STCI C1IF_falling Input mode In input mode, the TMRx_CxDT registers latch the current counter values after the selected triggle signal is detected, and the capture compare interrupt flag bit (CxIF) is set.
Page 206: Figure 14- 21 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F403A/407 Series Reference Manual  PWM mode: Set CxOCTRL=3’b110/111 to enable PWM mode. Each channel can be independently configured to output one PWM signal. In this case, the period of the output signal is configured by the TMRx_PR register, and the duty cycle by the CxDT register. The counter value is compared with the value of the TMRx_CxDT register, and the corresponding level signal is sent according to the counting direction.
Page 207: Figure 14- 22 Upcounting Mode And Pwm Mode A
AT32F403A/407 Series Reference Manual 14- 22 Figure Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0] C1ORAW >32 C1DT[15：0] C1ORAW 14- 23 Figure Up/down counting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0]...
Page 208: Tmr Synchronization
AT32F403A/407 Series Reference Manual Figure 14-25 shows the example of clearing CxORAW signal. When the EXT input is high, the CxORAW signal, which was originally high, is driven low; when the EXT is low, the CxORAW signal outputs the corresponding level according to the comparison result between the counter value and CxDT value. 14- 25 Figure Clearing CxORAW(PWM mode A) by EXT input...
Page 209: Figure 14- 27 Example Of Suspend Mode
AT32F403A/407 Series Reference Manual 14- 27 Figure Example of suspend mode TMR_CLK CI1F1 TMR_EN CNT_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] Slave mode: Trigger mode The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1) Figure 14- 28 Example of trigger mode TMR_CLK CI1F1 TMR_EN...
Page 210: Figure 14- 30 Using Master Timer To Start Slave Timer
AT32F403A/407 Series Reference Manual  Configure the slave timer trigger input signal TRGIN as master timer output (STIS[2: 0] in the TMRx_STCTRL register)  Configure the slave timer to use external clock mode A (SMSEL[2: 0]=3’b111 in the TMRx_STCTRL register ) ...
Page 211: Debug Mode
AT32F403A/407 Series Reference Manual Figure Starting master and slave timers synchronously by an external trigger 14- 31 TMR_CLK COUNTER PR[15:0] Master DIV[15:0] TRGIN TMR_EN TMR_CLK TMREN Slave COUNTER DIV[15:0] PR[15:0] 14.2.3.6 Debug mode When the microcontroller enters debug mode (Cortex -M4F core halted), the TMRx counter stops counting by setting the TMRx_PAUSE in the DEBUG module.
Page 212: Control Register1 (Tmrx_Ctrl1)
AT32F403A/407 Series Reference Manual 14.2.4.1 Control register1 (TMRx_CTRL1) Register Reset value Type Description Kept at its default value. Bit 15: 11 Reserved 0x00 resd Plus Mode Enable This bit is used to enable TMRx plus mode. In this mode, TMRx_CVAL, TMRx_PR and TMRx_CxDT are extended from 16-bit to 32-bit.
Page 213: Control Register2 (Tmrx_Ctrl2)
AT32F403A/407 Series Reference Manual 14.2.4.2 Control register2 (TMRx_CTRL2) Register Reset value Type Description Kept at its default value. Bit 15: 8 Reserved 0x00 resd C1IN selection 0: CH1 pin is connected to C1IRAW input Bit 7 C1INSEL 1: The XOR result of CH1, CH2 and CH3 pins is connected to C1IRAW input Master TMR output selection This field is used to select the TMRx signal sent to the...
Page 214: Dma/Interrupt Enable Register (Tmrx_Iden)
AT32F403A/407 Series Reference Manual 1010: f /16, N=5 �� 1011: f /16, N=6 �� 1100: f /16, N=8 �� 1101: f /32, N=5 �� 1110: f /32, N=6 �� 1111: f /32, N=8 �� Subordinate TMR synchronization If enabled, master and slave timer can be synchronized.
Page 215: Interrupt Status Register (Tmrx_Ists)
AT32F403A/407 Series Reference Manual 1: Enabled Channel 1 DMA request enable 0: Disabled Bit 9 C1DEN 1: Enabled Overflow event DMA request enable 0: Disabled Bit 8 OVFDEN 1: Enabled Kept at its default value Bit 7 Reserved resd Trigger interrupt enable 0: Disabled Bit 6 TIEN...
Page 216: Software Event Register (Tmrx_Sw Evt)
AT32F403A/407 Series Reference Manual Please refer to C1IF description. Channel 3 interrupt flag rw0c Bit 3 C3IF Please refer to C1IF description. Channel 2 interrupt flag rw0c Bit 2 C2IF Please refer to C1IF description. Channel 1 interrupt flag If the channel 1 is configured as input mode: This bit is set by hardware on a capture event.
Page 217 AT32F403A/407 Series Reference Manual Channel 2 output control Bit 14: 12 C2OCTRL Channel 2 output buffer enable Bit 11 C2OBEN Channel 2 output enable immediately Bit 10 C2OIEN Channel 2 configuration This field is used to define the direction of the channel 2 (input or output), and the selection of input pin when C2EN=’0’: 00: Output...
Page 218 AT32F403A/407 Series Reference Manual Channel 1 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C1EN=’0’: 00: Output Bit 1: 0 01: Input, C1IN is mapped on C1IRAW 10: Input, C1IN is mapped on C2IRAW 11: Input, C1IN is mapped on STCI.
Page 219: Channel Mode Register2 (Tmrx_Cm2)
AT32F403A/407 Series Reference Manual 00: Output 01: Input, C1IN is mapped on C1IRAW 10: Input, C1IN is mapped on C2IRAW 11: Input, C1IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS. 14.2.4.8 Channel mode register2 (TMRx_CM2) Output compare mode: Register...
Page 220: Channel Control Register (Tmrx_Cctrl)
AT32F403A/407 Series Reference Manual 01: Input, C3IN is mapped on C3IRAW 10: Input, C3IN is mapped on C4IRAW 11: Input, C3IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS. 14.2.4.9 Channel control register (TMRx_CCTRL) Register Reset value Type...
Page 221: Division Value (Tmrx_Div)
AT32F403A/407 Series Reference Manual 14.2.4.11 Division value (TMRx_DIV) Register Reset value Type Description Divider value The counter clock frequency f /(DIV[15: CK_CNT TMR_CLK Bit 15: 0 0x0000 0]+1). DIV contains the value written at an overflow event. 14.2.4.12 Period register (TMRx_PR) Register Reset value Type...
Page 222: Channel 4 Data Register (Tmrx_C4Dt)
AT32F403A/407 Series Reference Manual When the channel 3 is configured as input mode: The C3DT is the CVAL value stored by the last channel 3 input event (C1IN) When the channel 3 is configured as output mode: C3DT is the value to be compared with the CVAL value. Whether the written value takes effective immediately depends on the C3OBEN bit, and the corresponding output is generated on C3OUT as configured.
Page 223: Tmrx Main Features
AT32F403A/407 Series Reference Manual 14.3.2 TMRx main features 14.3.2.1 TMR9 and TMR12 main features The main functions of general-purpose TMR9 and TMR12 include:  Souce of counter clock: internal clock and external clock  16-bit up counter  2 independent channels for input capture, output compare, PWM generation and one-pulse mode output ...
Page 224: Tmrx Functional Overview
AT32F403A/407 Series Reference Manual 14.3.3 TMRx functional overview 14.3.3.1 Count clock The count clock of general-purpose timers can be provided by the internal clock (CK_INT), external clock (external clock mode A) and internal trigger input (ISx) Internal clock (CK_INT) By default, the CK_INT divided by the prescaler is used to drive the counter to start counting. Figure 14- 34 Control circuit with CK_INT divided by 1...
Page 225: Counting Mode
AT32F403A/407 Series Reference Manual Table 14- 7 TMRx internal trigger connection Slave controler (STIS=000) (STIS = 001) (STIS = 010) (STIS = 011) TMR9 TMR2_TRGOUT TMR3_TRGOUT TMR10_OC TMR11_OC TMR12 TMR4_TRGOUT TMR5_TRGOUT TMR13_OC TMR14_OC Note: If there is no corresponding timer in a device, the corresponding trigger signal ISx is not present. 14- 37 Figure Counter timing with prescaler value changing from 1 to 4...
Page 226: Tmr Input Function
AT32F403A/407 Series Reference Manual 14.3.3.3 TMR input function Each timer of TMR9 and TMR12 has two independent channels, while each of TMR10, TMR11, TMR13 and TMR14 has an independent channel. Each channel can be configured as input or output. As input, the channel can be used for the filtering, selection, division and input capture of the input signals.
Page 227: Figure 14- 42 Capture/Compare Channel Output Stage (Channel 1)
AT32F403A/407 Series Reference Manual 14- 42 Figure Capture/compare channel output stage (channel 1 ) CVAL CVAL=C1DT Compare Output mode C1ORAW Polarity Output controller CVAL>C1DT selection enable C1OUT C1DT circuit Output mode Write CxC[2: 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this case, the counter value is compared with the value in the TMRx_CxDT register, and the intermediate signal CxORAW is generated according to the output mode selected by CxOCTRL[2: 0], which is sent to IO after being processed by the output control circuit.
Page 228: Tmr Synchronization
AT32F403A/407 Series Reference Manual 14- 43 Figure C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW 14- 44 Figure Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0]...
Page 229: Debug Mode
AT32F403A/407 Series Reference Manual Figure 14- 46 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] CI1F1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low.
Page 230: Tmr9 And Tmr12 Registers
AT32F403A/407 Series Reference Manual 14.3.4 TMR9 and TMR12 registers These peripheral registers must be accessed by word (32 bits). All TMRx register are mapped into a 16-bit addressable space. Table 14- 8 TMRx register map and reset value Register Reset value TMRx_CTRL1 0x00 0x0000...
Page 231: Slave Timer Control Register (Tmrx_Stctrl)
AT32F403A/407 Series Reference Manual 14.3.4.2 Slave timer control register (TMRx_STCTRL) Register Reset value Type Description Bit 15:7 Reserved 0x000 resd Kept at its default value Subordinate TMR input selection This field is used to select the subordinate TMR input. 000: Internal selection 0 (IS0) 001: Internal selection 1 (IS1) 010: Internal selection 2 (IS2) 011: Internal selection 3 (IS3)
Page 232: Software Event Register (Tmrx_Sw Evt)
AT32F403A/407 Series Reference Manual Channel 1 recapture flag This bit indicates whether a recapture is detected when C1IF=1. This bit is set by hardware, and cleared by writing Bit 9 C1RF rw0c “0”. 0: No capture is detected 1: Capture is detected. Kept at its default value.
Page 233: Channel Mode Register1 (Tmrx_Cm1)
AT32F403A/407 Series Reference Manual 14.3.4.6 Channel mode register1 (TMRx_CM1) The channel can be used in input (capture mode) or output (compare mode). The direction of a channel is defined by the corresponding CxC bits. All the other bits of this register have different functons in input and output modes.
Page 234 AT32F403A/407 Series Reference Manual register, and can be sent to the TMRx_C1DT register only on an overflow event. Channel 1 output enable immediately In PWM mode A or B, this bit is used to accelerate the channel 1 output’s response to the trigger event. 0: Need to compare the CVAL with C1DT before Bit 2 C1OIEN...
Page 235: Channel Control Register (Tmrx_Cctrl)
AT32F403A/407 Series Reference Manual 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’ Channel 1 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when...
Page 236: Period Register (Tmrx_Pr)
AT32F403A/407 Series Reference Manual 14.3.4.10 Period register (TMRx_PR) Register Reset value Type Description Period value Bit 15: 0 0x0000 This defines the period value of the TMRx counter. The timer stops working when the period value is 0. 14.3.4.11 Channel 1 data register (TMRx_C1DT) Register Reset value Type...
Page 237: Control Register1 (Tmrx_Ctrl1)
AT32F403A/407 Series Reference Manual 14.3.5.1 Control register1 (TMRx_CTRL1) Register Reset value Type Description Bit 15: 10 Reserved 0x00 resd Kept at its default value Clock divider 00: Normal 01: Divided by 2 Bit 9: 8 CLKDIV 10: Divided by 4 11: Reserved Period buffer enable 0: Period buffer is disabled...
Page 238: Software Event Register (Tmrx_Sw Evt)
AT32F403A/407 Series Reference Manual 0: No capture event occurs 1: Capture event is generated If the channel 1 is configured as output mode: This bit is set by hardware on a compare event. It is cleared by software. 0: No compare event occurs 1: Compare event is generated Overflow interrupt flag This bit is set by hardware on an overflow event.
Page 239 AT32F403A/407 Series Reference Manual Note: In the configurations othern than 000’, the C1OUT is connected to C1ORAW. The C1OUT output level is not only subject to the changes of C1ORAW, but also the output polarity set by CCTRL. Channel 1 output buffer enable 0: Buffer function of TMRx_C1DT is disabled.
Page 240: Channel Control Register (Tmrx_Cctrl)
AT32F403A/407 Series Reference Manual 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’ Channel 1 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C1EN=’0’: 00: Output...
Page 241: Channel 1 Data Register (Tmrx_C1Dt)
AT32F403A/407 Series Reference Manual 14.3.5.10 Channel 1 data register (TMRx_C1DT) Register Reset value Type Description Channel 1 data register When the channel 1 is configured as input mode: The C1DT is the CVAL value stored by the last channel 1 input event (C1IN) Bit 15: 0 C1DT 0x0000...
Page 242: Tmr1 And Tmr8 Functional Overview
AT32F403A/407 Series Reference Manual Figure 14- 49 Block diagram of advanced-control timer Clock failure event From clock control CSS(Clock Security System) Polarity selection TMRx_BRK C4ORAW TMRx_CH4 C4IRAW Output C4OUT TMRx_CH4 control CxDT (INPUT) Edge detector TMRx_CH3 C3OUT C3IRAW C3ORAW Output TMRx_CH3 C3COUT TMRx_CH3C...
Page 243: Figure 14- 52 Counting In External Clock Mode A
AT32F403A/407 Series Reference Manual Note: The delay between the signal on the input side and the actual clock of the counter is due to the synchronization circuit. Figure 14- 52 Counting in external clock mode A TMR_CLK C2IRAW CNT_CLK COUNTER STIS[2:0] C2IF[2:0] OVFIF...
Page 244: Counting Mode
AT32F403A/407 Series Reference Manual Table 14- 12 TMRx internal trigger connection Slave timer IS0 (STIS=000) IS1 (STIS=001) IS2 (STIS=010) IS3 (STIS=011) TMR1 TMR5 TMR2 TMR3 TMR4 TMR8 TMR1 TMR2 TMR4 TMR5 Reserved TMR8 TMR2 TMR4 TMR5 Figure 14- 55 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER...
Page 245: Figure 14- 58 Counter Timing Diagram With Internal Clock Divided By 4
AT32F403A/407 Series Reference Manual Downcounting mode In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed in the TMRx_PR register, and generates a counter underflow event. Figure 14- 58 Counter timing diagram with internal clock divided by 4 TMR_CLK CNT_CLK COUNTER...
Page 246: Tmr Input Function
AT32F403A/407 Series Reference Manual Table 14- 13 Couting direction versus encoder signals C1INFP1 signal C2INFP2 signal Level on opposite signal Active edge (C1INFP1 to C2IN, C2INFP2 to C1IN) Rising Falling Rising Falling High Down No count No count Count on C1IN only Down No count No count...
Page 247: Tmr Output Function
AT32F403A/407 Series Reference Manual Input mode In input mode, the TMRx_CxDT registers latch the current counter values after the selected triggle signal is detected, and the capture compare interrupt flag bit (CxIF) is set. An interrupt/DMA request will be generated if the CxIEN bit and CxDEN bit are enabled. If the selected trigger signal is detected when the CxIF is set, the CxOF is set.
Page 248: Figure 14- 66 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F403A/407 Series Reference Manual  PWM mode: Set CxOCTRL=2’b110/111 to enable PWM mode. Each channel can be independently configured to output one PWM signal. In this case, the period of the output signal is configured by the TMRx_PR register, and the duty cycle by the CxDT register. The counter value is compared with the value of the TMRx_CxDT register, and the corresponding level signal is sent according to the counting direction.
Page 249: Figure 14- 67 Upcounting Mode And Pwm Mode A
AT32F403A/407 Series Reference Manual Figure 14- 67 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0] C1ORAW >32 C1DT[15：0] C1ORAW Figure 14- 68 Up/down counting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0]...
Page 250: Figure 14- 69 One-Pulse Mode
AT32F403A/407 Series Reference Manual Figure 14- 69 One-pulse mode CxORAW clear When the CxOSEN bit is set, the CxORAW signal for a given channel is cleared by applying a high level to the EXT input. The CxORAW signal remains unchanged until the next overflow event. This function can only be used in output capture or PWM modes, and does not work in forced mode.
Page 251: Tmr Break Function
AT32F403A/407 Series Reference Manual Figure 14- 71 Complementary output with dead-time insertion 14.4.3.5 TMR break function When the break function is enabled (BRKEN=1), the CxOUT 和 CxCOUT are jointly controlled by OEN, FCSODIS, FCSOEN, CxIOS and CxCIOS. But, CxOUT and CxCOUT cannot be set both to active level at the same time.
Page 252: Tmr Synchronization
AT32F403A/407 Series Reference Manual Figure 14- 72 Example of TMR break function AOEN CxORAW CxEN CxCEN CxIOS CxCIOS CxOUT Delay CxCOUT Delay Delay 14.4.3.6 TMR synchronization The timers are linked together internnaly for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit;...
Page 253: Debug Mode
AT32F403A/407 Series Reference Manual Figure 14- 74 Example of suspend mode TMR_CLK CI1F1 TMR_EN CNT_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] Slave mode: Trigger mode The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1) Figure 14- 75 Example of trigger mode TMR_CLK CI1F1 TMR_EN...
Page 254: Tmr1 And Tmr8 Control Register1 (Tmrx_Ctrl1)
AT32F403A/407 Series Reference Manual TMRx_CVAL 0x24 0x0000 TMRx_DIV 0x28 0x0000 TMRx_PR 0x2C 0x0000 TMRx_RPR 0x30 0x0000 TMRx_C1DT 0x34 0x0000 TMRx_C2DT 0x38 0x0000 TMRx_C3DT 0x3C 0x0000 TMRx_C4DT 0x40 0x0000 TMRx_BRK 0x44 0x0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000 14.4.4.1 TMR1 and TMR8 control register1 (TMRx_CTRL1) Register Reset value Type...
Page 255: Tmr1 And Tmr8 Control Register2 (Tmrx_Ctrl2)
AT32F403A/407 Series Reference Manual TMR enable 0: Disabled Bit 0 TMREN 1: Enabled 14.4.4.2 TMR1 and TMR8 control register2 (TMRx_CTRL2) Register Reset value Type Description Bit 15 Reserved 0x00 resd Kept at its default value. Bit 14 Channel 4 idle output state C4IOS Bit 13 Channel 3 complementary idle output state...
Page 256: Tmr1 And Tmr8 Slave Timer Control Register (Tmrx_Stctrl)
AT32F403A/407 Series Reference Manual 14.4.4.3 TMR1 and TMR8 slave timer control register (TMRx_STCTRL) Register Reset value Type Description External signal polarity 0: High or rising edge Bit 15 1: Low or falling edge External clock mode B enable This bit is used to enable external clock mode B Bit 14 ECMBEN 0: Disabled...
Page 257: Tmr1 And Tmr8 Dma/Interrupt Ena Ble Register (Tmrx_Iden)
AT32F403A/407 Series Reference Manual Subordinate TMR mode selection 000: Slave mode is disabled 001: Encoder mode A 010: Encoder mode B 011: Encoder mode C 100: Reset mode — Rising edge of the TRGIN input reinitializes the counter Bit 2: 0 SMSEL 101: Suspend mode —...
Page 258: Tmr1 And Tmr8 Interrupt Status Register (Tmrx_Ists)
AT32F403A/407 Series Reference Manual 0: Disabled 1: Enabled Channel 2 interrupt enable 0: Disabled Bit 2 C2IEN 1: Enabled Channel 1 interrupt enable 0: Disabled Bit 1 C1IEN 1: Enabled Overflow interrupt enable 0: Disabled Bit 0 OVFIEN 1: Enabled 14.4.4.5 TMR1 and TMR8 interrupt status register (TMRx_ISTS) Register Reset value...
Page 259: Software Event Register (Tmrx_Sw Evt)
AT32F403A/407 Series Reference Manual This bit is set by hardware on a capture event. It is cleared by software or read access to the TMRx_C1DT 0: No capture event occurs 1: Capture event is generated If the channel 1 is configured as output mode: This bit is set by hardware on a compare event.
Page 260: Tmr1 And Tmr8 Channel Mode Register1 (Tmrx_Cm1)
AT32F403A/407 Series Reference Manual 14.4.4.7 TMR1 and TMR8 channel mode register1 (TMRx_CM1) The channel can be used in input (capture mode) or output (compare mode). The direction of a channel is defined by the corresponding CxC bits. All the other bits of this register have different functons in input and output modes.
Page 261 AT32F403A/407 Series Reference Manual 1: Buffer function of TMRx_C1DT is enabled. The value to be written to the TMRx_C1DT is stored in the buffer register, and can be sent to the TMRx_C1DT register only on an overflow event. Channel 1 output enable immediately In PWM mode A or B, this bit is used to accelerate the channel 1 output’s response to the trigger event.
Page 262: Channel Mode Register2 (Tmrx_Cm2)
AT32F403A/407 Series Reference Manual 00: No divider. An input capture is generated at each active edge. 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’...
Page 263: Channel Control Register (Tmrx_Cctrl)
AT32F403A/407 Series Reference Manual Channel 4 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C4EN=’0’: 00: Output Bit 9: 8 01: Input, C4IN is mapped on C4IRAW 10: Input, C4IN is mapped on C3IRAW 11: Input, C4IN is mapped on STCI.
Page 264: Table 14- 15 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function
AT32F403A/407 Series Reference Manual When the channel 1 is configured as input mode: 0: C1IN active edge is on its rising edge. When used as external trigger, C1IN is not inverted. 1: C1IN active edge is on its falling edge. When used as external trigger, C1IN is inverted.
Page 265: Tmr1 And Tmr8 Counter Value (Tmrx_Cval)
AT32F403A/407 Series Reference Manual Note: If the two outputs of a channel are not used (CxEN = CxCEN = 0), CxIOS, CxCIOS, CxP and CxCP must be cleared. Note: The state of the external I/O pins connected to the complementary CxOUT and CxCOUT channels depends on the CxOUT and CxCOUT channel state and the GPIO and the IOMUX registers.
Page 266: Tmr1 And Tmr8 Channel 3 Data Register (Tmrx_C3Dt)
AT32F403A/407 Series Reference Manual 14.4.4.16 TMR1 and TMR8 channel 3 data register (TMRx_C3DT ) Register Reset value Type Description Channel 3 data register When the channel 3 is configured as input mode: The C3DT is the CVAL value stored by the last channel 3 input event (C1IN) Bit 15: 0 C3DT...
Page 267: Tmr1 And Tmr8 Dma Control Register (Tmrx_ Dmactrl)
AT32F403A/407 Series Reference Manual 1: CxOUT/CxCOUT outputs are enabled. Output idle level. Write protection configuration his field is used to enable write protection. 00: Write protection is OFF. 01: Write protection level 3, and the following bits are write protected: TMRx_BRK: DTC, BRKEN, BRKV and AOEN TMRx_CTRL2: CxIOS and CxCIOS 10: Write protection level 2.
Page 268: Tmr1 And Tmr8 Dma Data Register (Tmrx_ Dmadt)
AT32F403A/407 Series Reference Manual 14.4.4.20 TMR1 and TMR8 DMA data register (TMRx_ DMADT) Register Reset value Type Description DMA data register A write/read operation to the DMADT register accesses any TMR register located at the following address: Bit 15: 0 DMADT 0x0000 TMRx peripheral address + ADDR*4 to TMRx peripheral...
Page 269: Window Watchdog Timer (Wwdt)
AT32F403A/407 Series Reference Manual 15 Window watchdog timer (WWDT) 15.1 WWDT introduction The window watchdog downcounter must be reloaded in a limited time window to prevent the watchdog circuits from generating a system reset. The window watch dog is used to detect the occurrence of system malfunctions.
Page 270: Debug Mode
AT32F403A/407 Series Reference Manual Table 15- 1 Minimum and maximum timeout value when PCLK1=72 MHz Prescaler Min. Timeout value Max. Timeout value 56.5μs 3.64ms 113.5μs 7.28ms 227.5μs 14.56ms 455μs 29.12ms Figure 15- 2 W indow watchdog timing diagram CNT[6：0] 55 54 52 51 50 4F 4E 4D 4C 4B 4A 41 40...
Page 271: Status Register (Wwdt_Sts)
AT32F403A/407 Series Reference Manual 01: PCLK1 divided by 8192 10: PCLK1 divided by 16384 11: PCLK1 divided by 32768 Window value if the counter is reloaded while its value is greater than the Bit 6: 0 0x7F window register value, a reset is generated. The counter must be reloaded between 0x40 and WIN[6: 0].
Page 272: Watchdog Timer (Wdt)
AT32F403A/407 Series Reference Manual 16 Watchdog timer (WDT) 16.1 WDT introduction The WDT is driven by a dedicated low-speed clock (LICK). Due to the lower clock accuracy of LICK, the WDT is best suited to the applications that have lower timing accuracy and can run independently outside the main application.
Page 273: Debug Mode
AT32F403A/407 Series Reference Manual Figure 16- 1 W DT block diagram power domain 1.2 V power domain Prescaler register 8-bit SYNC WDT_DIV prescaler Reload register 12-bit reload 12-bit SYNC CNT=0 reset WDT_RLD value downcounter Status register WDT_STS CMD register WDT_CMD LICK 40KHz PCLK Table 16- 1 W DT timeout period (LICK=40kHz)
Page 274: Command Register (Wdt_Cmd)
AT32F403A/407 Series Reference Manual 16.5.1 Command register (WDT_CMD) (Reset in Standby mode) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. Command register 0xAAAA: Reload counter Bit 15: 0 0x0000 0x5555: Unlock write-protected WDT_DIV and WDT_RLD 0xCCCC: Enable WDT.
Page 275: Real-Time Clock (Rtc)
AT32F403A/407 Series Reference Manual 17 Real-time clock (RTC) 17.1 RTC introduction The real-time clock provides a calendar clock function. It has an internal 32-bit incremental couner that is increased by one at each second. In other words, this counter serves as a second clock. The current seond value can be converted into time and date to provide a calendar function.
Page 276: Rtc Functional Overview
AT32F403A/407 Series Reference Manual Figure 17- 1 Simplified RTC block diagram 1.2V power domain VBAT domain Powered in Standby mode RTC_TA Not powered in Standby mode RTC_Alarm RTC_Oveflow RTC_CNT OVFF LN_CLK Reload RTC_Second RTC_DIVCNT RTC_DIV RTC registers interface RTC_CLK NVIC interrupt controller Not powered in Standby mode PCLK1...
Page 277: Reading Rtc Registers
AT32F403A/407 Series Reference Manual 17.4.2 Reading RTC registers Based on synchronization circuit, when reading the RTC registers, the correct values have yet been uploaded from the battery powered domain to the APB1 interface if one of the following events occurred: A system reset or power reset has occurred;...
Page 278: Rtc Registers
AT32F403A/407 Series Reference Manual Figure 17- 3 RTC overflow waveform example with DIV=0004 RTC_CLK RTC_Second Can be cleared by software RTC_Overflow RTC_CNT FFFFFFFD FFFFFFFE FFFFFFFF 00000000 00000001 FFFFFFFC 17.5 RTC registers These peripheral registers must be accessed by word (32 bits). RTC registers are 16-bit addressable registers.
Page 279: Rtc Control Register Low (Rtc_Ctrll)
AT32F403A/407 Series Reference Manual 17.5.2 RTC control register low (RTC_CTRLL) Register Reset value Type Description Bit 15: 6 Reserved 0x000 resd Kept at its default value. RTC configuration finish Indicates whether the last write operation on the RTC registers has been completed or not. Write access to the Bit 5 CFGF RTC registers is allowed only when this bit is set.
Page 280: Rtc Divider Counter Register (Rtc_ Divcnth/Rtc_Divcntl)
AT32F403A/407 Series Reference Manual 17.5.4 RTC divider counter register (RTC_ DIVCNTH/RTC_DIVCNTL) RTC divider counter register high (RTC_DIVCNTH ) Register Reset value Type Description Bit 15: 4 Reserved 0x000 resd Kept at its default value. Bit 3: 0 DIVCNT RTC clock divider counter RTC divider counter register low (RTC_DIVCNTL ) Register Reset value...
Page 281: Battery Powered Registers (Bpr)
AT32F403A/407 Series Reference Manual 18 Battery powered registers (BPR) 18.1 BPR introduction The battery powered registers are located in the battery powered domain and powered by VDD/VBAT. These registers are forty two 16-bit registers. Upon a tamper event or when battery powered domain reset occurs, the contents in these registers are cleared so as to ensure the highest level of data security.
Page 282: Battery Powered Data Register X (Bpr_Dtx) (X = 1
AT32F403A/407 Series Reference Manual BPR_DT14 0x4C 0x0000 0000 BPR_DT15 0x50 0x0000 0000 BPR_DT16 0x54 0x0000 0000 BPR_DT17 0x58 0x0000 0000 BPR_DT18 0x5C 0x0000 0000 BPR_DT19 0x60 0x0000 0000 BPR_DT20 0x64 0x0000 0000 BPR_DT21 0x68 0x0000 0000 BPR_DT22 0x6C 0x0000 0000 BPR_DT23 0x70 0x0000 0000...
Page 283: Bpr Control Register (Bpr_ Ctrl)
AT32F403A/407 Series Reference Manual 1: Toggle output (The corresponding pin output level changes at each time when an alarm event or second event is detected) Note: This bit is reset only by a battery powered domain reset. Calibration clock output selection 0: Calibration clock output is disabled Bit 10 CCOS...
Page 284: Bpr Control/Status Register (Bpr_ Ctrlsts)
AT32F403A/407 Series Reference Manual 18.4.4 BPR control/status register (BPR_ CTRLSTS) Register Reset value Type Description Kept at its default value. Bit 15: 10 Reserved 0x00 resd Tamper interrupt flag This bit is set when a tamper event is detected and the TPIEN is set.
Page 285: Analog-To-Digital Converter (Adc)
AT32F403A/407 Series Reference Manual 19 Analog-to-digital converter (ADC) 19.1 ADC introduction The ADC is a peripheral that converts an analog input signal into a 12-bit digital signal. Its sampling rate is as high as 2 MSPS. It has up to 18 channels for sampling and conversion. 19.2 ADC main features In terms of analog part: ...
Page 286: Adc Functional Overview
AT32F403A/407 Series Reference Manual Figure 19- 1 ADC1 block diagram OCTESEL[3:0] ADCPSC[3:0] TMR1_CH1 TMR1_CH2 ADC prescaler TMR1_CH3 PCLK2 TMR2_CH2 ADCCLK TMR3_TRGOUT TMR4_CH4 OCTEN EXINT11 ADCx_IN0 TMR8_TRGOUT Trigger ADCx_IN1 detection GPIO ADCx_ETO_MUX Ordinary OCSWTRG ADCx_IN15 conversion start TMR1_TRGOUT TMR8_CH1 Temp.sensor TMR8_CH2 INTRV Channel manegement...
Page 287: Internal Temperature Sensor
AT32F403A/407 Series Reference Manual  ADC2_IN0 to ADC2_IN15 are referred to as the external analog input, and ADC2_IN16 and ADC2_IN17 as Vss  ADC3_IN0 to ADC3_IN3, and ADC3_IN10 to ADC3_IN13 are referred to as the external analog input, the rest of them are Vss. Channel conversion The conversions are divided into two groups: ordinary and preempted.
Page 288: Power-On And Calibration
AT32F403A/407 Series Reference Manual 19.4.2.1 Power-on and calibration Power-on Set the ADCxEN bit in the CRM_APB2EN register to enable ADC clocks: PCLK2 and ADCCLK. Program the desired ADCCLK frequency by setting the ADCDIV bit in the CRM_CFG register. The ADCCLK is derived from PCLK2 frequency division. Note: ADCCLK must be less than 28 MHz.
Page 289: Sampling And Conversion Sequence
AT32F403A/407 Series Reference Manual Table 19- 1 Trigger sources for ADC1 and ADC2 OCTESEL Source PCTESEL Source 0000 TMR1_CH1 event 0000 TMR1_TRGOUT event 0001 TMR1_CH2 event 0001 TMR1_CH4 event 0010 TMR1_CH3 event 0010 TMR2_TRGOUT event 0011 TMR2_CH2 event 0011 TMR2_CH1 event 0100 TMR3_TRGOUT event 0100...
Page 290: Conversion Sequence Management
AT32F403A/407 Series Reference Manual 19.4.3 Conversion sequence management Only one channel is converted at each trigger event by default, that is, OSN1-defined channel or PSN4- defined channel. The detailed conversion sequence modes are described in the following sections. With this, the channels can be converted in a specific order.
Page 291: Repetition Mode
AT32F403A/407 Series Reference Manual 19.4.3.3 Repetition mode The repetition mode is enabled by setting the RPEN bit in the ADC_CTRL2 register. When a trigger signal is detected, the ordinary channels will be converting repeatedly. This mode can work with the ordinary channel conversion in the sequence mode to enable the repeated conversion of the ordinary group.
Page 292: Data Management
AT32F403A/407 Series Reference Manual 19.4.4 Data management At the end of the conversion of the ordinary group, the converted value is stored in the ADC_ODT register. Once the preempted group conversion ends, the converted data of the preempted group is stored in the ADC_PDTx register.
Page 293: Master/Slave Mode
AT32F403A/407 Series Reference Manual 19.5 Master/Slave mode If Master/Slave mode is enabled, the master is triggered to work with the slave to do the channel conversion. The ADC_ODT register is used as a single interface obtaining the ordinary channel converted data of master/salve ADC. In this mode, ADC1 acts as a master while ADC2 as a slave.
Page 294: Alternate Preempted Trigger Mode
AT32F403A/407 Series Reference Manual Figure 19- 10 Regular simultaneous mode ADC1: OCLEN=2, OSN1=ADC1_IN0, OSN2=ADC1_IN1, OSN3=ADC1_IN2 Sampling ADC2: OCLEN=2, OSN1=ADC2_IN5, OSN2=ADC2_IN4, OSN3=ADC2_IN3 Conversion ADC1 ordinary ADC1 ordinary trigger trigger ADC1 ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC2 ADC2_IN5 ADC2_IN4 ADC2_IN3 ADC2_IN5 ADC2_IN4 ADC2_IN3 CCE flag set...
Page 295: Regular Switch Mode
AT32F403A/407 Series Reference Manual Combined regular simultaneous + alternate preempted trigger mode MSSEL bit in the ADC_CTRL1 register is used to select combined regular simultaneous + alternate preempted trigger mode. In this mode, trigger the regular group of the master to start regular simultaneous conversion of master/slave, or trigger the preempted group of the master continuously to allow the master/slave ADCs to convert the preempted group alternately.
Page 296: Adc Registers
AT32F403A/407 Series Reference Manual Figure 19- 14 Fast slow mode ADC1: SQEN=0, OSN1=ADC1_IN3, RPEN=1 Sampling ADC2: SQEN=0, OSN1=ADC2_IN3, RPEN=1 ADC1 ordinary Conversion trigger ADC1 ADC1_IN3 ADC1_IN3 ADC1_IN3 ADC1 CCE flag set ADC2_IN3 ADC2_IN3 ADC2_IN3 ADC2 ADC2 CCE flag set 14 ADCCLK Combined preempted simultaneous + slow switch mode MSSEL bit in the ADC_CTRL1 register is used to select combined preempted simultaneous + slow switch mode.
Page 297: Adc Status Register (Adc_Sts)
AT32F403A/407 Series Reference Manual 19.6.1 ADC status register (ADC_STS) Register Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at its default value. Ordinary channel conversion start flag This bit is set by hardware and cleared by software (writing Bit 4 OCCS rw0c...
Page 298 AT32F403A/407 Series Reference Manual Master/slave mode select 0000: Independnet mode 0001: Combined regular simultaneous + preempted simultaneous mode 0010: Combined regular simultaneous + alternate preempted trigger mode 0011: Combined preempted simultaneous + fast switch mode on regular group 0100: Combined preempted simultaneous + slow switch Bit 19: 16 MSSEL mode on regular group...
Page 299: Adc Control Register2 (Adc_Ctrl2)
AT32F403A/407 Series Reference Manual Channel conversion end interrupt enable 0: Channel conversion end interrupt disabled Bit 5 CCEIEN 1: Channel conversion end interrupt enabled Voltage monitoring channel select This filed is valid only when the VMSGEN is enabled. 00000: ADC_IN0 channel 00001: ADC_IN1 channel ……...
Page 300 AT32F403A/407 Series Reference Manual Trigger event select for ordinary channels conversion For ADC1 and ADC2, the trigger events are configured as follows: 0000: Timer 1 CH1 event 0001: Timer 1 CH2 event 0010: Timer 1 CH3 event 0011: Timer 2 CH2 event 0100: Timer 3 TRGOUT event 0101: Timer 4 CH4 event 0110: EXINT line 11/ TMR8_TRGOUT event...
Page 301 AT32F403A/407 Series Reference Manual Trigger event select for preempted channels conversion For ADC1 and ADC2, the trigger events are configured as follows: 0000: Timer 1 TRGOUT event 0001: Timer 1 CH4 event 0010: Timer 2 TRGOUT event 0011: Timer 2 CH1 event 0100: Timer 3 CH4 event 0101: Timer 4 TRGOUT event 0110: EXINT line 15/TMR8_CH4 event...
Page 302: Adc Sampling Time Register 1 (Adc_Spt1)
AT32F403A/407 Series Reference Manual Repition mode enable 0: Repition mode disabled When SQEN=0, a single conversion is done each time when a trigger event arrives; when SQEN=1, a group of conversion is done each timer when a trigger event arrives. Bit 1 RPEN 1: Repition mode enabled...
Page 303 AT32F403A/407 Series Reference Manual Sample time selection of channel ADC_IN15 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 17: 15 CSPT15 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN14 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles...
Page 304: Adc Sampling Time Register 2 (Adc_Spt2)
AT32F403A/407 Series Reference Manual 19.6.5 ADC sampling time register 2 (ADC_SPT2) Register Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value Sample time selection of channel ADC_IN9 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 29: 27 CSPT9...
Page 305 AT32F403A/407 Series Reference Manual Sample time selection of channel ADC_IN4 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 14: 12 CSPT4 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN3 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles...
Page 306: Adc Voltage Monitor High Threshold Register (Adc_ Vwhb)
AT32F403A/407 Series Reference Manual 19.6.6 ADC preempted channel data offset register x ( ADC_ PCDTOx) (x=1..4) Register Reset value Type Description Kept at its default value Bit 31: 12 Reserved 0x00000 resd Data offset for Preempted channel x Bit 11: 0 PCDTOx 0x000 Converted data stored in the ADC_PDTx = Raw converted...
Page 307: Adc Ordinary Sequence Register 3 (Adc_ Osq3)
AT32F403A/407 Series Reference Manual Number of 7th conversion in ordinary sequence Note: The number can be from 0 to 17. For example, if the Bit 4: 0 OSN7 0x00 number is set to 8, it means that the 7 conversion is ADC_IN8 channel.
Page 308: Digital-To-Analog Converter (Dac)
AT32F403A/407 Series Reference Manual 20 Digital-to-analog converter (DAC) 20.1 DAC introduction The DAC uses a 12-bit digital input to generate an analog output between 0 and reference voltage. The digital part of the DAC can be configured in 8-bit or 12-bit mode and can be used in conjunction with the DMA.
Page 309: Function Overview
AT32F403A/407 Series Reference Manual  Input/output configuration The digital inputs are linearly converted to analog voltage outputs by the DAC, and it is between 0 and V The analog DAC module is supplied by VDDA. The positive analog reference voltage REF+.
Page 310: Figure 20- 2 Lfsr Register Calculation Algorithm
AT32F403A/407 Series Reference Manual Figure 20- 2 LFSR register calculation algorithm The DxNBSEL [3: 0] bit in the DAC_CTRL register is set to mark partially or totally the LFSR data. The resulting value is then added up to the DHRx value without overflow and this value is loaded into the DAC_DxODT register.
Page 311: Dac Data Alignment
AT32F403A/407 Series Reference Manual 20.4.3 DAC data alignment The DAC supports a single DAC and dual DA mode. The data format is dependent on the selected configuration mode. Single DAC data format: 8-bit right alignment: load data into the DAC_DxDTH8R [7:0] 12-bit left alignment: load data into the DAC_DxDTH12L [15: 4] 12-bit right alignment: load data in the DAC_DxDTH12R [11: 0] Dual DAC data format:...
Page 312 AT32F403A/407 Series Reference Manual 0011: Unmask LSFR bit[3: 0] /Triangle amplitude is equal to 15 0100: Unmask LSFR bit[4: 0] /Triangle amplitude is equal to 31 0101: Unmask LSFR bit[5: 0] /Triangle amplitude is equal to 于 63 0110: Unmask LSFR bit[6: 0] /Triangle amplitude is equal to 127 0111: Unmask LSFR bit[7: 0] /Triangle amplitude is equal to 255...
Page 313 AT32F403A/407 Series Reference Manual DAC1 noise bit select These bits are used to select the mark bit in noise generation mode amplitude triangular-wave generation mode. 0000: Unmask LSFR bit0/Triangle amplitude is equal to 1 0001: Unmask LSFR bit[1:0]/Triangle amplitude is equal to 0010: Unmask LSFR bit[2: 0]/Triangle amplitude is equal to 7 0011: Unmask LSFR bit[3: 0]/Triangle amplitude is equal...
Page 314: Dac Software Trigger Register (Dac_Swtrg)
AT32F403A/407 Series Reference Manual 1: DAC1 output buffer disabled DAC1 enable 0: DAC1 disabled Bit 0 D1EN 1: DAC1 enabled 20.5.2 DAC software trigger register (DAC_SWTRG) Register Reset value Type Description Kept at its default value Bit 31: 2 Reserved 0x0000 0000 resd DAC2 software trigger...
Page 315: Dac2 12-Bit Left-Aligned Data Holding Register (Dac_ D2Dth12L)
AT32F403A/407 Series Reference Manual 20.5.7 DAC2 12-bit left-aligned data holding register (DAC_ D2DTH12L) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value Bit 15: 4 D2DT12L 0x000 DAC2 12-bit left-aligned data Bit 3: 0 Reserved resd Kept at its default value...
Page 316: Can
AT32F403A/407 Series Reference Manual 21 CAN 21.1 CAN introduction CAN (Controller Area Network) is a distributed serial communication protocol for real-time and reliable data communication among various nodes. It supports the CAN protocol version 2.0A and 2.0B. 21.2 CAN main features ...
Page 317 AT32F403A/407 Series Reference Manual = 1 x t ��_�� = (1 + BTS1[3: 0]) x t ��1 �� = (1 + BTS2[2: 0]) x t ��2 �� = (1 + BRDIV[11: 0]) x t �� Hard synchronization and resynchronization The start location of each bit in CAN nodes is always in synchronization segment by default, and the sampling is performed at the edge location of bit segment 1 and big segment 2 simulatenously.
Page 318: Figure 21- 2 Transmit Interrupt Generation
AT32F403A/407 Series Reference Manual Figure 21- 2 Transmit interrupt generation Inter-frame Inter-frame space or Data frame (standard identifier) space overload frame 44 + 8* N Ack field Data field CRC field Arbitration field Control field 8* N Inter-frame Inter-frame space or Data frame ( extended identifier) space overload frame...
Page 319: Interrupt Management
AT32F403A/407 Series Reference Manual 21.4 Interrupt management The CAN controller contains four interrupt vectors that can be used to enable or disable interrups by setting the CAN_INTEN register. Figure 21- 3 Transmit interrupt generation Figure 21- 4 Receive interrupt 0 generation RF0MN != 00 RFF0MIEN = 1 RF0FF = 1...
Page 320: Interrupt Management
AT32F403A/407 Series Reference Manual 21.5 Interrupt management The following information can be used as reference for CAN application development:  Debug control When the system enters the debug mode, the CAN controller stops or continues to work normally, depending on the CANx_PAUSE bit in the DEBUG_CTRL register or the PTD bit in the CAN_MCTRL register.
Page 321: Operating Modes
AT32F403A/407 Series Reference Manual 21.6.2 Operating modes The CAN controller has three operating modes:  Sleep mode After a system reset, the CAN controller is in Sleep mode. In this mode, the CAN clock is stopped to reduce power consumption and an internal pull-up resistance is disabled. However, the software can still access to the mailbox registers.
Page 322: Message Filtering
AT32F403A/407 Series Reference Manual 21.6.4 Message filtering The received message has to go through filtering by its identifier. If passed,the message will be stored in the correspoinding FIFOs. If not, the message will be discarded. The whole operation is done by hardware without using CPU resources.
Page 323: Figure 21- 11 16-Bit Identifier List Mode
AT32F403A/407 Series Reference Manual Figure 21- 11 16-bit identifier list mode CAN_FiFB1[15:8] CAN_FiFB1[7:0] CAN_FiFB1[31:24] CAN_FiFB1[23:16] CAN_FiFB2[15:8] CAN_FiFB2[7:0] CAN_FiFB2[31:24] CAN_FiFB2[23:16] SID[10:0] EID[17:15] Mapping Filter match number 14 filter banks have different filtering effects dependent on the bit width mode. For example, 32-bit identifier mask mode contains the filters numbered n while 16-bit identifier list mode contains the filters numbered n, n+1, n+2 and n+3.
Page 324: Message Transmission
AT32F403A/407 Series Reference Manual Priority rules When the CAN controller receives a frame of message, the message may pass through severl filters. In this case, the filter match number stored in the receive mailbox is determined according to the following priority rules: ...
Page 325: Figure 21- 12 Transmit Mailbox Status
AT32F403A/407 Series Reference Manual Figure 21- 12 Transmit mailbox status EMPTY Send request(TMSR = 1) Abort sending(TMxCT = 1) PENDING Is it the highest priority Abort sending(TMxCT = 1) SCHEDULED Is the bus idle Send success or send failed with Send failed with automatic SENDING auto retransmission forbidden...
Page 326: Message Reception
AT32F403A/407 Series Reference Manual 21.6.6 Message reception Register configuration The CAN_RFIx, CAN_RFCx, CAN_RFDTLx and CAN_RFDTHx registers can be used by user applications to obtain valid messages. Message reception The CAN controller boasts two FIFO with three levels to receive messages. FIFO rule is adopted. When the message is received correctly and has passed the identifier filtering, it is regarded as a valid message and is stored in the corresponding FIFO.
Page 327: Can Registers
AT32F403A/407 Series Reference Manual 21.7 CAN registers These peripheral registers must be accessed by word (32 bits). Table 21- 1 CAN register map and reset values Register Offset Reset value MCTRL 000h 0x0001 0002 MSTS 004h 0x0000 0C02 TSTS 008h 0x1C00 0000 00Ch 0x0000 0000...
Page 328: Can Control And Status Registers
AT32F403A/407 Series Reference Manual FACFG 21Ch 0x0000 0000 Reserved 220h~23Fh FB0F1 240h 0xXXXX XXXX FB0F2 244h 0xXXXX XXXX FB1F1 248h 0xXXXX XXXX FB1F2 24Ch 0xXXXX XXXX … … FB13F1 2A8h 0xXXXX XXXX FB13F2 2ACh 0xXXXX XXXX 21.7.1 CAN control and status registers 21.7.1.1 CAN master control register (CAN_MCTRL) Register...
Page 329: Can Master Status Register (Can_Msts)
AT32F403A/407 Series Reference Manual soon as a message is monitored on the CAN bus. Prohibit retransmission enable when sending fails enable 0: Retransmission is enabled. Bit 4 PRSFEN 1: Retransmission is disabled. Message discard rule select when overflow 0: The previous message is discarded. Bit 3 MDRSEL 1: The new incoming message is discarded.
Page 330 AT32F403A/407 Series Reference Manual Kept at its default value. Bit 7: 5 Reserved resd Enter doze mode interrupt flag 0: Sleep mode is not entered or no condition for flag set. 1: Sleep mode is entered. Note: Bit 4 EDZIF rw1c This bit is set by hardware only when EDZIEN=1 and the CAN enters Sleep mode.
Page 331: Can Transmit Status Register (Can_Tsts)
AT32F403A/407 Series Reference Manual 21.7.1.3 CAN transmit status register (CAN_TSTS) Register Reset value Type Description Transmit mailbox 2 lowest priority flag 0: Mailbox 2 is not given the lowest priority. Bit 31 TM2LPF 1: Lowest priority (This indicates that more than one mailboxes are pending for transmission, the mailbox 2 has the lowest priority.) Transmit mailbox 1 lowest priority flag...
Page 332 AT32F403A/407 Series Reference Manual 1: Transmit mailbox 2 arbitration lost Note: This bit is set when the mailbox 2 transmission failed due to an arbitration lost. It is cleared by software writing 1 or by hardware at the start of the next transmission Transmit mailbox 2 transmission success flag 0: Transmission failed 1: Transmission was successful.
Page 333: Can Receive Fifo 0 Register (Can_Rf0)
AT32F403A/407 Series Reference Manual Note: This bit is set by hardware when the transmission/abort request on mailbox 1 has been completed. It is cleared by software writing 1 or by hardware when a new transmission request is received. Clearing this bit will clear the TSMF1, ALMF1 and TEMF1 bits of mailbox 1.
Page 334: Can Receive Fifo 1 Register (Can_Rf1)
AT32F403A/407 Series Reference Manual by hardware when the FIFO 0 is released. Seting this bit by software has no effect when the FIFO 0 is empty. If there are more than two messages pending in the FIFO 0, the software has to release the FIFO 0 to access the second message.
Page 335: Can Interrupt Enable Register (Can_Inten)
AT32F403A/407 Series Reference Manual This bit is set by hardware when three messages are pending in the FIFO 1. It is cleared by software by writing 1. Kept at its default value. Bit 2 Reserved resd Receive FIFO 1 message num Note: These two bits indicate how many messages are pending in the FIFO 1.
Page 336: Can Error Status Register (Can_Ests)
AT32F403A/407 Series Reference Manual Kept at its default value. Bit 7 Reserved resd Receive FIFO 1 overflow interrupt enable 0: Receive FIFO 1 overflow interrupt disabled Bit 6 RF1OIEN 1: Receive FIFO 1 overflow interrupt enabled Note: The flag bit of this interrupt is the RF1OF bit. An interrupt is generated when this bit and RF1OF bit are set.
Page 337: Can Bit Timing Register (Can_Btmg)
AT32F403A/407 Series Reference Manual 110: CRC error 111: Set by software Note: This field is used to indicate the current error type. It is set by hardware according to the error condition detected on the CAN bus. It is cleared by hardware when a message has been transmitted or received successfully.
Page 338: Can Mailbox Registers
AT32F403A/407 Series Reference Manual 21.7.2 CAN mailbox registers This section describes the registers of the transmit and receive mailboxes. Refer to 21.6.5 for more information on register map. Transmit and receive mailboxes are the same except: RFFMN field in the CAN_RFCx register ...
Page 339: Transmit Mailbox Data Low Register (Can_Tmdtlx) (X=0
AT32F403A/407 Series Reference Manual sampled at the SOF transmission. Kept at its default value Bit 15: 9 Reserved 0xXX resd Transmit mailbox time stamp transmit enable 0: Time stamp is not sent 1: Time stamp is sent Note: Bit 8 TMTSTEN This valid...
Page 340: Receive Fifo Mailbox Data Length And Time Stamp Register (Can_Rfcx) (X=0
AT32F403A/407 Series Reference Manual Receive FIFO frame type indication 0: Data frame Bit 1 RFFRI 1: Remote frame Kept at its default value Bit 0 Reserved resd 21.7.2.6 Receive FIFO mailbox data length and time stamp register (CAN_RFCx) (x=0..1) Note: All the receive mailbox registers are read only. Register Reset value Type...
Page 341: Can Filter Mode Configuration Register (Can_Fmcfg)
AT32F403A/407 Series Reference Manual 21.7.3.2 CAN filter mode configuration register (CAN_FMCFG) Note: This register can be written only when FCS=1 in the CAN_FCTRL register (The filter is in configuration mode) Register Reset value Type Description Bit 31: 14 Reserved 0x00000 resd Kept at its default value Filter mode select...
Page 342: External Memory Controller
AT32F403A/407 Series Reference Manual 22 External memory controller 22.1 XMC introduction XMC peripheral block can translate the AHB signals into the external memory signals and vice versa. It boasts two chip-select signals for interfacing up to external memories at a time. The supported external memories include a NAND Flash and a static memory device featuring multiplexed signals or additional address latch function.
Page 343: Xmc Architecture
AT32F403A/407 Series Reference Manual 22.3 XMC architecture 22.3.1 Block diagram Figure 22- 1 XMC block diagram Address/Data bus XMC registers AHB XMC memory AHB interface interface Central memory XMC_A[0] controller XMC_A[23:16] XMC_D[15:0] XMC_NOE NOR/PSRAM memory interface XMC_NWE XMC_NWAIT XMC_NE[1] XMC_NE[4] XMC_NADV XMC_LB NAND bank2 memory interface...
Page 344: Address Mapping
AT32F403A/407 Series Reference Manual 22.3.2 Address mapping XMC address is divided into multiple memory banks, as shown below. Figure 22- 2 XMC memory banks Memory Address Memory banks chip select signals 6000 0000h NOR/PSRAM bank1 16 MB XMC_NE[1] 60FF FFFFh Reserved 6C00 0000h NOR/PSRAM bank4...
Page 345: Nor/Psram
AT32F403A/407 Series Reference Manual 22.4 NOR/PSRAM NOR/PSRAM offers multiple access modes with different timings to drive multiple memories including NOR Flash, SRAM, PSRAM and Cellular RAM. There are two banks, bank 1 and bank, with independent control registers. Such two banks can be accessed by means of different timings and different chip-select signals.
Page 346: Access Mode
AT32F403A/407 Series Reference Manual read/write Synchronous read Synchronous Split into two XMC accesses read Asynchronous read Asynchronous Use XMC_LB and XMC_UB write Asynchronous read/write Asynchronous PSRAM Split into two XMC accesses read/write Synchronous Use XMC_LB and XMC_UB write Synchronous read/write Synchronous Split into two XMC accesses read/write...
Page 347: Table 22- 9 Mode 1- Sram/Nor Flash Chip Select Timing Register (Xmc_ Bk1Tmg) Configuration
AT32F403A/407 Series Reference Manual Bit 10 WRAPEN: Wrapped enable Bit 9 NWPOL: NWAIT polarity Configure according to memory specifications Bit 8 SYNCBEN: Synchronous burst enable Bit 7 Reserved Bit 6 NOREN: NOR flash access enable EXTMDBW: External memory data Bit 5: 4 Configure according to memory specifications bus width Configure according to memory specifications.
Page 348: Figure 22- 3 Nor/Psarm Mode 1 Read Access
AT32F403A/407 Series Reference Manual Figure 22- 3 NOR/PSARM mode 1 read access Don t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_A[23：16] Address signals Memory address XMC_A[0] XMC_NOE High XMC_NWE Data signals XMC_LB XMC_UB Data from external memory High-Z XMC_D[15：0]...
Page 349: Figure 22- 4 Nor/Psarm Mode 1 Write Access
AT32F403A/407 Series Reference Manual Figure 22- 4 NOR/PSARM mode 1 write access Don t care DTST+1 ADDRST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_A[23：16] Address signals Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15：0] High-Z Mode 2...
Page 350: Figure 22- 5 Nor/Psarm Mode 2 Read Access
AT32F403A/407 Series Reference Manual Table 22- 11 Mode 2 — SRAM/NOR Flash chip select timing register (XMC_BK1TMG) configuration Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to Bit 19: 16 BUSLAT: Bus latency...
Page 351: Read/Write Operation With Different Timings
AT32F403A/407 Series Reference Manual Figure 22- 6 NOR/PSARM mode 2 write access Don t care DTST+1 ADDRST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15：0] High-Z 22.4.2.2 Read/write operation with different timings...
Page 352: Figure 22- 7 Nor/Psarm Mode A Read Access
AT32F403A/407 Series Reference Manual Table 22- 13 Mode A— SRAM/NOR Flash chip select timing register (XMC_BK1TMG) configuration Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x0 (Mode A) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16...
Page 353: Figure 22- 8 Nor/Psarm Mode A Write Access
AT32F403A/407 Series Reference Manual Figure 22- 8 NOR/PSARM mode A write access Don t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_A[23：16] Address signals Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15：0] High-Z Mode B...
Page 354: Figure 22- 9 Nor/Psarm Mode B Read Access
AT32F403A/407 Series Reference Manual Table 22- 16 Mode B— SRAM/NOR Flash chip select timing register (XMC_BK1TMG) configuration Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x1 (Mode B) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16...
Page 355: Figure 22- 10 Nor/Psarm Mode B Write Access
AT32F403A/407 Series Reference Manual Figure 22- 10 NOR/PSARM mode B write access Don t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB XMC_D[15：0] Data from XMC High-Z Mode C As configured in...
Page 356: Figure 22- 11 Nor/Psarm Mode C Read Access
AT32F403A/407 Series Reference Manual Table 22- 19 Mode C—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) configuration Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x2 (Mode C) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16...
Page 357: Figure 22- 12 Nor/Psarm Mode C Write Access
AT32F403A/407 Series Reference Manual Figure 22- 12 NOR/PSARM mode C write access Don t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15：0] High-Z Mode D...
Page 358: Figure 22- 13 Nor/Psarm Mode D Read Access
AT32F403A/407 Series Reference Manual Table 22- 22 Mode D—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) configuration Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x3 (Mode D) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16...
Page 359: Multiplexed Mode
AT32F403A/407 Series Reference Manual Figure 22- 14 NOR/PSARM mode D write access t care ADDRST+1 ADDRHT+1 DTST+1 HCLK HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15：0] High-Z 22.4.2.3 Multiplexed mode...
Page 360: Figure 22- 15 Nor/Psarm Multiplexed Mode Read Access
AT32F403A/407 Series Reference Manual Table 22- 25 Multiplexed mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) configuration Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the Bit 19: 16 BUSLAT: Bus latency...
Page 361: Synchronous Mode
AT32F403A/407 Series Reference Manual Figure 22- 16 NOR/PSARM multiplexed mode write access Don t care ADDRST+1 ADDRHT+1 DTST+2 HCLK HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address[23:16] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Address data Data from XMC XMC_D[15：0] Memory address[15:0]...
Page 362: Figure 22- 17 Nor/Psarm Synchronous Multiplexed Mode Read Access
AT32F403A/407 Series Reference Manual Table 22- 27 Synchronous mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode Bit 27: 24 DTLAT: Data latency Refer to Figure 22-17 and Figure 22-18. XMC_CLK cycle is HCLK cycle*CLKPSC.
Page 363: Nand
AT32F403A/407 Series Reference Manual Figure 22- 18 NOR/PSARM synchronous multiplexed mode write access DTLAT+1 Don t care XMC_CLK Clock XMC_CLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address[23:16] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Wait signal XMC_NWAIT Address data XMC_D[15：0] Memory address[15:0]...
Page 364: Access Timings
AT32F403A/407 Series Reference Manual section, and reads or writes the data from or to the data section. As the access addresses are transmitted through data bus, the HADDR is actually not associated with NAND Flash size, so theoretically the XMC has no limitation on the NAND Flash capacity accessible.
Page 365: Figure 22- 19 Nand Read Access
AT32F403A/407 Series Reference Manual Figure 22- 19 NAND read access RGST+2 HCLK RGWT+1 RGHT RGDHIZT+1 HCLK HCLK HCLK Chip select XMC_NCE[2] signal XMC_A[17:16] ALE/CLE If write XMC_NOE High Data XMC_NWE signals XMC_D[15：0] Data from XMC High-Z If read XMC_NOE Data High XMC_NWE signals...
Page 366: Ecc Computation
AT32F403A/407 Series Reference Manual Figure 22- 20 NAND wait functionality XMC check SPHT+1 XMC_NWAIT HCLK Chip select XMC_NCE[2] signal XMC_A[17] XMC_A[16] High XMC_NOE Data XMC_NWE signals Command Address3 Address0 Address1 Address2 XMC_D[7：0] High-Z XMC_NWAIT CPU write CPU write CPU write CPU write CPU write command to...
Page 367: Nor Flash And Psram Control Registers
AT32F403A/407 Series Reference Manual XMC_BK2TMGRG 0x068 0xFCFC FCFC XMC_BK2TMGSP 0x06C 0xFCFC FCFC XMC_BK2ECC 0x074 0x0000 0000 XMC_BK1TMGWR1 0x104 0x0FFF FFFF XMC_BK1TMGWR4 0x11C 0x0FFF FFFF XMC_EXT1 0x220 0x0000 0808 XMC_EXT4 0x22C 0x0000 0808 22.6.1 NOR Flash and PSRAM control registers 22.6.1.1 SRAM/NOR Flash chip select control register 1 (XMC_BK1CTRL1) Register...
Page 368: Sram/Nor Flash Chip Select Control Register 4
AT32F403A/407 Series Reference Manual access into two accesses. 0: Direct wrapped access is not allowed 1: Direct wrapped access is allowed NWAIT polarity This bit defines the polarity of the NWAIT signal in synchronous mode. Bit 9 NWPOL 0: NWAIT active low 1: NWAIT active high Synchronous burst enable This bit allowes synchronous access to Flash memories.
Page 369 AT32F403A/407 Series Reference Manual Others: Reserved. NWAIT enable during asynchronous transfer 0: NWAIT signal is disabled Bit 15 NWASEN 1: NWAIT signal is enable Read-write timing different Different timings are used for read and write operations, that is, the XMC_BK1TMGWR register is enabled. Bit 14 RWTD 0: Same timings for read and write operations...
Page 370: Sram/Nor Flash Chip Select Timing Register
AT32F403A/407 Series Reference Manual Memory bank enable 0: Memory bank disabled Bit 0 1: Memory bank enabled 22.6.1.3 SRAM/NOR Flash chip select timing register 1, 4 (XMC_BK1CTRL1, 4) Register Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value. Asynchronous mode This field is valid only when the RWTD bit is enabled.
Page 371: Sram/Nor Flash Write Timing Register
AT32F403A/407 Series Reference Manual 22.6.1.4 SRAM/NOR Flash write timing register 1, 4 (XMC_BK1 TMGWR1, 4) Register Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value. Asynchronous mode This field is valid only when the RWTD bit is enabled. 00: Mode A Bit 29: 28 ASYNCM...
Page 372: Nand Flash Control Registers
AT32F403A/407 Series Reference Manual 00000000: 1 HCLK cycle is inserted for consecutive write operations 00000001: 2 HCLK cycles are inserted for consecutive write operations …… 00001000: 9 HCLK cycles are inserted for consecutive write operations (default value) …… 11111111: 256 HCLK cycles are inserted for consecutive write operations 22.6.2 NAND Flash control registers 22.6.2.1...
Page 373: Interrupt Enable And Fifo Status Register 2 (Xmc_Bk2Is)
AT32F403A/407 Series Reference Manual 1: Enabled Kept at its default value. Bit 0 Reserved resd 22.6.2.2 Interrupt enable and FIFO status register 2 (XMC_BK2IS) Register Reset value Type Description Bit 31: 7 Reserved 0x000000 resd Kept at its default value. FIFO empty This bit is set by hardware when the FIFO is empty.
Page 374: Special Memory Timing Register 2 (Xmc_ Bk2Tmgsp)
AT32F403A/407 Series Reference Manual 00000000: 0 HCLK cycle is inserted 00000001: 1 additonal HCLK cycle is inserted …… 11111111: 255 additiona HCLK cycles are inserted Regular memory setup time This field defines the address seti[time when access to NAND Flash in a regular memory. 00000000: 0 HCLK cycle is inserted Bit 7: 0 RGST...
Page 375: Sdio Interface
AT32F403A/407 Series Reference Manual 23 SDIO interface 23.1 SDIO introduction The SD/SDIO MMC card host interface (SDIO) provides an interface between the AHB peripheral bus and MultiMediaCards (MMC), SD memory cards and SDIO cards. SD memory card and SDI/O card system specifications are available through the SD card association website www.sdcard.org.
Page 376: Figure 23- 1 Sdio "No Response" And "No Data" Operations
AT32F403A/407 Series Reference Manual Figure 23- 1 SDIO “no response” and “no data” operations From From From host host card to card to card to host SDIO_CMD Command Command Response SDIO_D Operation (No response) Operation (No data) Figure 23- 2 SDIO multiple block read operation Data from card From From...
Page 377: Sdio Main Features
AT32F403A/407 Series Reference Manual Figure 23- 4 SDIO sequential read operation From From host card to card to host Stop command stops data Data from card transfer to host SDIO_CMD Command Response Command Response SDIO_D Data stream Data stop operation Data transfer operation Figure 23- 5 SDIO sequential write operation From...
Page 378: Data Transfer Mode
AT32F403A/407 Series Reference Manual The card identification process is described as follows: The bus is activated to confirm whether the card is connected or not. The clock frequency is at 0- 400kHz during the card identification process. The SDIO host sends a SD card, SDI/O card or MMC card. Card Initialization SD card: The SDIO host sends CMD2 (ALL_SEND_CID) to obtain its unique CID number.
Page 379: Erase
AT32F403A/407 Series Reference Manual Data blocks will keep transferring until the host sends CMD12(STOP_TRANSMISSION). The stop command has an execution delay due to the serial command transmission and the data transfers stops after the end bit of the the stop command. Data block write During block write (CMD24-27), one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block.
Page 380: Table 23- 1 Lock/Unlock Command Structure
AT32F403A/407 Series Reference Manual bit in the CSD, part of the data can be protected, and the write protection can be changed by the application. The SET_WRITE_PROT commands set the write protection of the addressed group. The CLR_WRITE_PROT commands clear the write protection of the addressed group. The SEND_WRITE_PROT command is similar to a single block read command.
Page 381 AT32F403A/407 Series Reference Manual When the old password is matched, the new password and its size are saved into the PWD and PWD_LEN fields, respectively. When the old password sent is not correct (in size and/or content), the LOCK_UNLOCK_FAILED error bit is set in the SDIO_STS register, and the old password is not changed.
Page 382: Commands And Responses
AT32F403A/407 Series Reference Manual Forcing erase If the user forgot the password (PWD content), it is possible to access the card after clearing all the data on the card. This forced erase operation will erase all card data and all password data. Select a card using CMD7 (SELECT/DESELECT_CARD), if none is selected previously Define the block length with CMD16(SET_BLOCKLEN) to send in the 8-bit card lock/unlock mode, 8-bit PWD_LEN, and the number of bytes of the new password.
Page 383: Table 23- 3 Data Block Read Commands
AT32F403A/407 Series Reference Manual [31: 26] set to 0 [25: 24] access Used only for the MMC card to switch the [23: 16] index CMD6 SWITCH operation modes modify [15: 8] value EXT_CSD register [7: 3] set to 0 [2: 0] command set This command is used to switch a card between the standby state and the send SELECT/DESEL...
Page 384: Table 23- 5 Data Block Write Commands
AT32F403A/407 Series Reference Manual Table 23- 5 Data block write commands Response CMD index Type Parameter Abbreviation Description format This command is used to set the length [31: 0]=data block SET_ of data blocks (in bytes) for all block CMD16 length BLOCKLEN commands.
Page 385: Response Formats
AT32F403A/407 Series Reference Manual Table 23- 8 I/O mode commands Response CMD index Type Parameter Abbreviation Description format Used to write and read 8-bit (register) data fields. The command specifies a [31: 16]=RCA card and a register and provides the data [15]=register write for writing if the write flag is set.
Page 386: Table 23- 11 R1 Response
AT32F403A/407 Series Reference Manual Table 23- 11 R1 response [45: 40] [39: 8] [7：1] Field width Value Transmission Command Description Start bit Card status CRC7 End bit index 23.3.2.2.2 It is the same as R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands based on its state prior to the command reception.
Page 387: Sdio Functional Description
AT32F403A/407 Series Reference Manual Field width Value Card Numberof I/O Current Description Start bit Tx bit Res. Stuff bit Res. End bit ready functions memory 23.3.2.2.7 R5 (interrupt request) For MultiMedia card only. Code length = 48 bits. If the response is generated by the host, the RCA field in the parameter will be 0x0.
Page 388: Sdio Adapter
AT32F403A/407 Series Reference Manual Figure 23- 6 SDIO block diagram SDIO Adapter AHB Bus Control unit SDIO_CK Adapter DMA_req Command SDIO_CMD Interface Register Path DMA_ack SDIO_INT Data SDIO_D [ 7:0 ] Path HCLK SDIOCLK 23.3.3.1 SDIO adapter SDIO_CK is a clock to the MultiMedia/SD/SDIO car provided by the host. One bit of command or data is transferred on both command and data lines with each clock cycle.
Page 389: Table 23- 19 Command Formats
AT32F403A/407 Series Reference Manual register where the CLKDIV bit is used to define the divider factor between the SDIOCLK and the SDIO output clock. If BYPSEN = 0, the SDIO_CK output signal is driven by the SDIOCLK divided according to the CLKDIV bit; if BYPSEN = 1, the SDIO_CK output signal is directly driven by the SDIOCLK. The HFCEN is set to enable hardwar flow control feature in order to avoid the occurrence of an error at transmission underflow or reception overflow.
Page 390: Figure 23- 7 Command Channel State Machine (Ccsm)
AT32F403A/407 Series Reference Manual Table 23- 22 Command path status flags Flag Description CMDRSPCMPL A response is already received (CRC OK) CMDFAIL A command response is already received (CRC fails) CMDCMPL A command is sent (does not require a response) CMDTIMEOUT Command response timeout (64 SDIO_CK cycles) DOCMD...
Page 391: Figure 23- 8 Sdio Command Transfer
AT32F403A/407 Series Reference Manual Figure 23- 8 SDIO command transfer At least 8 SDIO_CK cycles SDIO_CMD Response CPSM status Idle Send Wait Receive Idle Send Data path The data path subunit transfers data between the host and the cards. The databus width can be configured using the BUSWS bit in the SDIO_CLKCTRL register.
Page 392: Data Buf
AT32F403A/407 Series Reference Manual  Busy: The DCSM waits for the CRC flag. If the DCSM receives a correct CRC status and is not busy, it will enter the Wait_S state. If it does not receive a correct CRC status or a timeout occurs while the DCSM is in the busy state, a CRC fail flag or timeout flag is generated.
Page 393: Hardware Flow Control
AT32F403A/407 Series Reference Manual and then program the SDIO data control register (SDIO_DTCTRL): TFREN=1 (enable the SDIO card host to send data), TFRDIR=0 (from the controller to the card), TFRMODE=0 (block data transfer), DMAEN=1 (enable DMA), BLKSIZE=9 (512 bytes), and wait from SDIO_STS [10]=DTBLKCMPL.
Page 394: Sdio Registers
AT32F403A/407 Series Reference Manual SDIO interrupts There is a pin with interrupt feature on the SD interface in oder to enable the SD I/O card to interrupt the MultiMedia card/SD module. In 4-bit SD mode, this pin is SDIO_D1. The SD I/O interrupts are detected when the level is active.
Page 395: Sdio Clock Control Register (Sdio_ Clkctrl)
AT32F403A/407 Series Reference Manual 23.4.2 SDIO clock control register (SDIO_ CLKCTRL) The SDIO_CLKCTRL register controls the SDIO_CK output clock. Register Reset value Type Description Bit 31: 17 Reserved 0x0000 resd Kept at its default value. Clock division This field is set or cleared by software. It defines the clock division relations between the SDIOCLK and the Bit 16: 15 CLKDIV...
Page 396: Sdio Argument Register (Sdio_Arg)
AT32F403A/407 Series Reference Manual CLKCTRL register does not control the SDIO_CK. 23.4.3 SDIO argument register (SDIO_ARG) The SDIO_ARG register contains 32-bit command argument, which is sent to a card as pat of a command. Register Reset value Type Description Command argument Command argument is sent to a card as part of a command.
Page 397: Sdio Command Response Register (Sdio_Rspcmd)
AT32F403A/407 Series Reference Manual can vary according to the type of response. The software will distinguish the tpe fo response accorind to the command sent. 23.4.5 SDIO command response register (SDIO_RSPCMD) The SDIO_RSPCMD register contains the command index of the last command response received. If the command response transmiision does not contain the command index (long or OCR response), the SDIO_RSPCMD field is unknon, alghout it should have contained 111111b (the value of the reserved field from a response)
Page 398: Sdio Data Control Register (Sdio_Dtctrl)
AT32F403A/407 Series Reference Manual 23.4.9 SDIO data control register (SDIO_DTCTRL) The SDIO_DTCTRL register controls the data channel statue machine (DCSM). Register Reset value Type Description Bit 31: 12 Reserved 0x00000 resd Kept at its default value. SD I/O enable functions This bit is set or cleared by software.
Page 399: Sdio Data Counter Register (Sdio_Dtcntr)
AT32F403A/407 Series Reference Manual block data transfer. 0: Disabled 1: Enabled Data transfer direction selection This bit is set or cleared by software. If this bit is set, data transfer is from a card to a controller; if this bit is cleared, Bit 1 TFRDIR data transfer is from a controlle to a card.
Page 400: Sdio Clear Interrupt Register (Sdio_Intclr)
AT32F403A/407 Series Reference Manual Transmit BUF half empty: At least 8 words can be written to the BUF. This flag bit can Bit 14 TXBUFH be used as DMA request. Data receive in progress Bit 13 DORX Data transmit in progress Bit 12 DOTX Command transfer in progress...
Page 401: Sdio Interrupt Mask Register (Sdio_Inten)
AT32F403A/407 Series Reference Manual 23.4.13 SDIO interrupt mask register (SDIO_INTEN) The SDIO_INTEN register determines which status bit generates an interrupt by setting the corresponding bit. Register Reset value Type Description Bit 31: 23 Reserved 0x000 resd Kept at its default value. SD I/O mode received interrupt enable This bit is set or cleared by software to enable/disable the SD I/O mode received interrupt function.
Page 402 AT32F403A/407 Series Reference Manual 1: Enabled Data transmit acting interrupt enable This bit is set or cleared by software to enable/disable the Data transmit acting interrupt. Bit 12 DOTXIEN 0: Disabled 1: Enabled Command acting interrupt enable This bit is set or cleared by software to enable/disable the Command acting interrupt.
Page 403: Sdiobuf Counter Register (Sdio_Bufcntr)
AT32F403A/407 Series Reference Manual 1: Enabled Data CRC fail interrupt enable This bit is set or cleared by software to enable/disable the Data CRC fail interrupt. Bit 1 DTFAILIEN 0: Disabled 1: Enabled Command CRC fail interrupt enable This bit is set or cleared by software to enable/disable the Command CRC fail interrupt.
Page 404: Universal Serial Bus Full-Seed Device Interface (Usbfs)
AT32F403A/407 Series Reference Manual 24 Universal serial bus full-seed device interface (USBFS) 24.1 USBFS introduction The USBFS implements the USB2.0 full-speed protocols. At the bus speed of 1212Mb/s, it supports control transfer, bulk transfer, synchronous transfer and interrupt transfer, as well as USB suspend/resume.
Page 405: Endpoint Configuration
AT32F403A/407 Series Reference Manual 24.3.2 Endpoint configuration The USBFS supports up to 8 bidirectional and 16 unidirectional endpoints (8 IN and 8 OUT). Each point has its corresponding USBFS endpoint n register (USBFS_EPTn) that is used to store the endpoint status.
Page 406: Double-Buffered Endpoints
AT32F403A/407 Series Reference Manual describe the buffer and data length of the endpoint receive/transmit. The structure of a regular endpoint register buffer description field is shown as follows (dual buffer description table is detailed in the next section): Endpoint n: TnADDR Reserved TnLEN...
Page 407: Sof Output
AT32F403A/407 Series Reference Manual RnLEN_1 SBUF=0, USBFS uses RnADDR_1 and RnLEN_1, while the user application uses RnADDR_0 and RnLEN_0 Double-buffered IN endpoints: SBUF corresponds to bit 14 in the USB_EPTn  SBUF=1, USBFS uses TnADDR_0 and TnLEN_0, while the user application uses TnADDR_1 and TnLEN_1 SBUF=0, USBFS uses TnADDR_1 and TnLEN_1, while the user application uses TnADDR_0 and TnLEN_0...
Page 408: Usbfs Endpoint N Register (Usbfs_Eptn), N=[0
AT32F403A/407 Series Reference Manual USBFS_EPT4 0x10 0x0000 USBFS_EPT5 0x14 0x0000 USBFS_EPT6 0x18 0x0000 USBFS_EPT7 0x1C 0x0000 USBFS_CTRL 0x40 0x0003 USBFS_INTSTS 0x44 0x0000 USBFS_SOFRNUM 0x48 0x0XXX USBFS_DEVADDR 0x4C 0x0000 USBFS_BUFTBL 0x50 0x0000 USBFS_CFG 0x60 0x0000 USBFS_TnADDR [USB_BUFTBL] x 2 + n x 16 0xXXXX USBFS_TnLEN [USB_BUFTBL] x 2 + n x 16 + 4...
Page 409: Usbfs Control Register (Usbfs_Ctrl)
AT32F403A/407 Series Reference Manual USB endpoint extend function is used for Bulk and Control transfers. For Bulk transfer, this bit is set to indicate that double-buffered is enabled. For Control transfer, if this bit is set, it detects whether the data length in the SETUP transaction is 0 or not, a STALL is returned if the value is not 0.
Page 410: Usbfs Interrupt Status Register (Usbfs_Intsts)
AT32F403A/407 Series Reference Manual Kept at its default value. Bit 7: 5 Reserved resd Generate Resume request In suspend mode, the software can set this bit to send a Bit 4 GRESUME resume signal to the host in order to wake up it. It must be cleared between 10ms and 15ms.
Page 411: Usbfs Sof Frame Number Register (Usbfs_Sofrnum)
AT32F403A/407 Series Reference Manual 1: No SOF has been received for more than 1ms. Kept at its default value. Bit 7: 5 Reserved resd IN/Out transaction When TC complete interruput is generated, this bit is used to indicate whether IN/OUT transcation has been Bit 4 INOUT completed.
Page 412: Usbfs Transmission Buffer First Address Register (Usbfs_Tnaddr)
AT32F403A/407 Series Reference Manual DP pull-up off 0: DP pull-up resistance enabled Bit 1 1: DP pull-up resistance disabled SOF output enable 0: No SOF pulse output Bit 0 SOFOUTEN 1: SOF pulse output to the pin 24.5.8 USBFS transmission buffer first address register (USBFS_TnADDR) Register Reset value...
Page 413: Hick Auto Clock Calibration (Acc)
AT32F403A/407 Series Reference Manual 25 HICK auto clock calibration (ACC) 25.1 ACC introduction HICK auto clock calibration (HICK ACC), which uses the SOF signal (1 ms of period) generated as a reference signal, implements the sampling and calibration for the HICK clocks. The main pupose of this module is to provide a clock of 48MHz±0.25% for the USB device.
Page 414: Functional Description
AT32F403A/407 Series Reference Manual 25.4 Functional description Auto clock calibration (HICK ACC), which uses the SOF signal (1 ms of period) generated as a reference signal, implements the sampling and calibration for the HICK clocks. In particular, the HICK clock frequency can be calibrated to a precision of ±0.25% so as to meet the needs of the high-precision clock applications such as USB.
Page 415: Principle
AT32F403A/407 Series Reference Manual Figure 25- 2 ACC block diagram CRM_HICKCAL HICKCAL CALON CRM_HICKTRIM HICKTRIM 控制寄存器(CR） STEP ENTRIM ACC_HICKCAL USB_SOF CALIBRATION CONTROL ACC_HICKTRIM HICKCLK CALRDY INTERRUPT RSLOST CONTROL CALRDYIEN EIEN 25.5 Principle USB_SOF period signal: 1ms of period must be accurate, which is a prerequisite of the normal operaion of an auto calibration module.
Page 416: Register Description
AT32F403A/407 Series Reference Manual Return: After cross operation is completed, the actual value closest to C2 can be obtained by comparing the difference (calculated as absolute value) between the actual sampling value and C2 before and after crossing C2 so as to get the best calibration value HICKCAL or HICKTRIM. If the difference after crossing is less than the one before crossing C2, the calibration value after crossing prevails, and stops the calibration process until the next condition for auto calibration appears.
Page 417: Control Register 1 (Acc_Ctrl1)
AT32F403A/407 Series Reference Manual CALON=1. Internal high-speed clock calibration ready 0: Interal 8MHz oscillator calibration is not ready 1: Interal 8MHz oscillator calibration is ready Note: This bit is set by hardware to indicate that internal Bit 0 CALRDY 8MHz oscillator has been calibrated to the frequency closest to 8MHz.
Page 418: Control Register 2 (Acc_Ctrl2)
AT32F403A/407 Series Reference Manual 25.6.3 Control register 2 (ACC_CTRL2) Register Reset value Type Description Forced to 0 by hardware Bit 31: 14 Reserved 0x00000 resd Internal high-speed auto clock trimming This field is read only, but not written. Internal high-speed clock is adjusted by ACC module, which is added to the ACC_HICKCAL[7: 0] bit.
Page 419: Compare Value 3 (Acc_C3)
AT32F403A/407 Series Reference Manual 25.6.6 Compare value 3 (ACC_C3) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Forced to 0 by hardware Compare 3 This value is the upper boundary for triggering calibration. When the number of clock sampled by ACC in 1ms period is greater than or equal to C3, auto calibration is triggered Bit 15: 0 0x1F54...
Page 420: Ethernet Media Access Control (Emac)
AT32F403A/407 Series Reference Manual 26 Ethernet media access control (EMAC) This module applies only to AT32F407 series, not including AT32F403A series. 26.1 EMAC introduction Copyright Synopsys, Inc. All rights reserved. The Ethernet peripheral enables the AT32F407 to transmit and receive data (10/100Mbps) through Ethernet in compliance with IEEE 802.3-2002 standard.
Page 421: Emac Functional Description
AT32F403A/407 Series Reference Manual  Supports checking IPv4 header checksum and IPv4, TCP, UDP or ICMP (packaged in IPv4 or IPv6 data formats) checksum  Supports Ethernet frame time stamp as defined in IEEE 1588-2008. 64-bit time stamps are recorded in the transmit or receive status ...
Page 422: Figure 26- 2 Smi Interface Signals
AT32F403A/407 Series Reference Manual Figure 26- 2 SMI interface signals EMAC SMI MDIO Before write operation, PHY address, MII register and EMAC_MACMIIDT register must be configured first, followed by the MII MW and MB bits, and then the SMI interface will transfer the PHY address, PHY register address and data to the PHY.
Page 423: Table 26- 2 Transmit Interface Signal Encode
AT32F403A/407 Series Reference Manual MII_TX_CLK: Transmit data clock signal. This clock is 2.5MHz at 10Mbps speed; 25MHz at 100Mbps speed. MII_RX_CLK: Receive data clock signal. This clock is 2.5MHz at 10Mbps speed; 25MHz at 100Mbps speed. MII_TX_EN: Transmit enable signal. It must be set synchronously with the start bit of the preamble, and must remain asserted until all bits to be transmitted are transmitted.
Page 424: Figure 26- 4 Reduced Media-Independent Interface Signals
AT32F403A/407 Series Reference Manual Figure 26- 4 Reduced media-independent interface signals MII/RMII selection and clock sources Either the MII or RMII mode can be selected using the 23 bit MII_RMII_SEL in the IOMUX_REMAP register. The MII/RMII mode must be selected when the Ethernet controller is in reset state or before the clock is enabled.
Page 425: Figure 26- 7 Rmii Clock Sources (Provide By Clkout Pin)
AT32F403A/407 Series Reference Manual Figure 26- 7 RMII clock sources (provide by CLKOUT pin) AT32F407 REF_CLK 25MHz CLKOUT 50MHz Figure 26- 8 RMII clock sources (provide by an external crystal oscillator) EMAC pin allocation and multiplexing Table 26- 4 Ethernet peripheral pin configuration (black: default red: remapping signals) EMAC signal RMII Pin description...
Page 426: Emac Frame Communication
AT32F403A/407 Series Reference Manual 26.2.2 EMAC frame communication Frame format Figure 26-9 shows the MAC frame format and tagged MAC frame format (Refer to IEEE 802.C-2002 for more information on MAC frame formats) Figure 26- 9 MAC frame format Figure 26- 10 Tagged MAC frame format Preamble 7bytes 1byte...
Page 427: Table 26- 5 Destination Address Filtering
AT32F403A/407 Series Reference Manual upper CRC bits to index the HASH table. A value of 000000 corresponds to bit 0 in the HASH table register, and a value of 111111 corresponds to bit 63 in the HASH table register. If the corresponding bit in the HASH table relative to the CRC value is set to 1, it indicates that the frame has passed through the HASH filter, otherwise, it has failed the HASH filter.
Page 428: Table 26- 6 Source Address Filtering
AT32F403A/407 Series Reference Manual Fail on HASH filter match and drop PAUSE frames if PCF= 0x Fail on HASH or perfect/group filter match and drop PAUSE frames if PCF= 0x Table 26- 6 Source address filtering Frame type SAIF SA filter operation Pass all frames Pass status on perfect/group filter match but do not drop frames that failed...
Page 429 AT32F403A/407 Series Reference Manual In MII mode, if a collision occurs at any time from the beginning of a frame to the end of the CRC, the collision signal is sent to the EMAC core. The EMAC core will send a 32-bit jam signal of 0x5555 5555 to informe all other stations on the LAN that a collision has occurred.
Page 430 AT32F403A/407 Series Reference Manual Transmit status word and time stamp At the EMAC controller has completed the transmission of the Ethernet frame, the transmit status is given to the application. If IEEE 1588 time stamp is enabled, a 64-bit time stamp, along with the transmit status, will be written to the transmit descriptor.
Page 431 AT32F403A/407 Series Reference Manual The result of this operation is indicated by the checksum error status bit in the transmit status vector (TDES0 bit 12). The data checksum error status bit is set when either of the following is detected: 1.
Page 432: Ethernet Frame Transmission And Reception Using Dma
AT32F403A/407 Series Reference Manual 1. Received TCP, UDP or ICMP data length does not match that of the IP headers 2. The calculated checksum does not equal the value of the TCP, UDP or ICMP checksum field Receive flow control In Full-duplex mode, the MAC detects the receiving Pause frame and pauses the frame transmission according to the delay specified within the received Pause frame.
Page 433: Figure 26- 11 Descriptor For Ring And Chain Structure
AT32F403A/407 Series Reference Manual reception process, which has its respective descriptor list. The descriptor list is usually stored in the system buffer area (SRAM). When the transmission and reception is enabled, the DMA polls the descriptor table through the transmit and receive poll register to start the transmission and reception process.
Page 434 AT32F403A/407 Series Reference Manual AHB host data alignment The DMA always initiates transfers with address aligned to the bus width. But the start address of the buffers can abligned to any of the four bytes. Example of buffer read: If the transmit buffer address is 0x2000 0AA3, and 15 bytes are to be ...
Page 435 AT32F403A/407 Series Reference Manual TXDMA operation: non-OSF mode The TXDMA proceeds as follows, in default moe: The application sets up the Enthernet frame data buffer and the transmit descriptor (TDES0- TDES3), and sets the OWN bit (TDES0[31]) Once the SSTC is set (EMAC_DMAOPM bit [13]), the DMA enables transmission. The DMA polls the transmit descriptor to get a frame to be transmitted.
Page 436: Figure 26- 12 Transmit Descriptors
AT32F403A/407 Series Reference Manual Transmit frame processing Ethernet frames stored in the transmit buffer must contain destination address, source address, correct type/length field and valid data. As for whether to include CRC value, it depends on the transmit descriptor. If the transmit descriptor requires the EMAC core to disable CRC or pad insertion, the buffer must contain the CRC.
Page 437 AT32F403A/407 Series Reference Manual When set, this bit indicates that the buffer contains the first segment of the frame Disable CRC When set, the MAC does not append a CRC field to the end of the transmitted Bit 27 frame. This bit is valid only when the FS bit is set (TDES0[28]=1). Disable pad 0: The MAC automatically adds padding to a frame shorter than 64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]).
Page 438 AT32F403A/407 Series Reference Manual When set, this bit indicates that the MAC transmitter has experienced a jabber timeout. This bit is set only when the JAD bit is not set in the EMAC_MACCTRL register. Frame flushed Bit 13 When set, this bit indicates that the DMA or MTL flushed the frame in the FIFO due to a flush command given by the CPU.
Page 439 AT32F403A/407 Series Reference Manual this buffer and uses buffer 2 or the next buffer, depending on the TDES0[20] bit. TDES2: Transmit descriptor word2 TDES2 contains the address pointer to the first buffer of the descriptor or it contains the lower 32-bit time stamp data.
Page 440 AT32F403A/407 Series Reference Manual the LS bit set. The receive controller checks the latest receive descriptors, if the DMA owns the descriptor, the receive controller will return to Step 4. If the CPU owns the descriptor, the RXDMA will enter suspend state and set the receive buffer unavailable bit, and the controller will flush the received frames if the receive frame flushing feature is enabled.
Page 441: Figure 26- 13 Rxdma Descriptor Structure
AT32F403A/407 Series Reference Manual Figure 26- 13 RXDMA descriptor structure RDES 0 Status [30:0] Rers. Control Contr RDES 1 Buffer 2 byte count [28:16] Rers. Buffer 1 byte count [12:0] [30:29] [15:14] RDES 2 Buffer 1 address [31:0] RDES 3 Buffer 2 address [31:0] or next descriptor address[31:0] RDES0: Receive descriptor word0 RDES0 contains the receive frame state, the frame length and the descriptor ownership information.
Page 442: Table 26- 7 Receive Descriptor 0
AT32F403A/407 Series Reference Manual marked as a VLAN frame by the MAC. First descriptor When set, this bit indicates that this descriptor contains the first buffer of the frame. Bit 9 If the size of the first buffer is 0, the seond buffer contains the beginning of the frame. If the size of the seond buffer is also 0, the buffer of the next descriptor contains the beginning of the frame.
Page 443 AT32F403A/407 Series Reference Manual A type frame is neither IPv4 nor IPv6 (the checksum offload bypasses checksum inspection) Reserved RDES1: Receive descriptor 1 Name Type Description Disable interrupt on completion When set, this bit prevents setting the Ethernet DMA status register’s RECV bit (EMAC_DMASTS) for the received frame pointed to by this descriptor.
Page 444: Ethernet Frame Transmission And Reception Using Dma
AT32F403A/407 Series Reference Manual stored in memory). 26.2.4 Ethernet frame transmission and reception using DMA The EMAC enters power-off mode when the PD bit is enabled in the EMAC_MACPMTCTRLSTS register. In this mode, all received frames are dropped by the EMAC and they are not forwarded to the application. PMT supports the reception of remote wakeup frames and AMD Magic Packet frames and uses them to wake up the EMAC from power-off mode.
Page 445: Ieee1588 Precision Time Protocol
AT32F403A/407 Series Reference Manual When a remote wakeup frame is received, the EMAC will move from sleep mode to normal mode. At the same time, the RRWF bit (bit 6) is set in the EMAC_MACPMTCTRLSTS register, indicating that a remote wakeup frame is received.
Page 446 AT32F403A/407 Series Reference Manual Reference clock source According to IEEE158 standard, the system requires a reference time in a 64-bit format as the current time record, with the upper 32 bits time information in seconds, and the lower 32 bits time information in nanoseconds.
Page 447: Figure 26- 15 System Time Update Using The Fine Correction Method
AT32F403A/407 Series Reference Manual Figure 26- 15 System time update using the fine correction method The subsecond register update frequency requires 50 MHz to achieve 20 ns accuracy for the system clock update circuit. Therefore, if the system clock frequency is 70 MHz, the ratio is calculated as 70/50=1.4.
Page 448: Figure 26- 16 Ptp Trigger Output To Tmr2 Itr1 Connection
AT32F403A/407 Series Reference Manual The frequency compensation value for the addend register, FreqCompensationValue FreqCompensationValue = FreqScaleFactor ×FreqCompensationValue This algorithm comes with a self-correction feature. In theory, the frequency can be locked at a synchronized cycle. However, it may makes several cycles to synchronize the slave device. System time initialization procedure Mask the time stamp trigger interrupt by setting the bit 9 in the EMAC_MAIMR register.
Page 449: Emac Interrupts
AT32F403A/407 Series Reference Manual PTP second pulse output signal Refer to the EMAC_PTPPPSCR register descriptor for more information about PTP pulse second output. The following contents are based on the fact wen the emac_pps_sel bit (bit 15) is cleared in the CRM_MISC3 register.
Page 450: Emac Registers
AT32F403A/407 Series Reference Manual Figure 26- 18 Ethernet interrupts FBEI FBEE MMCI PMTI TSTI RWTE RBUE 26.3 EMAC registers Table 26-8 shows the Ethernet register map and its reset values. The peripheral registers can be accessed by bytes (8-bit), half words (16-bit) or words (32-bit). Table 26- 8 Ethernet register map and its reset values Register Offset...
Page 451 AT32F403A/407 Series Reference Manual EMAC_MAIMR 0x3C 0x0000 0000 EMAC_MACA0H 0x40 0x0010 FFFF EMAC_MACA0L 0x44 0xFFFF FFFF EMAC_MACA1H 0x48 0x0000 FFFF EMAC_MACA1L 0x4C 0xFFFF FFFF EMAC_MACA2H 0x50 0x0000 FFFF EMAC_MACA2L 0x54 0xFFFF FFFF EMAC_MACA3H 0x58 0x0000 FFFF EMAC_MACA3L 0x5C 0xFFFF FFFF EMAC_MMCCTRL 0x100 0x0000 0000...
Page 452: Ethernet Mac Configuration Register (Emac_Macctrl)
AT32F403A/407 Series Reference Manual EMAC_DMAMFBOCNT 0x1020 0x0000 0000 EMAC_DMACTD 0x1048 0x0000 0000 EMAC_DMACRD 0x104C 0x0000 0000 EMAC_DMACTBADDR 0x1050 0x0000 0000 EMAC_DMACRBADDR 0x1054 0x0000 0000 26.3.1 Ethernet MAC configuration register (EMAC_MACCTRL) The Ethernet MAC configuration register defines the receive and transmit operation modes. A delay greater than 4 us is required for two consecutive write accesees to this register.
Page 453 AT32F403A/407 Series Reference Manual mode. This bit is reserved (with default value RO) when the MAC is configured as “For full-duplex mode only” mode. Loopback Mode When this bit is set, the MAC MII operates in loopback mode. The MII receive clock input (clk_rx_i) is required for Bit 12 the loopback mode to work normally, for the transmit clock is not looped-back internally.
Page 454: Ethernet Mac Frame Filter Register (Emac_ Macfrmf)
AT32F403A/407 Series Reference Manual retransmission attempt. r takes the random integer value in the range 0 ≤ r < 2k. Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a frame abort status and sets the excessive deferral error flag bit in the transmit frame status when the transmit state machine is delayed for more than 24288 bit times in 10/100 Mbit/s mode.
Page 455 AT32F403A/407 Series Reference Manual HUC bit. When this bit is cleared, if the HUC or HMC bit is set, only frames that match the hash filter can pass address filter. Source Address Filter When this bit is set, the MAC compares the source address of the received frame with the value programmed in the enabled source address registers.
Page 456: Ethernet Mac Hash Table High Register (Emac_Machth)
AT32F403A/407 Series Reference Manual filtering of the received multicast frames according to the hash table. When this bit is cleared, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the destination address field with the values programmed in the destination registers.
Page 457: Ethernet Mac Mii Address Register (Emac_Macmiiaddr)
AT32F403A/407 Series Reference Manual 26.3.5 Ethernet MAC MII address register (EMAC_MACMIIADDR) The Ethernet MAC MII address register controls the external PHY through the management interface. Register Reset value Type Description Kept at its default value. Bit 31: 16 Reserved 0x0000 resd PHY Address This field indicates which of the 32 possible PHY devices...
Page 458: Ethernet Mac Mii Data Register (Emac_Macmiidt)
AT32F403A/407 Series Reference Manual 26.3.6 Ethernet MAC MII data register (EMAC_MACMIIDT) The Ethernet MAC MII data register stores data to be written to the PHY register located at the address specified in the EMAC_MACMIIADDR register. EMAC_MACMIIDT register also stores data read out from the PHY registers.
Page 459: Ethernet Mac Vlan Tag Register (Emac_Macvlt)
AT32F403A/407 Series Reference Manual address0 low registers. When this bit is cleared, the MAC detects only a Pause frame with a unique multicast address. Note: If the multicast address of the received frame does not match the unique multicast address, the MAC will not process the Pause frame.
Page 460: Ethernet Mac Remote Wakeup Frame Filter Register (Emac_Macrwff)
AT32F403A/407 Series Reference Manual VLAN hash filtering. VLAN Tag Identifier (for receive frames) This field contains the 802.1Q VLAN tag to identify VLAN frames, which is compared with the 15 and 16 bytes of the received VLAN frames, described as follows: Bit [15: 13]: User priority Bit 12: Canonical format indicator (CFI) or drop eligible indicator (DEI)
Page 461: Ethernet Mac Interrupt Status Register (Emac_ Macists)
AT32F403A/407 Series Reference Manual a read access to this register. Received Magic Packet When this bit is set, it indicates that the power management event is generated because of the reception Bit 5 of a Magic packet. This bit is cleared by a read access to this register.
Page 462: Ethernet Mac Interrupt Mask Register (Emac_ Maimr)
AT32F403A/407 Series Reference Manual 26.3.12 Ethernet MAC interrupt mask register (EMAC_ MAIMR) The Ethernet MAC interrupt mask register is used to mask the interrupt signal generated due to the corresponding event in the EMAC_MACISTS register Register Reset value Type Description Bit 15: 10 Reserved 0x00...
Page 463: Ethernet Mac Address 1 Low Register (Emac_Maca1H)
AT32F403A/407 Series Reference Manual Description Register Reset value Type Address Enable When this bit is set, the address filter uses the second MAC address for a perfect filtering. Bit 31 When this bit is cleared, the address filter will ignore the address for filtering.
Page 464: Ethernet Mac Address 2 Low Register (Emac_Maca2L)
AT32F403A/407 Series Reference Manual comparison with the source address field of the received frame. When this bit is cleared, the MAC address 2 [47: 0] is used for comparison with the destination address field of the received frame. Mask Byte Control These bits are mask control bits for comparison with each of the MAC address bytes.
Page 465: Ethernet Mac Address 3 Low Register (Emac_Maca3L)
AT32F403A/407 Series Reference Manual When this bit is set, the MAC does not compare the corresponding byte of the received DA/SA with the contents of the MAC address 3 register. Each control bit is used for controlling the mask of the bytes as follows: Bit 29: EMAC_MACA3H [15: 8] Bit 28: EMAC_MACA3H [7: 0] Bit 27: EMAC_MACA3L[31: 24]...
Page 466 AT32F403A/407 Series Reference Manual These bits are applicable only when the USB bit is set. Fixed Burst This bit controls whether the AHB master interface performs fixed burst transfers or not. When this bit is set, Bit 16 the AHB uses only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers.
Page 467: Ethernet Dma Transmit Poll Demand Register (Emac_Dmatpd)
AT32F403A/407 Series Reference Manual Otherwise, Rx has priority over Tx. Software Reset When this bit is set, the MAC DMA controller resets all Bit 0 nternal registers and MAC logic. This bit is automatically cleared after all reset operations have been completed. 26.3.22 Ethernet DMA transmit poll demand register (EMAC_DMATPD) The EMAC_DMATPD register enables the Tx DMA to check whether or not the current descriptor is...
Page 468: Ethernet Dma Transmit Descriptor List Address Register
AT32F403A/407 Series Reference Manual zero by the DMA. Therefore these LSB bits are read only. 26.3.25 Ethernet DMA transmit descriptor list address register (EMAC_DMATDLADDR) The EMAC_DMATDLADDR regiser points to the start of the transmit descriptor list. The descriptor list is located in the host’s physical memory and must be word-aligned. The DMA enables bus-width aligned address by making the corresponding LS bit low.
Page 469 AT32F403A/407 Series Reference Manual 100: Error during Rx DMA descriptor write access 101: Error during Tx DMA descriptor write access 110: Error during Rx DMA descriptor read access 111: Error during Tx DMA descriptor read access Note: 001 and 010 are reserved. Transmit Process State This field indicates the Tx DMA FSM state.
Page 470 AT32F403A/407 Series Reference Manual summary. This is a sticky bit and it must be cleared (by writing 1 to this bit) each time a corresponding bit (causes AIS to be set) is cleared. Early Receive Interrupt This bit indicates that the DMA has filled the first data buffer of the packet.
Page 471: Ethernet Dma Operation Mode Register (Emac_Dmaopm)
AT32F403A/407 Series Reference Manual This bit indicates that the next descriptor in the transmit list is owned by the host and cannot be acquired by the DMA. Then the transmit process is suspended. Bit [22: 20] explains the transmit process state. To resume transmit process, the host should change the ownership of the descriptor by setting the TDES0[31] and issue the transmit poll demand command...
Page 472 AT32F403A/407 Series Reference Manual Transmit Threshold Control These bits control the threshold of the Tx FIFO. Transmission starts when the frame size in the Tx FIFO is greater than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are applicable only when the bit 21 (TSF) is reset.
Page 473: Ethernet Dma Interrupt Enable Register (Emac_Dmaie)
AT32F403A/407 Series Reference Manual These two bits control the threshold of the Rx FIFO. Transfer to DMA starts when the frame in the Rx FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also automatically transferred.
Page 474 AT32F403A/407 Series Reference Manual the status register) EMAC_DMASTS[1]: Transmit process stopped EMAC_DMASTS[3]: Transmit Jabber timeout EMAC_DMASTS[4]: Transmit overflow EMAC_DMASTS[5]: Transmit data underflow EMAC_DMASTS[7]: Transmit buffer u unavailable EMAC_DMASTS[8]: Receive process stopped EMAC_DMASTS[9]: Receive watchdog timeout EMAC_DMASTS[10]: Early transmit interrupt EMAC_DMASTS[13]: Fatal bus error Early Receive interrupt Enable When this bit is set with the normal interrupt summary Bit 14...
Page 475: Ethernet Dma Missed Frame And Buffer Overflow Counter Register (Emac_Dmamfbocnt)
AT32F403A/407 Series Reference Manual enabled. When this bit is cleared, the transmit buffer unavailable interrupt is disabled. Transmit Stopped Enable When this bit is set with the abnormal interrupt summary Bit 1 enable bit, the transmit stopped interrupt is enabled. When this bit is cleared, the transmit stopped interrupt is disabled.
Page 476: Ethernet Dma Current Receive Descriptor Register (Emac_Dmacrd)
AT32F403A/407 Series Reference Manual 26.3.31 Ethernet DMA current receive descriptor register (EMAC_DMACRD) The EMAC_DMACRD register points to the start address of the receive descriptor being read by the DMA. Register Reset value Type Description Host Receive Descriptor Address Pointer These bits are cleared when reset. The DMA updates the Bit 31: 0 HRDAP 0x0000 0000...
Page 477: Ethernet Mmc Transmit Interrupt Register (Emac_Mmcti)
AT32F403A/407 Series Reference Manual When the counter stops rolling, an interrupt is set but the counter is still all 1. The EMAC_MMCRI is a 32-bit register. An interrupt bit is cleared when the the MMC counter that generates the interrupt is read. The least significant byte bit [7: 0] of the corresponding counter must be read in order to clear the interrupt bit.
Page 478: Ethernet Mmc Transmit Interrupt Register (Emac_Mmctim)
AT32F403A/407 Series Reference Manual Kept at its default value. Bit 16: 7 Reserved 0x000 resd Received Alignment Error Frame Alignment Counter Interrupt Mask Bit 6 RAEFACIM Setting this bit masks the interrupt when the received alignment error frame counter reaches half its maximum value or its maximum value.
Page 479: Ethernet Mmc Transmitted Good Frames Counter Register (Emac_Mmctfcnt)
AT32F403A/407 Series Reference Manual 26.3.41 Ethernet MMC transmitted good frames counter register (EMAC_MMCTFCNT) This register maintains the number of the transmitted good frames. Register Reset value Type Description Transmitted Good Frames Counter Bit 31: 0 TGFC 0x0000 0000 26.3.42 Ethernet MMC received frames with CRC error counter register (EMAC_MMCRFCECR) This register maintains the number of the received good frames with CRC error.
Page 480 AT32F403A/407 Series Reference Manual When this bit is set, the MAC receiver processes the PTP encapsulated in UDP over IPv4 packet. When this bit is cleared, the MAC ignores the PTP transferred over UDP- IPv4 packet. This bit is set by default. Enable Processing of PTP Frames Sent over IPv6-UDP When this bit is set, the MAC receiver processes the PTP encapsulated in UDP over IPv6 packet.
Page 481: Ethernet Ptp Subsecond Increment Register
AT32F403A/407 Series Reference Manual When this bit is set, it indicates that the system time is updated using a fine update method. When this bit is cleared, it indicates that the system time is updated using a coarse update method. Timestamp Enable When this bit is set, time stamp function is enabled for transmit and receive frames.
Page 482: Ethernet Ptp Time Stamp Low Register (Emac_Ptptsl)
AT32F403A/407 Series Reference Manual 26.3.48 Ethernet PTP time stamp low register (EMAC_PTPTSL) This register contains the lower 32 time bits. It is a read-only register containing the subsecond system time value. Register Reset value Type Description Add or Subtract Time When this bit is set, the time value is subtracted from the Bit 31 value of the update register.
Page 483: Ethernet Ptp Target Time High Register (Emac_Ptptth)
AT32F403A/407 Series Reference Manual 26.3.52 Ethernet PTP target time high register (EMAC_PTPTTH ) Target time second register and target time subsecond register are used to schedule an interrupt event when the system time exceeds the value programmed in these registers. Register Reset value Type...
Page 484: Ethernet Ptp Pps Register (Emac_Ptpppscr)
AT32F403A/407 Series Reference Manual 26.3.55 Ethernet PTP PPS register (EMAC_PTPPPSCR) Register Reset value Type Description Bit 31: 4 Reserved 0x0000000 resd Kept at its default value. PPS0 Output Frequency Control The output of this field depends on the emac_pps_sel bit (bit 15 in the CRM_MISC2 register) Emac_pps_sel=0: 0000: 1 Hz, use binary rollover control, pulse width is 125...
Page 485: Debug (Debug)
AT32F403A/407 Series Reference Manual 27 Debug (DEBUG) 27.1 Debug introduction Cortex™-M4F core provides poweful debugging features including halt and single step support, as well as trace function that is used for checking the details of the program execution. The debug features are implemented with two interfaces: serial wire debug (SWD) and JTAG debug port.
Page 486: Debug Registers
AT32F403A/407 Series Reference Manual Table 27- 2 Trace function mode TRACE PB3/JTDO/TR PE2/TRAC PE3/TRAC PE4/TRAC PE5/TRACE PE6/TRAC _MODE[1: 0] ACESWO ED[0] ED[1] D[2] ED[3] Asynchronous TRACES Released (can be used as general-puspose I/Os) trace Synchronous TRAC TRAC Released (can be used as general- trace ED[0] puspose I/Os)
Page 487: Debug Control Register (Debug_Ctrl)
AT32F403A/407 Series Reference Manual 27.4.2 DEBUG control register (DEBUG_CTRL) This register is asynchronously reset by POR Reset (not reset by system reset). It can be written by the debugger under reset. Register Reset value Type Description C3 pause control bit 0: Work normally Bit 31 I2C3_SMBUS_TIMEOUT 0x0...
Page 488 AT32F403A/407 Series Reference Manual TMR4 pause control bit 0: Work normally Bit 13 TMR4_PAUSE 1: Timer is disabled TMR3 pause control bit 0: Work normally Bit 12 TMR3_PAUSE 1: Timer is disabled TMR2 pause control bit 0: Work normally Bit 11 TMR2_PAUSE 1: Timer is disabled TMR1 pause control bit...
Page 489: Revision History
AT32F403A/407 Series Reference Manual 28 Revision history Document Revision History Date Version Revision Note Initial release. 2021.06.30 2.00 1. Update Figure 4- 1 to make it easier to read; 2021.10.22 2.01 2. Revised some typos. Revised some typos. 2021.12.01 2.02 2021.12.01 Page 489 Ver 2.02...
Page 490 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previous representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third party’s products or services...

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