Table of Contents
Advertisement
Quick Links
®
ARM
-based 32-bit Cortex
OTGFS, 13 timers, ADC, 12 communication interfaces
Feature
®
Core: ARM
32-bit Cortex
− 96 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
− DSP instructions
Memories
− 32 to 64 KBytes of Flash memory
− 4 Kbytes of boot code area used as a Bootloader or
as a general instruction/data memory (one-time-
configured)
− sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
− 20 KBytes of SRAM
Power control (PWC)
− 2.4 V ~ 3.6 V application suppy
− Power-on reset (POR)/ low-voltage reset (LVR), and
power voltage monitor (PVM)
− Low power: Sleep, Deepsleep, and Standby modes,
6 WKUP pins can wake up Standby mode
− 5 x 32-bit battery power registers (BPR)
Clock and reset management (CRM)
− 4 to 25 MHz crystal oscillator (HEXT)
− Internal 48 MHz factory-trimmed clock (HICK),
accuracy 1% at T
+105 °C, with automatic clock calibration (ACC)
− PLL with configurable frequency multiplication and
division factor
− 32.768 kHz crystal oscillator (LEXT)
− Internal 40 kHz RC oscillator (LICK)
Analog
− 1 x 12-bit 2 MSPS A/D converter, up to 16 input
channels, hardware over-sampling up to equivalent
16-bit resolution
− Internal reference voltage (V
DMA:
− 1 x DMA controller for flexible mapping support
− 7 channels in all
Up to 55 Fast I/O Interfaces
− All mappable to 16 external interrupt vectors
− Almost 5 V-tolerant
Up to 3 Timers (TMR)
− 1 x 16-bit 7-channel advanced timer, 6- channel PWM
2022.03.30
®
-M4F MCU with 32 to 64 KB Flash, sLib, CAN,
®
-M4F CPU
=25 °C, 2.5 % at T
=-40 to
A
A
)
I NT R V
AT32F425 Series Reference Manual
output with dead-time generator and emergency stop
− Up to 6 x 16-bit and 1 x 32-bit general-purpose timers,
each with 4 IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
− Advanced and general-purpose timers provide up to 24-
channel PWM
− 2 x 16-bit basic timers
− 2 x Watchdog timers (WDT and WWDT)
− SysTick timer: 24-bit downcounter
ERTC: enhanced RTC with auto wakeup, alarm,
subsecond precision, hardware calendar and
calibration feature
Up to 12 communication interfaces
− Up to 2 x I
2
C interfaces (SMBus/PMBus)
− Up to 4 x USARTs
modem control, with ISO7816 interface, LIN, IrDA and
RS485 driver enable; support TX/RX swap
− Up to 3 x SPIs (36 Mbit/s), all with I
multiplexed, I
− CAN interface (2.0B Active), with 256 bytes of dedicated
SRAM
− OTG full speed interface, with 1280 bytes of dedicated
SRAM, supporting crystal-less in device mode
− Infrared transmitter (IRTMR)
CRC Calculation Unit
96-bit ID (UID)
Debug mode
− Serial wire debug (SWD) and serial wire output (SWO)
Temperature range: -40 to 105℃
Packaging
− LQFP64 10 x 10 mm
− LQFP64 7 x 7 mm
− QFN48 6 x 6 mm
− TSSOP20 6.5 x 4.4 mm
List of Models
Internal Flash
AT32F425R8T7, AT32F425R8T7 -7, AT32F425C8T7,
AT32F425C8U7, AT32F425K8T7, AT32F425K8U7-4,
64 KBytes
AT32F425F8P7
A T32F425R6T7, AT32F425R6T7 -7, AT32F425C6T7,
AT32F425C6U7, AT32F425K6T7, AT32F425K6U7-4,
32 KBytes
AT32F425F6P7
Page 1
,
support master synchronous SPI and
2
S interface
2
2
S2/ I
S3 support full-duplex
LQFP32 7 x 7 mm
LQFP48 7 x 7 mm
QFN32 4 X 4 mm
Model
Ver 2.01
Advertisement
Table of Contents
Subscribe to Our Youtube Channel
Related Manuals for ARTERY AT32F425 Series
Summary of Contents for ARTERY AT32F425 Series
- Page 1 AT32F425 Series Reference Manual ® ® -based 32-bit Cortex -M4F MCU with 32 to 64 KB Flash, sLib, CAN, OTGFS, 13 timers, ADC, 12 communication interfaces Feature output with dead-time generator and emergency stop ® ® Core: ARM 32-bit Cortex -M4F CPU −...
-
Page 2: Table Of Contents
AT32F425 Series Reference Manual Contents System architecture ..............30 System overview ................32 1.1.1 ARM Cortex -M4 processor ............32 1.1.2 Bit band ..................32 1.1.3 Interrupt and exception vectors ............ 34 1.1.4 System Tick (SysTick) ..............36 1.1.5 Reset ..................36 List of abbreviations for registers .......... - Page 3 AT32F425 Series Reference Manual 4.1.1 Clock sources ................49 4.1.2 System clock ................50 4.1.3 Peripheral clock ................50 4.1.4 Clock fail detector ............... 51 4.1.5 Clock output ................51 4.1.6 Interrupts ..................51 Reset ..................51 4.2.1 System reset ................51 4.2.2 Battery powered domain reset ............
- Page 4 AT32F425 Series Reference Manual 5.4.2 Erase operation ................71 5.4.3 Programming operation..............72 5.4.4 Read operation ................73 Flash memory protection .............. 73 5.5.1 Access protection ................ 73 5.5.2 Erase/program protection............. 74 Special functions ................. 75 5.6.1 Security library settings ............... 75 5.6.2 Bootloader code area used as Flash memory extension ....
- Page 5 AT32F425 Series Reference Manual Function overview ................ 84 6.2.1 GPIO structure ................84 6.2.2 GPIO reset status ................ 85 6.2.3 General-purpose input configuration ..........85 6.2.4 Analog input/output configuration ..........85 6.2.5 General-purpose output configuration ........... 85 6.2.6 GPIO port protection ..............86 6.2.7 IOMUX structure .................
- Page 6 AT32F425 Series Reference Manual 7.2.5 SCFG external interrupt configuration register4 (SCFG_ EXINTC4) 97 7.2.6 SCFG configuration register2 (SCFG_CFG2) ........ 98 External interrupt/Event controller (EXINT) ........99 EXINT introduction ............... 99 Function overview and configuration procedure ......99 EXINT registers ................. 100 8.3.1 Interrupt enable register (EXINT_INTEN) ........
- Page 7 AT32F425 Series Reference Manual 9.4.7 DMA channel source register (DMA_SRC_SEL0) ......112 9.4.8 DMA channel source register1 (DMA_SRC_SEL1) ......112 CRC calculation unit (CRC) ............113 10.1 CRC introduction ............... 113 10.2 CRC registers ................113 10.2.1 Data register (CRC_DT).............. 113 10.2.2 Common data register (CRC_CDT) ..........
- Page 8 AT32F425 Series Reference Manual 11.7.8 Status clear register (I2C_CLR) ..........146 11.7.9 PEC register (I2C_PEC) ............. 146 11.7.10 Receive data register (I2C_RXDT) ..........146 11.7.11 Transmit data register (I2C_TXDT) ........... 146 Universal synchronous/asynchronous receiver/transmitter (USART) 147 12.1 USART introduction ..............147 12.2 Full-duplex/half-duplex selector ..........
- Page 9 AT32F425 Series Reference Manual 12.12.6 Control register3 (USART_CTRL3) ........... 160 12.12.7 Guard time and divider register (USART_GDIV) ......161 Serial peripheral interface (SPI) ..........162 13.1 SPI introduction ................. 162 13.2 Function overview ..............162 13.2.1 SPI description ................162 13.2.2 Full-duplex/half-duplex selector ..........
- Page 10 AT32F425 Series Reference Manual 13.4.4 SPI data register (SPI_DT) ............184 13.4.5 SPICRC register (SPI_CPOLY) (Not used in I S mode) ....184 13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I S mode) ....184 13.4.7 SPITxCRC register (SPI_TCRC) ..........184 13.4.8 SPI_I2S register (SPI_I2SCTRL) ..........
- Page 11 AT32F425 Series Reference Manual 14.2.4.3 TMR2 and TMR3 slave timer control register (TMRx_STCTRL) . 203 14.2.4.4 TMR2 and TMR3 DMA/interrupt enable register (TMRx_IDEN) .. 204 14.2.4.5 TMR2 and TMR3 interrupt status register (TMRx_ISTS) ... 205 14.2.4.6 TMR2 and TMR3 software event register (TMRx_SW EVT) ..206 14.2.4.7 TMR2 and TMR3 channel mode register1 (TMRx_CM1) ....
- Page 12 AT32F425 Series Reference Manual 14.4.1 TMR15 introduction ..............220 14.4.2 TMR15 main features ..............220 14.4.3 TMR15 functional overview ............221 14.4.3.1 Count clock ................221 14.4.3.2 Counting mode ..............222 14.4.3.3 TMR input function ..............223 14.4.3.4 TMR output function .............. 224 14.4.3.5 TMR break function ...............
- Page 13 AT32F425 Series Reference Manual 14.5.4 TMR16 and TM17 registers ............245 14.5.4.1 TMR16 and TMR17 control register1 (TMRx_CTRL1) ....246 14.5.4.2 TMR16 and TMR17 control register2 (TMRx_C TRL2) ....246 14.5.4.3 TMR16 and TMR17 DMA/interrupt enable register (TMRx_IDEN) 247 14.5.4.4 TMR16 and TMR17 interrupt status register (T MRx_ISTS) ..247 14.5.4.5 TMR16 and TMR17 software event register (TMRx_SW EVT) ..
- Page 14 AT32F425 Series Reference Manual 14.6.4.11 TMR1 division value (TMR1_DIV) ........275 14.6.4.12 TMR1 period register (TMR1_PR) ........275 14.6.4.13 TMR1 repetition period register (TMR1_RPR) ...... 275 14.6.4.14 TMR1 channel 1 data register (TMR1_C1DT) ...... 275 14.6.4.15 TMR1 channel 2 data register (TMR1_C2DT) ...... 275 14.6.4.16...
- Page 15 AT32F425 Series Reference Manual 17.1 ERTC introduction..............285 17.2 ERTC main features ..............285 17.3 ERTC function overview ............. 285 17.3.1 ERTC clock ................285 17.3.2 ERTC initialization ..............286 17.3.3 Periodic automatic wakeup ............288 17.3.4 ERTC calibration ................ 288 17.3.5 Time stamp function ..............
- Page 16 AT32F425 Series Reference Manual 18.4.1 Channel management ..............300 18.4.1.1 Internal reference voltage ............301 18.4.2 ADC operation process ............... 301 18.4.2.1 Power-on and calibration ............301 18.4.2.2 Trigger ................. 302 18.4.2.3 Sampling and conversion sequence ........302 18.4.3 Conversion sequence management ..........303 18.4.3.1 Sequence mode ..............
- Page 17 AT32F425 Series Reference Manual Controller area network (CAN) ............ 319 19.1 CAN introduction ............... 319 19.2 CAN main features ..............319 19.3 Baud rate .................. 319 19.4 Interrupt management ..............322 19.5 Design tips ................322 19.6 Functional overview ..............323 19.6.1 General description ..............
- Page 18 AT32F425 Series Reference Manual 19.7.3 CAN filter registers ..............341 19.7.3.1 CAN filter control register (CAN_FCTRL) ........ 341 19.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ..... 341 19.7.3.3 CAN filter bit width configuration register (CAN_ FBW CFG) ..342 19.7.3.4 CAN filter FIFO association register (CAN_ FRF) ....342 19.7.3.5 CAN filter activation control register (CAN_ FACFG) ....
- Page 19 AT32F425 Series Reference Manual 20.5.4.3 Endpoint initialization on enumeration completion ....365 20.5.4.4 Endpoint initialization on SetAddress command ....... 365 20.5.4.5 Endpoint initialization on SetConfiguration/SetInterface command 365 20.5.4.6 Endpoint activation ............... 365 20.5.4.7 USB endpoint deactivation ............. 366 20.5.4.8 Control write transfers (SETUP/Data OUT/Status IN) ....366 20.5.4.9 Control read transfers (SETUP/Data IN/Status OUT) ....
- Page 20 AT32F425 Series Reference Manual 20.6.3.13 OTGFS controller ID register (OTGFS_GUID) ...... 396 20.6.3.14 OTGFS host periodic Tx FIFO size register (OTGFS_HPTXFSIZ) ................396 20.6.3.15 OTGFS device IN endpoint Tx FIFO size register (OTGFS_DIEPTXFn) (x=1…7, where n is the FIFO number) ....396 20.6.4 Host-mode registers ..............
- Page 21 AT32F425 Series Reference Manual (x=x=1…7, where x is endpoing number) ..........408 20.6.5.11 OTGFS device control OUT endpoint 0 control register (OTGFS_DOEPCTL0) ................. 410 20.6.5.12 OTGFS device control OUT endpoint -x control register (OTGFS_DOEPCTLx) (x= x=1…7, where x if endpoint number) ..... 411 20.6.5.13...
- Page 22 AT32F425 Series Reference Manual Infrared timer (IRTMR) ..............424 Debug (DEBUG) ................425 23.1 Debug introduction ..............425 23.2 Debug and Trace ............... 425 23.3 I/O pin control................425 23.4 DEGUB registers ............... 425 23.4.1 DEBUG device ID (DEBUG_IDCODE) .......... 425 23.4.2 DEBUG control register (DEBUG_CTRL) ........
- Page 23 AT32F425 Series Reference Manual List of figures Figure 1-1 AT32F425 Series microcontrollers system architecture..............31 Figure 1-2 Internal block diagram of Cortex ® -M4 ..................32 Figure 1-3 Comparison between bit-band region and its alias region: image A ......... 32 Figure 1-4 Comparison between bit-band region and its alias region: image B .........
- Page 24 AT32F425 Series Reference Manual Figure 11-19 SMBus slave transmission timing ..................137 Figure 11-20 SMBus slave receive flow ....................138 Figure 11-21 SMBus slave receive timing ....................138 Figure 12-1 USART block diagram ......................147 Figure 12-2 Tx/Rx swap ..........................155 Figure 12-3 USART interrupt map diagram ....................
- Page 25 AT32F425 Series Reference Manual Figure 14-16 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32 ....194 Figure 14-17 Example of counter behavior in encoder interface mode (encoder mode C) ...... 195 Figure 14-18 Input/output channel 1 main circuit ..................195 Figure 14-19 Channel 1 input stage ......................
- Page 26 AT32F425 Series Reference Manual Figure 14-61 Example of trigger mode ...................... 229 Figure 14-62 Block diagram of TMR16 and TMR17 timer ................ 240 Figure 14-63 Control circuit with CK_INT divided by 1 ................240 Figure 14-64 Overflow event when PRBEN=0 ..................241 Figure 14-65 Overflow event when PRBEN=1 ..................
- Page 27 AT32F425 Series Reference Manual Figure 18-1 ADC1 block diagram ......................300 Figure 18-2 ADC basic operation process ....................301 Figure 18-3 ADC power-on and calibration ....................302 Figure 18-4 Sequence mode ........................303 Figure 18-5 Preempted group auto conversion mode................303 Figure 18-6 Repetition mode ........................
- Page 28 Table 1-1 Bit-band address mapping in SRAM ................... 33 Table 1-2 Bit-band address mapping in the peripheral area ............... 34 Table 1-3 AT32F425 series vector table ...................... 34 Table 1-3 List of abbreviations for registers ....................38 Table 1-4 List of abbreviations for registers ....................38 Table 2-1 Flash memory organization (64 KB) ....................
- Page 29 AT32F425 Series Reference Manual Table 13-2 SPI register map and reset value .................... 181 Table 14-1 TMR functional comparison ..................... 186 Table 14-2 TMR6 and TMR7— register table and reset value ..............188 Table 14-3 TMRx internal trigger connection ..................... 193 Table 14-4 Counting direction versus encoder signals................
-
Page 30: System Architecture
AT32F425 Series Reference Manual 1 System architecture ® ® AT32F425 series microcontrollers incorporates a 32-bit ARM Cortex -M4 processor core, multiple 16- bit and 32-bit timers, Infrared Transmisster (IRTMR), DMA controller, ERTC, communication interfaces such as SPI, I2C, USART/UART, CAN bus controller, USB2.0 full-speed interface, HICK with automatic clock calibration (ACC), 12-bit ADC, programmable voltage monitor (PVM) and other peripherals. -
Page 31: Figure 1-1 At32F425 Series Microcontrollers System Architecture
AT32F425 Series Reference Manual Figure 1-1 AT32F425 Series microcontrollers system architecture HEXT 4~25MHz HICK 48MHz OTGFS Max. 96MHz Cortex-M4 FCLK (Freq. Max. 96MHz) HCLK PCLK1 PCLK2 NVIC @VDD Flash Flash POR/LVR Controller SRAM SRAM LDO 1.2V 7 Channel Controller GPIOA... -
Page 32: System Overview
AT32F425 Series Reference Manual 1.1 System overview 1.1.1 ARM Cortex -M4 processor Cortex ® -M4 processor is a low-power consumption processor featuring low gate count, low interrupt latency, and low-cost debug. It supports DSP instruction set and FPU, and is applicable to deeply-embedded applications that require quicker response to interruption. -
Page 33: Figure 1-4 Comparison Between Bit-Band Region And Its Alias Region: Image B
AT32F425 Series Reference Manual Figure 1-4 Comparison between bit-band region and its alias region: image B bitband alias region (total 32M bytes) 0x23FF_FFFC 0x23FF_FFF8 0x23FF_FFF4 0x23FF_FFF0 0x23FF_FFEC 0x23FF_FFE8 0x23FF_FFE4 0x23FF_FFE0 0x2200_001C 0x2200_0018 0x2200_0014 0x2200_0010 0x2200_000C 0x2200_0008 0x2200_0004 0x2200_0000 bitband region... -
Page 34: Interrupt And Exception Vectors
AT32F425 Series Reference Manual … … 0x200F_FFFC.31 0x23FF_FFFC.0 Table 1-2 shows the mapping between bit-band region and alias region in the peripheral area: Table 1-2 Bit-band address mapping in the peripheral area Bit-band region Equivalent alias address 0x4000_0000.0 0x4200_0000.0 0x4000_0000.1 0x4200_0004.0... - Page 35 AT32F425 Series Reference Manual Reserved 0x0000_0034 Configu PendSV Pendable request for system service 0x0000_0038 rable Configu SysTick System tick timer 0x0000_003C rable Configu WWDT Window watchdog timer 0x0000_0040 rable Configu PVM from EXINT interrupt 0x0000_0044 rable Configu TAMPER Tamper interrupt...
-
Page 36: System Tick (Systick)
AT32F425 Series Reference Manual rable Configu OTGFS global interrupt and OTGFS OTGFS 0x0000_00BC rable wakeup interrupt through EXINT line 18 Configu I2C1_ERR C1 error interrupt 0x0000_00C0 rable Configu SPI3 SPI3 global interrupt 0x0000_00C4 rable Configu I2C2_ERR C1 error interrupt 0x0000_00C8... -
Page 37: Figure 1-6 Example Of Msp And Pc Initialization
0x0000_0000 0x2000_8000 In the AT32F425 series, the main Flash memory, Boot code or SRAM can be remapped to the code area between 0x0000_0000 and 0x07FF_FFFF. nBOOT1 corresponds to the value of the bit nBOOT1 in the SSB of the User System Data (USD). nBOOT1 and BOOT0 are used to set the specific memory from which CODE starts. -
Page 38: List Of Abbreviations For Registers
AT32F425 Series Reference Manual 1.2 List of abbreviations for registers List of abbreviations for registers Table 1-4 Register type Description Software can read and write to this bit. Software can only read this bit. Software can only write to the bit. Reading it returns its reset value. -
Page 39: Memory Resources
AT32F425 Series Reference Manual Bit 31: 0 UID[95: 64] 0xXXXX XXXX UID for bit 95 to bit 64 Note: UID[95:88] is series ID, which is 0x0F for AT32F425. 2 Memory resources 2.1 Internal memory address map Internal memory contains program memory (Flash), data memory (SRAM), peripheral registers and core registers. -
Page 40: Flash Memory
AT32F425 Series Reference Manual 2.2 Flash memory AT32F425 series provide up to 64 KB of on-chip Flash memory, supporting a single-cycle 32-bit read operation. Refer to Chapter 5 for more details about Flash memory controller and register configuration. Flash memory organization (64 KB) The main memory contains bank 1 (64 Kbytes), including 64 pages, 1 Kbytes per page. -
Page 41: Peripheral Address Map
AT32F425 Series Reference Manual 2.4 Peripheral address map Table 2-3 Peripheral boundary address Boundary address Peripherals 0xA000 1000 - 0xFFFF FFFF Reserved 0x6000 0000 - 0xA000 0FFF Reserved 0x5004 0000 - 0x5FFF FFFF Reserved 0x5000 0000 – 0x5003 FFFF OTGFS 0x4800 1800 –... - Page 42 AT32F425 Series Reference Manual Boundary address Peripherals 0x4000 6400 - 0x4000 67FF 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF Reserved 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF 0x4000 5000 - 0x4000 53FF Reserved...
-
Page 43: Power Control (Pwc)
Standby modes so as to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.The AT32F425 series have two power domains - VDD/VDDA domain and 1.2 V domain. The VDD/VDDA domain is supplied directly by external power, the 1.2 V domain is powered by an embedded LDO in the VDD/VDDA domain. -
Page 44: Por/Lvr
AT32F425 Series Reference Manual 3.3 POR/LVR A POR analog module embedded in the VDD/VDDA domain is used to generate a power reset. The power reset signal is released at V when the VDD is increased from 0 V to the operating voltage, or it is triggered at V when the VDD drops from the operating voltage to 0 V. -
Page 45: Power Domain
AT32F425 Series Reference Manual 3.5 Power domain 1.2 V domain 1.2 V core domain includes a CPU core, SRAM, embedded digital peripherals and Phase Locked Loop (PLL). Such power domain is supplied by LDO (voltage regulator). VDD/VDDA domain VDD/VDDA domain includes VDD domain and VDDA domain. The VDD domain contains I/O circuit, power-saving mode wakeup circuit, watchdog timer (WDT), power-on reset/low voltage reset (POR/LVR), LDO, ERTC circuit, LEXT oscillator and and all PAD circuits. -
Page 46: Pwc Registers
AT32F425 Series Reference Manual external interrupt line in Interrupt mode can wake up the system from Deepsleep mode. 2) When the Sleep mode is entered by executing a WFE instruction, the interrupt generated on any external interrupt line in Event mode can wake up the system from Deepsleep mode. -
Page 47: Power Control Register (Pwc_Ctrl)
AT32F425 Series Reference Manual 3.7.1 Power control register (PWC_CTRL) Name Reset value Type Description Kept at its default value. Bit 31: 9 Reserved 0x000000 resd Battery powered domain write enable 0: Disabled 1: Enabled Bit 8 BPWEN Note: After reset, ERTC is write protected. To write, this bit must be set. -
Page 48: Power Control Register2 (Pwc_Ctrl2)
AT32F425 Series Reference Manual Note: This bit is cleared by hardware after system reset. resd Kept at its default value. Bit 10 Reserved 0x00 Standby wake-up pin2 enable 0: Disabled (this pin is used for general-purpose I/O) 1: Enabled (this pin is forced in input pull-down mode, and... -
Page 49: Clock And Reset Manage (Crm)
HICK clock is 48 MHz. Although it is less accurate, its startup time is shorter than the HEXT crystal oscillator. The HICK clock frequency of each device is calibrated by ARTERY to 1% accuracy (25°C) in factory. The factory calibration value is loaded in the HICKCAL[7: 0] bit of the clock control register. The RC oscillator speed may be affected by voltage or temperature variations. -
Page 50: System Clock
AT32F425 Series Reference Manual divider must remain between 2 MHz and 16 MHz, and the VCO operating frequency must be kept between 500 MHz and 1000 MHz. The PLL must be configured before enabling it. The reason is that the configuration parameters cannot be changed once PLL is enabled. The PLL clock signal is not released before it becomes stable. -
Page 51: Clock Fail Detector
If a failure is detected on the HEXT clock, the CFD interrupt is generated. Such interrrpt is directly linked to CPU NMI. 4.2 Reset 4.2.1 System reset AT32F425 series provide the following system reset sources: NRST reset: on the external NRST pin WDT reset: watchdog overflow ... -
Page 52: Battery Powered Domain Reset
AT32F425 Series Reference Manual Figure 4-2 System reset circuit Pulse generator (Min 20 µs) NRST CTRL NRST reset Filter WDT reset System WWDT reset reset CPU software reset Low-power management reset POR reset LVR reset standby return reset 4.2.2 Battery powered domain reset Battery powered domain has two specific reset sources: ... -
Page 53: Clock Control Register (Crm_Ctrl)
AT32F425 Series Reference Manual 4.3.1 Clock control register (CRM_CTRL) Name Reset value Type Description Bit 30: 26 Reserved 0x00 resd Kept at its default value. PLL clock stable This bit is set by hardware after PLL is ready. Bit 25 PLLSTBL 0: PLL clock is not ready. -
Page 54: Clock Configuration Register (Crm_Cfg)
AT32F425 Series Reference Manual High speed internal clock enable This bit is set and cleared by software. It can also be set by hardware when exiting Standby or Deepsleep mode. When a HEXT clock failure occurs. This bit can also be set. When... -
Page 55: Clock Interrupt Register (Crm_Clkint)
AT32F425 Series Reference Manual 111: PCLK/16 APB2 division The divided HCLK is used as APB2 clock. 0xx: not divided 100: divided by 2 Bit 13: 11 APB2DIV 101: divided by 4 110: divided by 8 111: divided by 16 Note: The software must set these bits correctly to ensure that the APB2 clock frequency does not exceed 96 MHz. - Page 56 AT32F425 Series Reference Manual LEXT stable flag clear Writing 1 by software to clear LEXTSTBLF. Bit 17 LEXTSTBLFC 0: No effect 1: Clear LICK stable flag clear Writing 1 by software to clear LICKSTBLF. Bit 16 LICKSTBLFC 0: No effect...
-
Page 57: Apb2 Peripheral Reset Register (Crm_Apb2Rst)
AT32F425 Series Reference Manual 4.3.4 APB2 peripheral reset register (CRM_APB2RST) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Bit 31:19 Reserved 0x00 resd Kept at its default value. TMR17 reset Bit 18 TMR17RST... -
Page 58: Apb Peripheral Clock Enable Register (Crm_Ahben)
AT32F425 Series Reference Manual 0: Does not reset EDMA 1: Reset EDMA Bit 20 Reserved resd Kept at its default value. USART4 reset Bit 19 USART4RST 0: Does not reset USART4 1: Reset USART4 USART3 reset Bit 18 USART3RST 0: Does not reset USART3... -
Page 59: Apb2 Peripheral Clock Enable Register (Crm_Ahb2En)
AT32F425 Series Reference Manual 0: Disabled 1: Enabled Bit 16: 13 Reserved resd Kept at its default value. OTGFS1 clock enable 0: Disabled Bit 12 OTGFS1EN 1: Enabled Bit 11: 7 Reserved resd Kept at its default value. CRC clock enable... -
Page 60: Apb1 Peripheral Clock Enable Register (Crm_Ahb1En)
AT32F425 Series Reference Manual 4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN) Access: 0 wait state, accessible by words, half-words and bytes. No-wait states in most cases. However, when accessing to peripherals on APB1, wait-states are inserted until the end of peripheral access on the APB1 bus. -
Page 61: Battery Powered Domain Control Register (Crm_Bpdc)
AT32F425 Series Reference Manual TMR2 clock enable Bit 0 TMR2EN 0: Disabled 1: Enabled 4.3.9 Battery powered domain control register (CRM_BPDC) Access: 0 to 3 wait states, accessible by words, half-words or bytes. Wait states are inserted in the case of consecutive accesses to this register. -
Page 62: Apb Peripheral Reset Register (Crm_Apbrst)
AT32F425 Series Reference Manual Sety by hardware. Cleared by writing to the RSTFC bit. 0: No software reset occurs 1: Software reset occurs. POR/LVR reset flag Sety by hardware. Cleared by writing to the RSTFC bit. Bit 27 PORRSTF 0: No POR/LVR reset occurs 1: POR/LVR reset occurs. -
Page 63: Additional Register1 (Crm_Misc1)
AT32F425 Series Reference Manual 010: 7.8125 ~ 8.33 MHz 011: 8.33 ~ 12.5 MHz 100: 15.625 ~ 20.83 MHz 101: 20.83 ~ 31.25 MHz 110: Reserved 111: Reserved Bit 23: 17 Reserved 0x00 resd Kept at its default value. PLL multiplication factor... -
Page 64: Additional Register2 (Crm_Misc2)
AT32F425 Series Reference Manual 4.3.14 Additional register2 (CRM_MISC2) Name Reset value Type Description Bit 31: 10 Reserved 0x0000 resd Kept at its default value. HICK as system clock frequency select When HICK is used as a clock source of SCLKSEL, the... -
Page 65: Flash Memory Controller (Flash)
AT32F425 Series Reference Manual 5 Flash memory controller (FLASH) 5.1 FLASH introduction Flash memory is divided into three parts: main Flash memory, information block and Flash memory registers. Main Flash memory is up to 64 KB Information block consists of 4 KB boot loader and the user system data area. The boot loader ... - Page 66 AT32F425 Series Reference Manual [15: 8] nFAP[7: 0]: Inverse code of FAP[7: 0] SSB[7:0]: System configuration byte (it is stored in the FLASH_USD[9: 2] register) Bit 7 Reserved 0: WDT stops counting while entering Standby mode Bit 6 (nWDT_STDBY) 1: WDT does not stop counting while...
-
Page 67: Flash Memory Operation
AT32F425 Series Reference Manual … … [7: 0] Data248[7: 0]: User system data 248 [15: 8] nData248[7: 0]: Inverse code of Data248[7: 0] 0x1FFF_F9FC [23: 16] Data249[7: 0]: User system data 249 [31: 24] nData249[7: 0]: Inverse code of Data249[7: 0] 5.2 Flash memory operation... -
Page 68: Figure 5-1 Flash Memory Page Erase Process
AT32F425 Series Reference Manual Flash memory page erase process Figure 5-1 Start Check the OBF bit in FLASH_STSx OBF = 0 ? Write the erased sector address to FLASH_ADDRx Set SECERS = 1 and ERSTR =1 in FLASH_CTRLx Check the OBF bit in FLASH_STSx... -
Page 69: Programming Operation
AT32F425 Series Reference Manual Flash memory mass erase process Figure 5-2 Start Check the OBF bit in FLASH_STSx OBF = 0? Set BANKERS = 1 and ERSTR =1 in FLASH_CTRLx Check the OBF bit in FLASH_STSx OBF = 0 ? -
Page 70: Read Operation
AT32F425 Series Reference Manual Figure 5-3 Flash memory programming process Start Check the OBF bit in FLASH_STS OBF = 0? Set the FPRGM bit = 1 in FLASH_CTRL Write word/half-word/byte (32bits/16 bits/8bits) data Check the OBF bit in FLASH_STS OBF = 0? Read EPPERR bit、PRGMERR... -
Page 71: Erase Operation
AT32F425 Series Reference Manual When KEY1 (0x45670123) and KEY2 (0xCDEF89AB) is written to the FLASH_USD_UNLOCK register, the USDULKS bit in the FLASH_CTRL register will be automatically set by hardware, indicating that it supports write/erase operation to the user system data area. -
Page 72: Programming Operation
AT32F425 Series Reference Manual Figure 5-4 System data area erase process Start Check the OBF bit in FLASH_STS OBF = 0? Set USDERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ? Read ODF bit in FLASH_STS 5.4.3... -
Page 73: Read Operation
AT32F425 Series Reference Manual Figure 5-5 System data area programming process Start Check the OBF bit in FLASH_STS OBF = 0? Set the USDPRGM bit = 1 in FLASH_CTRL Write word/half-word (32bits/16 bits) data Check the OBF bit in FLASH_STS... -
Page 74: Erase/Program Protection
AT32F425 Series Reference Manual Low-level access protection When the contents in the nFAP and FAP bytes are different from 0x5A and 0xA5, and 0x33 and 0xCC, the low-level Flash memory access protection is enabled after a system reset. When the Flash access is protected, the user can re-erase the system data area, and unlock Flash access protection (switching from protected to unprotected state will trigger mass erase on the Flash memory automatically) by wrting 0xA5 to FAP byte, and then perform a system reset. -
Page 75: Special Functions
AT32F425 Series Reference Manual 5.6 Special functions 5.6.1 Security library settings Security library is a defined area protected by a code in the main memory. This area is only executable but cannot be read (Except for I-Code and D-code buses), written, or deleted, unless a correct code is keyed in. -
Page 76: Bootloader Code Area Used As Flash Memory Extension
AT32F425 Series Reference Manual Note: Disabling the security library will automatically perform mass erase on the main memory and its extension area, as well as on security library setting block. 5.6.2 Bootloader code area used as Flash memory extension There is only one chance for users to program the bootloader code area as the main Flash extension... -
Page 77: Flash Performance Select Register (Flash_Psr)
AT32F425 Series Reference Manual Register Offset Reset value SLIB_MISC_STS 0x80 0x0000 0000 FLASH_CRC_ADDR 0x84 0x0000 0000 FLASH_CRC_CTRL 0x88 0x0000 0000 FLASH_CRC_CHKR 0x8C 0x0000 0000 SLIB_SET_PWD 0x160 0x0000 0000 SLIB_SET_RANGE 0x164 0x0000 0000 EM_SLIB_SET 0x168 0x0000 0000 BTM_MODE_SET 0x16C 0x0000 0000... -
Page 78: Flash User System Data Unlock Register (Flash_Usd_Unlock)
AT32F425 Series Reference Manual 5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) Abbr. Reset value Type Description Bit 31: 0 USD_UKVAL 0xXXXX XXXX wo User system data Unlock key value Note: All these bits are write-only, and return 0 when being read. -
Page 79: Flash Address Register (Flash_Addr)
AT32F425 Series Reference Manual Erase start An erase operation is triggered when this bit is set. This bit Bit 6 ERSTR is cleared by hardware after the completion of the erase operation. User system data erase Bit 5 USDERS It indicates the user system data erase. -
Page 80: Erase/Program Protection Status Register (Flash_Epps)
AT32F425 Series Reference Manual 5.7.8 Erase/program protection status register (FLASH_EPPS) Register Reset value Type Description Erase/Program protection status This register reflects the erase/program protection byte Bit 31: 0 EPPS 0xFFFF FFFF ro status in the loaded user system data. 5.7.9 Flash security library status register0 (SLIB_STS0) For Flash security library only. -
Page 81: Security Library Password Cle Ar Register (Slib_Pwd_Clr)
AT32F425 Series Reference Manual 5.7.11 Security library password clear register (SLIB_PWD_CLR) Only used in Flash security library. Register Reset value Type Description Security library password clear value This register is used to key in a correct sLib password in order to unlock sLib function. -
Page 82: Flash Crc Check Result Register (Flash_Crc_Chkr)
AT32F425 Series Reference Manual 5.7.15 Flash CRC check result register (FLASH_CRC_CHKR) For Flash memory and its extension area. Register Reset value Type Description CRC check result Bit 31: 0 CRC_CHKR 0x0000 0000 Note: All these bits are write-only, and return no response when being read. -
Page 83: Boot Mode Setting Register (Btm_Mode_Set)
AT32F425 Series Reference Manual 5.7.18 Flash extension memory security library setting register (EM_SLIB_SET) For Flash extension area only. Register Reset value Type Description Kept at its default value Bit 31: 24 Reserved 0x00 resd Extension memory sLib instruction start page... -
Page 84: Gpios And Iomux
6 GPIOs and IOMUX 6.1 Introduction AT32F425 series supports up to 55 bidirectional I/O pins, namely PA0-PA15, PB0-PB15, PC0-PC15, PD2, PF0-PF1, and PF4-PF7. Each of these pins features communication, control and data collection. In addition, their main features also include: ... -
Page 85: Gpio Reset Status
AT32F425 Series Reference Manual 6.2.2 GPIO reset status After power-on or system reset, all pins are configured as floating input mode except SWD-related pins. SWD pin configuration are as follows: PA13/SWDIO multiplexed pull-up PA14/SWCLK multiplexed pull-down 6.2.3 General-purpose input configuration... -
Page 86: Gpio Port Protection
AT32F425 Series Reference Manual 6.2.6 GPIO port protection Locking mechanism can freeze the I/O configuration for the purpose of protection. When LOCK is applied to a port bit, its configuration cannot be modified until the next reset or power on. -
Page 87: Iomux Input/Output
AT32F425 Series Reference Manual 6.2.9 IOMUX input/output The multiplexed function of each IO port line is configured through the GPIOx_MUXL (for pin 0 to 7) or GPIOx_MUXH (for pin 8 to 15) register. Table 6-1 Port A multiplexed function configuration with GPIOA_MUX* register... -
Page 88: Table 6-2 Port B Multiplexed Function Configuration With Gpiob_Mux* Register
AT32F425 Series Reference Manual Table 6-2 Port B multiplexed function configuration with GPIOB_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 USART3 EVENTO TMR3_CH TMR1_C USART2_ USART3 SPI1_MISO/ _RTS_D I2S1_MCK I2S1_MCK USART3 TMR14_ TMR3_CH TMR1_C USART2_ USART3 SPI2_SCK SPI1_MOSI/... -
Page 89: Table 6-3 Port C Multiplexed Function Configuration With Gpioc_Mux* Register
AT32F425 Series Reference Manual Table 6-3 Port C multiplexed function configuration with GPIOC_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 EVENT I2C2_SCL I2C1_SCL EVENT SPI3_MOSI / SPI1_MOS SPI2_MOS I2C2_SDA I2C1_SDA I2S3_SD I / I2S1_SD I / I2S2_SD EVENT... -
Page 90: Peripheral Mux Function Configuration
AT32F425 Series Reference Manual 6.2.10 Peripheral MUX function configuration IOMUX function configuration as follows: To use a peripheral pin in MUX output, it is configured as multiplexed push-pull/open-drain output. To use a peripheral pin in MUX input, it is configured as floating input/pull-up/pull-down input. -
Page 91: Gpio Configuration Register (Gpiox_Cfgr) (X=A/B/C/D/F)
AT32F425 Series Reference Manual GPIOx_ODT 0x14 0x0000 0000 GPIOx_SCR 0x18 0x0000 0000 GPIOx_WPR 0x1C 0x0000 0000 GPIOx_MUXL 0x20 0x0000 0000 GPIOx_MUXH 0x24 0x0000 0000 GPIOx_CLR 0x28 0x0000 0000 GPIOx_HDRV 0x3C 0x0000 0000 6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A/B/C/D/F) Address offset: 0x00... -
Page 92: Gpio Input Register (Gpiox_Idh) (X=A/B/C/D/F)
AT32F425 Series Reference Manual 6.3.5 GPIO input register (GPIOx_IDH) (x=A/B/C/D/F) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Always 0. GPIOx input data Bit 15: 0 0xXXXX Indicates the input status of I/O port. Each bit corresponds to an I/O. -
Page 93: Gpio Multiplexed Function Low Register (Gpiox_Muxl) (X= A/B/C/D/F)
AT32F425 Series Reference Manual 6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x= A/B/C/D/F) Address offset: 0x20 Reset value: 0x00000000 Register Reset value Type Description Multiplexed function select for GPIOx pin y (y=0…7) This field is used to configure multiplexed function IOs. -
Page 94: System Configuration Controller (Scfg)
AT32F425 Series Reference Manual 7 System configuration controller (SCFG) 7.1 Introduction This device contains a set of system configuration register. The system configuration controller is mainly used to: Manage the external interrupts connected to the GPIOs Control the memory mapping mode ... -
Page 95: Scfg External Interrupt Configuration Register1 (Scfg_ Exintc1)
AT32F425 Series Reference Manual soucing/sinking strength When this bit is set, the control bits of GPIOx_OTYPER&GPIOx_HDRV become invalid Bit 15: 8 Reserved resd Kept at its default value. Infrared modulation envelope signal source selection This field is used to select the infrared modulation envelope signal source. -
Page 96: Scfg External Interrupt Configuration Register2 (Scfg_ Exintc2)
AT32F425 Series Reference Manual These bits are used to select the input source for the EXINT0 external interrupt. 0000: GPIOA pin0 0001: GPIOB pin0 0010: GPIOC pin0 0101: GPIOF pin0 Others: Reserved 7.2.3 SCFG external interrupt configuration register2 ( SCFG_... -
Page 97: Scfg External Interrupt Configuration Register3 (Scfg_ Exintc3)
AT32F425 Series Reference Manual 7.2.4 SCFG external interrupt configuration register3 ( SCFG_ EXINTC3) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. EXINT11 input source configuration These bits are used to select the input source for the EXINT11 external interrupt. -
Page 98: Scfg Configuration Register2 (Scfg_Cfg2)
AT32F425 Series Reference Manual 0001: GPIOB pin14 0010: GPIOC pin14 Others: Reserved EXINT13 input source configuration These bits are used to select the input source for the EXINT13 external interrupt. 0000: GPIOA pin13 Bit 7:4 EXINT13 0001: GPIOB pin13 0010: GPIOC... -
Page 99: External Interrupt/Event Controller (Exint)
AT32F425 Series Reference Manual 8 External interrupt/Event controller (EXINT) 8.1 EXINT introduction EXINT consists of 22 interrupt lines EXINT_LINE[23:0], each of which can generate an interrupt or event by edge detection trigger or software trigger. EXINT can enable or disable an interrupt or event... -
Page 100: Exint Registers
AT32F425 Series Reference Manual Interrupt initialization procedure Select an interrupt source by setting IOMUX_EXINTCx register (This is required if GPIO is used as an interrupt source) Select an trigger mode by setting EXINT_POLCFG1 and EXINT_POLCFG2 register Enable interrupt or event by setting EXINT_INTEN and EXINT_EVTEN register Generate software trigger by setting EXINT_SWTRG register (This is applied to only software ... -
Page 101: Polarity Configuration Register2 (Exint_ Polcfg2)
AT32F425 Series Reference Manual 8.3.4 Polarity configuration register2 (EXINT_ POLCFG2) Register Reset value Type Description Bit 31: 24 Reserved 0x000 resd Forced to be 0 by hardware. Falling polarity configuration bit on line x These bits are used to select a falling edge to trigger an interrupt and event on line x. -
Page 102: Dma Controller (Dma)
AT32F425 Series Reference Manual 9 DMA controller (DMA) 9.1 Introduction Direct memory access (DMA) controller is designed for 32-bit MCU applications with the aim of enhancing system performance and reducing the generation of interrupts. One DMA controller is available in the microcontroller. Each controller contains 7 DMA channels. Each channel manages memory access requests from one or more peripherals. -
Page 103: Handshake Mechanism
AT32F425 Series Reference Manual Channel priority (CHPL) There are four levels, including very high priority, high priority, medium priority and low priority. If the two channels have the same priority level, then the channel with lower number will get priority over the one with higher number. -
Page 104: Errors
AT32F425 Series Reference Manual Figure 9-3 PWIDTH: byte, MWIDTH: half-word AHB Read Sequence AHB Write Sequence HW3 HW2 HW1 HW0 Half-word2 Half-word0 Half-word3 Half-word1 Figure 9-4 PWIDTH: half-word, MWIDTH: word AHB Read Sequence AHB Write Sequence HW3 HW2 HW1 HW0... -
Page 105: Interrupts
AT32F425 Series Reference Manual 9.3.6 Interrupts An interrupt can be generated on a DMA half-transfer, transfer complete and transfer error. Each channel has its specific interrupt flag, clear and enable bits, as shown in the table below. Table 9-2 DMA interrupt requests... -
Page 106: Dma Registers
AT32F425 Series Reference Manual 9.4 DMA registers Table 9-4 shows DMA register map and their reset values. These peripheral registers must be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits). Table 9-4 DMA register map and reset value... -
Page 107: Dma Interrupt Status Register (Dma_Sts)
AT32F425 Series Reference Manual 9.4.1 DMA interrupt status register (DMA_STS) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description 31: 28 Reserved resd Kept at its default value. Channel 7 data transfer error event flag... -
Page 108: Dma Interrupt Flag Clear Register (Dma_Clr)
AT32F425 Series Reference Manual Channel 4 global event flag 0: No transfer error, half transfer or transfer complete event Bit 12 occurred. 1: Transfer error, half transfer or transfer complete event Channel 3 data transfer error event flag Bit 11 DTERRF3 0: No transfer error occurred. - Page 109 AT32F425 Series Reference Manual Channel 7 transfer complete flag clear Bit 25 FDTFC7 rw1c 0: No effect 1: Clear the FDTF7 flag in the DMA_STS register Channel 7 global interrupt flag clear 0: No effect Bit 24 GFC7 rw1c 1: Clear the DTERRF7, HDTF7, FDTF7 and GF7 flag in...
-
Page 110: Dma Channel-X Configuration Register (Dma_Cxctrl ) (X = 1
AT32F425 Series Reference Manual Channel 3 global interrupt flag clear 0: No effect Bit 8 GFC3 rw1c 1: Clear the DTERRF3, HDTF3, FDTF3 and GF3 flag in the DMA_STS register Channel 2 data transfer error flag clear Bit 7 DTERRFC2... -
Page 111: Dma Channel-X Number Of Data Register (Dma_Cxdtcnt)
AT32F425 Series Reference Manual 1: Enabled. Circular mode Bit 5 0: Disabled 1: Enabled. Data transfer direction Bit 4 0: Read from peripherals 1: Read from memory Data transfer error interrupt enable Bit 3 DTERRIEN 0: Disabled 1: Enabled. Half-transfer interrupt enable... -
Page 112: Dma Channel Source Register (Dma_Src_Sel0)
AT32F425 Series Reference Manual 9.4.7 DMA channel source register (DMA_SRC_SEL0) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description CH4 source select Bit 31: 24 CH4_SRC 0x00 When DMA_FLEX_EN=1, channel 4 is selected by the CH4_SRC. -
Page 113: Crc Calculation Unit (Crc)
AT32F425 Series Reference Manual 10 CRC calculation unit (CRC) 10.1 CRC introduction The Cyclic Redundancy Check (CRC) is an independent peripheral with CRC check feature. It follows CRC32 standard. The CRC_CTRL register is used to select input data toggle (word, REVOD=1) or output data toggle (byte, REVID=01;... -
Page 114: Control Register (Crc_Ctrl)
AT32F425 Series Reference Manual 10.2.3 Control register (CRC_CTRL) Register Reset value Type Description Bit 31: 8 Reserved 0x000000 resd Kept at its default value. Reverse output data Set and cleared by software. This bit is used to control Bit 7... -
Page 115: C Interface
AT32F425 Series Reference Manual 11 I C interface 11.1 I C introduction C (inter-integrated circuit) bus interface manages the communication between the microcontroller and serial I C bus. It supports master and slave modes, with up to 1 Mbit/s of communication speed (enhanced edition). -
Page 116: I 2 C Interface
AT32F425 Series Reference Manual 11.4 I C interface Figure 11-2 shows the block diagram of I C function Figure 11-2 I2C function block diagram I2CCLK Clock Control TIMEOUT_Frozen I2C_SCL_out Master clock generation CPU_Halt_en GPIO I2C_SCL Slave clock Digital I2C_SCL_in stretching... - Page 117 AT32F425 Series Reference Manual Slave address masking capability The Slave address 2 (OADDR2) is maskable, which is done by setting the ADDR2MASK[2: 0]. ― 0: Address bit [7: 1] ― 1: Address bit [7: 2] ― 2: Address bit [7: 3] ―...
-
Page 118: C Timing Control
AT32F425 Series Reference Manual Address reception: The SCL clock is not stretched when the address received by slave matches the local address enabled (ADDRF=1 in the I2C_STS) Data reception: If there is data to be read in the I2C_RXDT register before the next ACK signal, an overflow will occur, and the OUF bit will also be set in the I2C_STS register ... -
Page 119: Data Transfer Management
AT32F425 Series Reference Manual In master mode, the width of SCL signals (high and low) can be configured freely by setting the DIV[7: 0], SCLH[7: 0] and SCLL[7: 0] in the I2C_CLKCTRL register. SCL low: When the SCL low signal is detected, the internal SCLL counter starts counting until it reaches the SCLL value. -
Page 120: C Master Communication Flow
AT32F425 Series Reference Manual ― Step 3: After the completion of 255-byte data transfer, the TCRLD is set in the I2C_STS register, and then configure CNT[7:0]=255 for continuous transfer, the remaiming bytes are 345-255=90 ― Step 4: After the completion of the seond 255-byte data transfer, the TCRLD is set in the I2C_STS register, and then set RLDEN=0 to disable reload mode before setting CNT[7:0]=90 for continuous transfer. - Page 121 AT32F425 Series Reference Manual ― SCL low duration: SCLL[7: 0] Set the number of bytes to be transferred ― ≤255 bytes Disable reload mode by setting RLDEN=0 in the I2C_CTRL2 register Set CNT[7:0]=N in the I2C_CTRL2 register ― ＞255 bytes...
-
Page 122: Figure 11-4 I 2 C Master Transmission Flow
AT32F425 Series Reference Manual ― Wait for the generation of a STOP condition, when a STOP condition is generated, STOPF=1 is asserted in the I2C_STS register. The STOPF flag can be cleared by setting STOPC=1 in the I2C_CLR register, and then transfer stops... -
Page 123: Figure 11-5 Transfer Sequence Of I
AT32F425 Series Reference Manual Figure 11-5 Transfer sequence of I C master transmitter I2C master transmitter N bytes Initial setting flow : 1. I2C_CTRL2_CNT = N 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL2_GENSTART = 1 Initial setting... -
Page 124: Figure 11-7 Transfer Sequence Of I
AT32F425 Series Reference Manual Figure 11-7 Transfer sequence of I C master receiver I2C master receiver N bytes Initial setting flow : 1. I2C_CTRL2_CNT = N 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL2_GENSTART = 1 Initial setting... -
Page 125: C Slave Communication Flow
AT32F425 Series Reference Manual 11.4.4 I C slave communication flow C clock initialization (by setting the I2C_CLKCTRL register) C clock divider: DIV[7: 0] ― I ― Data hold time (t ): SDAD[3: 0] H D ;D A T ― Data setup time (t ): SCLD[3: 0] S U ;D AT... - Page 126 AT32F425 Series Reference Manual software, and then write the first data to the TXDT register, the TDBE is cleared ― Write operation through interrupts or DMA: Clear the TXDT register by setting the TDBE bit through software, then set the TDIS bit to generate a TDIS event, which generates an interrupt or DMA request.
-
Page 127: Figure 11-10 I 2 C Slave Transmission Flow
AT32F425 Series Reference Manual Slave transmission Figure 11-10 I C slave transmission flow Slave initialization (if STRETCH =1, write data to I2C_TXDT_DT ) I2C_STS_ADDRF=1? Read I2C_STS_ADDR Read I2C_STS_SDIR Set I2C_CLR_ADDRC =1 I2C_STS_ACKFAIL=1? Write I2C_CLR_ACKFAILC I2C_STS_TDIS=1? I2C_STS_STOPF=1? Write I2C_TXDT_DT Set I2C_STS_TDBE = 1... -
Page 128: Figure 11-12 I 2 C Slave Receive Flow
AT32F425 Series Reference Manual Slave receive Figure 11-12 I C slave receive flow Slave initialization I2C_STS_ADDRF=1? Read I2C_STS_ADDR Read I2C_STS_SDIR Set I2C_CLR_ADDRC =1 I2C_STS_STOPF=1? Set I2C_CLR_STOPC=1 I2C_STS_RDBF=1? Read I2C_RXDT_DT Figure 11-13 I C slave receive timing I2C Slave receiver N bytes from I2C master... -
Page 129: Smbus
AT32F425 Series Reference Manual 11.4.5 SMBus The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other. It is based on I C. With SMBus, the device can provide manufacturer information, tell the system its model/part number, report different types of errors and accept control parameters and so on. -
Page 130: Table 11-3 Smbus Timeout Specification
AT32F425 Series Reference Manual PEC calculation is enabled when PECEN=1 to check address and data. PEC transfer: ― Host: PEC transfer is enabled by setting PECTEN=1 in the I2C_CTRL2 register. The host sends a PEC as soon as the number of data transfer reaches N-1 (CNT=N) ―... -
Page 131: Smbus Master Communication Flow
AT32F425 Series Reference Manual Slave receive byte control In slave receive mode, the slave receive byte control mode (SCTRL=1) can be used to control ACK/NACK signals of each received byte. Refer to section 11.4.2 for more information. Table 11-5 SMBus mode configuration... - Page 132 AT32F425 Series Reference Manual Set transfer direction (by setting the DIR bit in the I2C_CTRL2 register) ― DIR=0: Master reception ― DIR=1: Master transmission Start data transfer In case of GENSTART=1 in the I2C_CTRL2 register, the master starts sending a START condition and slave address.
-
Page 133: Figure 11-14 Smbus Master Transmission Flow
AT32F425 Series Reference Manual SMBus master transmission flow Figure 11-14 SMBus master transmission flow Master initialization Set I2C_CTRL2_CNT = N+1 I2C_CT RL1_PE CEN=1 I2C_CT RL2_PE CTEN=1 Configure slave address GENSTART = 1 Wait I2C_STS_STOPF=1 I2C_STS_ACKFAIL=1? Set I2C_CLR_STOPC=1 I2C_CLR_ACKFAILC=1 I2C_STS_TDIS=1? Write I2C_TXDT_DT... -
Page 134: Figure 11-15 Smbus Master Transmission Timing
AT32F425 Series Reference Manual Figure 11-15 SMBus master transmission timing SMBus master transmitter N bytes + PEC Initial setting flow : 1. I2C_CTRL2_CNT = N+ 1 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL1_PECEN = 1 5. I2C_CTRL2_PECTEN = 1 6. -
Page 135: Smbus Slave Communication Flow
AT32F425 Series Reference Manual Figure 11-17 SMBus master receive timing SMBus master receiver N bytes +PEC Initial setting flow : 1. I2C_CTRL2_CNT = N+ 1 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL1_PECEN = 1 5. I2C_CTRL2_PECTEN = 1 6. - Page 136 AT32F425 Series Reference Manual The ADDRF flag can be cleared by setting ADDRC=1 in the I2C_CLR register, and then data transfer starts. Data transfer (slave transmission, clock stretching enabled, STRETCH=0) After address matching: I2C_TXDT data register becomes empty, the shift register becomes empty, and TDIS=1 in the...
-
Page 137: Figure 11-18 Smbus Slave Transmission Flow
AT32F425 Series Reference Manual SMBus slave transmission Figure 11-18 SMBus slave transmission flow Slave initialization I2C_CTRL1_PECEN = 1 I2C_STS_ADDRF=1? Set I2C_CTRL2_CNT =N+ 1 I2C_CTRL2_PECTEN = 1 I2C_CLR_ADDRC =1 I2C_STS_ACKFAIL=1? Write I2C_CLR_ACKFAILC I2C_STS_TDIS=1? I2C_STS_STOPF=1? Write I2C_TXDT_DT Set I2C_STS_TDBE = 1 and I2C_CLR_TDIS = 1... -
Page 138: Figure 11-20 Smbus Slave Receive Flow
AT32F425 Series Reference Manual SMBus slave receive Figure 11-20 SMBus slave receive flow Slave initialization I2C_CTRL1_PECEN = 1 Read I2C_RXDT_DT Set I2C_CTRL2_NACKEN = 0 I2C_CTRL2_RLDEN =0 I2C_STS_ADDRF=1? I2C_CTRL2_CNT = 1 Set I2C_CTRL2, CNT = 1, RLDEN=1 , PECTEN = 1... -
Page 139: Data Transfer Using Dma
AT32F425 Series Reference Manual 11.4.8 Data transfer using DMA C data transfer can be done using DMA controller so as to reduce the burden on the CPU. The TDIEN and RDIEN must be set 0 when using DMA for data transfer. - Page 140 AT32F425 Series Reference Manual Overrun/underrun ERRIEN OUFC Arbitration lost ARLOST ERRIEN ARLOSTC Bus error BUSERR ERRIEN BUSERRC Overrun/Underrun (OUF) In slave mode, an underrun/overrun may appear if the clock stretching feature is disabled (STRETCH=1 in the I2C_CTRL1 register) In slave transmit mode: if data has not yet been written to the TXDT register before the transmission of the first bit of the to-be-transferred data (that is, before the generation of SDA edge), an underrun error may occur, and the OUF bit is set in the I2C_STS register, sending 0xFF to the bus.
-
Page 141: I 2 C Interrupt Requests
AT32F425 Series Reference Manual 11.5 I C interrupt requests The following table lists all the I C interrupt requests. Table 11-7 I C interrupt requests Interrupt event Event flag Enable control bit Address matched ADDRF ADDRIEN Acknowledge failure ACKFAIL ACKFAILIEN... -
Page 142: Control Register1 (I2C_Ctrl1)
AT32F425 Series Reference Manual 11.7.1 Control register1 (I2C_CTRL1) Register Reset value Type Description Bit 31:24 Reserved 0x00 Kept at its default value. PEC calculation enable Bit 23 PECEN 0: PEC calculation disabled 1: PEC calculation enabled SMBus alert enable / pin set... -
Page 143: Control Register2 (I2C_Ctrl2)
AT32F425 Series Reference Manual 0: Acknowledge fail interrupt disabled 1: Acknowledge fail interrupt enabled Address match interrupt enable Bit 3 ADDRIEN 0: Address match interrupt disabled 1: Address match interrupt enabled Data receive interrupt enable Bit 2 RDIEN resd 0: Data receive interrupt disabled... -
Page 144: Own Address Register2 (I2C_Oaddr2)
AT32F425 Series Reference Manual 1: 10-bit address mode Own address1 Bit 9: 0 ADDR1[9: 0] 0x000 In 7-bit address mode, bit 0 and bit [9：8] don’t care. 11.7.4 Own address register2 (I2C_OADDR2) Register Reset value Type Description Bit 31: 16... -
Page 145: Status Register (I2C_Sts)
AT32F425 Series Reference Manual 11.7.7 Status register (I2C_STS) Register Reset value Type Description Bit 31: 24 Reserved 0x00 Kept at its default value. Slave address matching value In 7-bit address mode: Slave address received Bit 23: 17 ADDR[6: 0] 0x00... -
Page 146: Status Clear Register (I2C_Clr)
AT32F425 Series Reference Manual 1: Acknowledge failure 0~7 bit address head match flag Bit 3 ADDRHF 0: 0~7 bit address head mismatch 1: 0~7 bit address head match Receive data buffer full flag Bit 2 RDBF 0: Data register has not received data yet... -
Page 147: Universal Synchronous/Asynchronous Receiver/Transmitter (Usart)
AT32F425 Series Reference Manual 12 Universal synchronous/asynchronous receiver/transmitter (USART) 12.1 USART introduction The universal synchronous/asynchronous receiver/transmitter (USART) serves an interface for communication by means of various configurations and peripherals with different data formats. It supports asynchronous full-duplex and half-duplex as well as synchronous transfer. With a... - Page 148 AT32F425 Series Reference Manual USART main features: Programmable full-duplex or half-duplex communication ─ Full-duplex, asynchronous communication ─ Half-duplex, single communication Programmable communication modes ─ NRZ standard format (Mark/Space) ─ LIN (Local Interconnection Network): LIN master with break generation capability and LIN slave with break detection capability ─...
-
Page 149: Full-Duplex/Half-Duplex Selector
AT32F425 Series Reference Manual ─ Noise error ─ Parity error 12.2 Full-duplex/half-duplex selector The full-duplex and half-duplex selector enables USART to perform data exchanges with peripherals in full-duplex or half-duplex mode, which is achieved by setting the corresponding registers. In two-wire unindirectional full-duplex mode (by default), TX pin is used for data output, while the RX pin is used for data input. -
Page 150: Usart Frame Format And Configuration
AT32F425 Series Reference Manual USART_DT[8. When parity check is enabled, if DBN1,DBN0=10, the MSB stands for USART_DT[5; if DBN1,DBN0=00, the MSB stands for USART_DT[6]; if DBN1,DBN0=01, the MSB stands for USART_DT[7]. When the ID[3: 0] bit is selected, the four LSB bits indicate the ID value; When the ID[7: 0] bit is selected, all of the LSB bits indicates the ID value, except for the above parity check bits and MSB bits. -
Page 151: Baud Rate Generation
AT32F425 Series Reference Manual Configure the source of DMA transfer: Configure the USART_DT register address as the source of DMA transfer in the DMA control register. Data will be loaded from the USART_DT register to the programmed destination after reception request is received by DMA. -
Page 152: Transmitter
AT32F425 Series Reference Manual 12.7 Transmitter 12.7.1 Transmitter introduction USART transmitter has its individual TEN control bit. The transmitter and receiver share the same baud rate that is programmable. There is a transmit data buffer (TDR) and a transmit shift register in the USART. -
Page 153: Receiver Configuration
AT32F425 Series Reference Manual 12.8.2 Receiver configuration Configuration procedure: 1. USART enalbe: UEN bit is set. 2. Full-duplex/half-duplex configuration: Refer to full-duplex/half-duplex selector for more information. 3. Mode configuration: Refer to mode selector for more information. 4. Frame format configuration: Refer to frame format for more information. -
Page 154: Start Bit And Noise Detection
AT32F425 Series Reference Manual If RDBF=1, it indicates that the last valid data is still stored in the receive data buffer, and can be read. If RDBF=0, it indicates that the last valid data in the receive data buffer has already been read. -
Page 155: Interrupt Requests
AT32F425 Series Reference Manual Figure 12-2 Tx/Rx swap USART_TX USART_TX USART_RX USART_RX USART USART TRPSWAP=0 TRPSWAP=1 Note: The SWAP (USART_CTRL2[15]) can be modified only when the USART is disabled (UEN=0) 12.10 Interrupt requests USART interrupt generator serves as a control center of USART interrupts. It is used to monitor the interrupt source inside the USART in real time and the generation of interrupts according to the programmed interrupt control bits. -
Page 156: I/O Pin Control
AT32F425 Series Reference Manual 12.11 I/O pin control The following five interfaces are used for USART communication. RX: Serial data input. TX: Serial data output. In single-wire half-duplex and Smartcard mode, the TX pin is used as an I/O for data transmission and reception. -
Page 157: Data Register (Usart_Dt)
AT32F425 Series Reference Manual Idle flag This bit is set by hardware when an idle line is detected. It is cleared by software. (Read USART_DT register followed Bit 4 IDLEF by a USART_DT read operation) 0: No idle line is detected. - Page 158 AT32F425 Series Reference Manual 11: Write operation forbidden. Bit 27: 26 Reserved resd Kept at its default value. Transmit start delay time） In RS485 mode, the first data (in sequential transmit mode) is transmitted after a period of time of being written so as...
-
Page 159: Control Register2 (Usart_Ctrl2)
AT32F425 Series Reference Manual 0: Receiver is disabled. 1: Receiver is enabled. Receiver mute This bit determines if the receiver is in mute mode or not. It is set or cleared by software. When the idle line is used to wake up from mute mode, this bit is cleared by hardware after wake up. -
Page 160: Control Register3 (Usart_Ctrl3)
AT32F425 Series Reference Manual 0: Disabled 1: Enabled Break frame bit num This bit is used to select 11-bit or 10-bit break frame. Bit 5 BFBN 0: 10-bit break frame 1: 11-bit break frame Identification bit num This bit is used to select ID bit number. -
Page 161: Guard Time And Divider Register (Usart_Gdiv)
AT32F425 Series Reference Manual 0: IrDA is disabled. 1: IrDA is enabled. Error interrupt enable An interrupt is generated when a framing error, overflow Bit 0 ERRIEN error or noise error occurs. 0: Error interrupt is disabled. 1: Error interrupt is enabled. -
Page 162: Serial Peripheral Interface (Spi)
AT32F425 Series Reference Manual 13 Serial peripheral interface (SPI) 13.1 SPI introduction The SPI interace supports either the SPI protocol or the I S protocoal, depending on software configuration. This chapter gives an introduction of the main features and congiruation procedure of SPI used as SPI or I 13.2 Function overview... -
Page 163: Full-Duplex/Half-Duplex Selector
AT32F425 Series Reference Manual Programmable clock plarity and phase Programmable data transfer order (MSB-first or LSB-first) Programmable error interrupt flags (CS pulse error, receiver overflow error, master mode error and CRC error) Programmable transmit data buffer empty interrupt and receive data buffer full interrupt Support transmission and reception using DMA ... -
Page 164: Figure 13-3 Single-Wire Unidirectional Receive Only In Spi Master Mode
AT32F425 Series Reference Manual Figure 13-3 Single-wire unidirectional receive only in SPI master mode SPI master SPI slave MISO MISO MOSI MOSI Figure 13-4 Single-wire unidirectional receive only in SPI slave mode SPI master SPI slave MISO MISO MOSI MOSI In master mode, it is necessary to wait until the second-to-last RDBF bit is set and then another SPI_CPK period before disabling the SPI. -
Page 165: Chip Select Controller
AT32F425 Series Reference Manual Figure 13-5 Single-wire bidirectional half-duplex mode SPI master SPI slave MISO MISO MOSI MOSI When the SPI is selected for data transmission in single-wire bidirectional half-duplex mode (master or slave), the TDBE bit must be set, and the BF must be 0 before disabling the SPI. The power-saving mode (or disabling SPI system clock) cannot be entered unless the SPI is disabled. -
Page 166: Spi_Sck Controller
AT32F425 Series Reference Manual 13.2.4 SPI_SCK controller The SPI protocol adopts synchronous transmission. In master mode with the SPI being used as SPI, it is required to generate a communication clock for data reception and transmission on the SPI, and the communication clock should be output to the slave via IO for data reception and transmission. -
Page 167: Dma Transfer
AT32F425 Series Reference Manual 13.2.6 DMA transfer The SPI supports write and read operations with DMA. Refer to the following configuration procedure. Special attention should be paid to: when the CRC calculation and check is enabled, the number of data transferred by DMA is configured as the number of the data to be transferred. The number of data read with DMA is configured as the number of the data to be received. -
Page 168: Transmitter
AT32F425 Series Reference Manual a CS pulse error is detected. At this point, the detected pulse error will be discarded by the SPI. However, since there is something wrong with the CS signal, the software should disable the SPI slave and re- configure the SPI master before re-enabling the SPI slave for communication. -
Page 169: Motorola Mode
AT32F425 Series Reference Manual Receiver configuration procedure: Configure full-duplex/half-duplex selector Configure chip select controller Configure SPI_SCK controller Configure CRC (if necessary) Configure DMA transfer (if necessary) If the DMA transfer mode is not used, the software will check whether to enable receive data interrupt (RDBEIE =1) through the RDBE bit. -
Page 170: Figure 13-7 Slave Full-Duplex Communications
AT32F425 Series Reference Manual Figure 13-7 Slave full-duplex communications Sampling Drive MISO MOSI TDBE flag Transmit buffer empty and RDBF flag software can write data BF flag Software needs to read the received data Half-duplex communication – master transmit Configured as follows:... -
Page 171: Ti Mode
AT32F425 Series Reference Manual FBN=0: 8-bit frame Slave transmit: 0xaa, 0xcc, 0xaa Figure 13-10 Slave half-duplex transmit Drive MISO Transmit buffer empty and TDBE flag software can write data BF flag Half-duplex communication – master receive Configured as follows: MSTEN=1: Master enable... -
Page 172: Interrupts
AT32F425 Series Reference Manual Figure 13-13 TI mode continous transfer with dummy CLK Write the to-be-transmitted data MISO MOSI dumm When the to-be-transmitted data is written after the falling SCK edge corresponding to the last data of the current transmit frame, the host always issues a valid SCK clock after 1T SCK + 4T PCLK. If the slave still does not detect a valid CS pulse at the end of the current data reception, it disables MISO output after 1/2T SCK + 3T PCLK to control MISO floating. -
Page 173: Precautions
AT32F425 Series Reference Manual 13.2.14 Precautions CRC value is obtained by software reading DT register at the end of CRC reception In the case of CPOL=1 and CPHA=1, the clock divided by 3 that is generated inside the SPI must be less than 32 MHz. -
Page 174: S Full-Duplex
AT32F425 Series Reference Manual Programmable channel bits (16 bit, 32 bit) Programmable audio protocol ─ I S Philips standard ─ MSB-aligned standard (left-aligned) ─ LSB-aligned standard (right-aligned) ─ PCM standard (long or short frame) S full-duplex ... -
Page 175: Figure 13-18 I 2 S Slave Device Transmission
AT32F425 Series Reference Manual Figure 13-18 I S slave device transmission I2S master I2S slave Slave device reception: Set the I2SMSEL bit, and OPERSEL[1:0]=01, the I S will work in slave device reception mode. Figure 13-19 I S slave device reception... -
Page 176: Audio Protocol Selector
AT32F425 Series Reference Manual Figure 13-21 I S master device reception I2S master I2S slave 13.3.4 Audio protocol selector While being used as I S, the SPI supports multiple audio protocols. The user can control the audio protol selector through software configuration to select the desired audio protocol, with the data bits and channel bits being controlled by the audio protocol selector. -
Page 177: I2S_Clk Controller
AT32F425 Series Reference Manual Philips standard, PCM standard, MSB-aligned or LSB-aligned standard, 32-bit data and 32-bit channel The data bit is the same as the channel bit. Each channel requires two read/write operations from/to the SPI_DT register, and the number of DMA transfer is 2. These 32-bit data are proceeded in two times, with 16-bit data each time. -
Page 178: Dma Transfer
AT32F425 Series Reference Manual Table 13-1 Audio frequency precision using system clock 16bit 32bit Target SCLK (MHz) I2S_ODD RealFs Error I2S_ODD RealFs Error (Hz) 192000 187500 2.34% 187500 2.34% 96000 97826.09 1.90% 93750 2.34% 44100 44117.65 0.04% 43269.23 1.88% 32000 32142.86... -
Page 179: Transmitter/Receiver
AT32F425 Series Reference Manual 13.3.7 Transmitter/Receiver Whether being used as SPI or I2S, there is no difference for CPU. The SPI (in whatever mode) shares the same base address, the same SPI_DT register, the same transmitter and receiver. The SPI transmitter and receiver is responsible fore sending and receiving the desired data frame according to the configuration of the communication controller. -
Page 180: Interrupts
AT32F425 Series Reference Manual Figure 13-23 Audio standard timings 16CK Left Right channel Philips channel standard 16CK Right Left channel 左声道 channel standard Right Left channel channel stanard 16CK 13CK PCM standard long frame PCM standard short frame 13.3.9 Interrupts... -
Page 181: Spi Registers
AT32F425 Series Reference Manual 13.4 SPI registers These peripheral registers must be accessed by half-word (16 bits) or word (32 bits). Table 13-2 SPI register map and reset value Register Offset Reset value SPI_CTRL1 0x00 0x0000 SPI_CTRL2 0x04 0x0000 SPI_STS... -
Page 182: Spi Control Register2 (Spi_Ctrl2)
AT32F425 Series Reference Manual This bit is used to select for MST transfer first or LSB transfer first. 0: MSB 1: LSB SPI enable Bit 6 SPIEN 0: Disabled 1: Enabled Master clock frequency division In master mode, the peripheral clock divided by the prescaler is used as SPI clock. -
Page 183: Spi Status Register (Spi_Sts)
AT32F425 Series Reference Manual I2S mode. Bit 3 Reserved resd Kept at its default value Hardware CS output enable This bit is valid only in master mode. When this bit is set, the I/O output on the CS pin is low; when this bit is 0, the... -
Page 184: Spi Data Register (Spi_Dt)
AT32F425 Series Reference Manual Receive data buffer full Bit 0 RDBF 0: Transmit data buffer is not full. 1: Transmit data buffer is full. 13.4.4 SPI data register (SPI_DT) Register Reset value Type Description Data value Bit 15: 0 0x0000 This register controls read and write operations. -
Page 185: Spi_I2S Prescaler Register (Spi_I2Sclkp)
AT32F425 Series Reference Manual 0: Short frame synchronization 1: Long frame synchronization Bit 6 Reserved resd Kept at its default value S standard select 00: Philips standard Bit 5: 4 STDSEL 01: MSB-aligned standard (left-aligned) 10: LSB-aligned standard (right-aligned) 11: PCM standard... -
Page 186: Timer
AT32F425 Series Reference Manual 14 Timer AT32F425 timers include basic timers, general-purpose timers, and advanced timers. Please refer to Section 14.1 Section 14.5 for the detailed function modes. All functions of different timers are shown in the following tables. Table 14-1 TMR functional comparison... -
Page 187: Basic Timer (Tmr6 And Tmr7)
AT32F425 Series Reference Manual 14.1 Basic timer (TMR6 and TMR7) 14.1.1 TMR6 and TMR7 introduction Each of the basic timers (TMR6 and TMR7) includes a 16-bit up counter and the corresponding control logic. without being connected to external I/Os, they can be used for a basic timing. -
Page 188: Debug Mode
AT32F425 Series Reference Manual Figure 14-3 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-4 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-5 Counting timing diagram when the prescaler division is 4... -
Page 189: Tmr6 And Tmr7 Control Register2 (Tmrx_Ctrl2)
AT32F425 Series Reference Manual 0: Period buffer is disabled. 1: Period buffer is enabled. Bit 6: 4 Reserved resd Kept at its default value. One cycle mode enable This bit is used to select whether to stop the counter at... -
Page 190: Tmr6 And Tmr7 Software Event Register (Tmrx_Swevt)
AT32F425 Series Reference Manual 1: Update event occurs, and OVFEN=0, and OVFS=0 in the TMRx_CTRL1 register: − An update event occurs when OVFG=1 in the TMRx_SWEVE register − An update event occurs when the counter value (CVAL) is reinitialized by a trigger event. -
Page 191: Tmr2 And Tmr3 Functional Overview
AT32F425 Series Reference Manual Figure 14-6 General-purpose timer block diagram C4IRAW TMRX_CH4 C4ORAW Output C1OUT TMRx_CH1 control CxDT Edge detector Input C3IRAW C3ORAW Output TMRX_CH3 C2OUT TMRx_CH2 control Prescaler C2IRAW TMRX_CH2 Input filter C2ORAW Output C3OUT CxDT TMRx_CH3 control Output... -
Page 192: Figure 14-9 Counting In External Clock Mode A
AT32F425 Series Reference Manual Note: The delay between the signal on the input side and the actual clock of the counter is due to the synchronization circuit. Figure 14-9 Counting in external clock mode A TMR_CLK C2IRAW CNT_CLK COUNTER STIS[2:0]... -
Page 193: Counting Mode
AT32F425 Series Reference Manual Table 14-3 TMRx internal trigger connection Slave controler （STIS = 000） （STIS = 001） （STIS = 010） （STIS = 011） TMR1 TMR15 TMR2 TMR3 TMR2 TMR1 TMR15 TMR3 USB_OTG_SOF TMR3 TMR1 TMR2 TMR15 TMR15 TMR2 TMR3... -
Page 194: Figure 14-14 Overflow Event When Prben=1
AT32F425 Series Reference Manual Figure 14-14 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed, and generates a counter underflow event. -
Page 195: Tmr Input Function
AT32F425 Series Reference Manual Table 14-4 Counting direction versus encoder signals C1INFP1 signal C2INFP2 signal Level on opposite signal Active edge (C1INFP1 to C2IN, C2INFP2 to C1IN) Rising Falling Rising Falling High Down No count No count Count on C1IN only... -
Page 196: Tmr Output Function
AT32F425 Series Reference Manual Input mode In input mode, the TMRx_CxDT registers latch the current counter values after the selected triggle signal is detected, and the capture compare interrupt flag bit (CxIF) is set. An interrupt or a DMA request will be generated if the CxIEN and CxDEN bits are enabled. -
Page 197: Figure 14-21 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F425 Series Reference Manual Output compare mode: Set CxOCTRL=3’b001/010/011 to enable output compare mode. In this case, when the counter value matches the value of the CxDT register, the CxORAW is forced high, low or toggling. One-pulse mode：This is a particular case of PWM mode. Set OCMEN=1 to enable one-pulse mode. -
Page 198: Tmr Synchronization
AT32F425 Series Reference Manual Figure 14-23 Up/down counting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW ≥32 C1DT[15：0] C1ORAW Figure 14-24 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT CxORAW clear When the CxOSEN bit is set, the CxORAW signal for a given channel is cleared by applying a high level to the EXT input. -
Page 199: Figure 14-26 Example Of Reset Mode
AT32F425 Series Reference Manual Slave mode: Reset mode The counter and its prescaler can be reset by a selected trigger signal. An overflow event is generated when OVFS=0. Figure 14-26 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0]... -
Page 200: Figure 14-29 Master/Slave Timer Connection
AT32F425 Series Reference Manual Master/slave timer interconnection Both Master and slave timer can be configured in different master and slave modes respectively. The combination of both them can be used for various purposes. Figure 14-29 provides an example of interconnection between master timer and slave timer. -
Page 201: Debug Mode
AT32F425 Series Reference Manual Starting master and slave timers synchronously by an external trigger: In this example, configure the master timer as master/slave mode synchronously and enable its slave timer synchronization function. This mode is used for synchronization between master timer and slave timer. -
Page 202: Tmr2 And Tmr3 Control Register1 (Tmrx_Ctrl1)
AT32F425 Series Reference Manual TMRx_PR 0x2C 0x0000 TMRx_C1DT 0x34 0x0000 TMRx_C2DT 0x38 0x0000 TMRx_C3DT 0x3C 0x0000 TMRx_C4DT 0x40 0x0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000 14.2.4.1 TMR2 and TMR3 control register1 (TMRx_CTRL1) Register Reset value Type Description Bit 15: 11... -
Page 203: Tmr2 And Tmr3 Control Register2 (Tmrx_Ctrl2)
AT32F425 Series Reference Manual 14.2.4.2 TMR2 and TMR3 control register2 (TMRx_CTRL2) Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at its default value. C1IN selection 0: CH1 pin is connected to C1IRAW input Bit 7 C1INSEL... -
Page 204: Tmr2 And Tmr3 Dma/Interrupt Enable Register (Tmrx_Iden)
AT32F425 Series Reference Manual 1: Enabled Subordinate TMR input selection This field is used to select the subordinate TMR input. 000: Internal selection 0 (IS0) 001: Internal selection 1 (IS1) 010: Internal selection 2 (IS2) 011: Internal selection 3 (IS3) -
Page 205: Tmr2 And Tmr3 Interrupt Status Register (Tmrx_Ists)
AT32F425 Series Reference Manual Channel 2 interrupt enable Bit 2 C2IEN 0: Disabled 1: Enabled Channel 1 interrupt enable Bit 1 C1IEN 0: Disabled 1: Enabled Overflow interrupt enable Bit 0 OVFIEN 0: Disabled 1: Enabled 14.2.4.5 TMR2 and TMR3 interrupt status register (TMRx_ISTS) -
Page 206: Tmr2 And Tmr3 Software Event Register (Tmrx_Sw Evt)
AT32F425 Series Reference Manual 14.2.4.6 TMR2 and TMR3 software event register (TMRx_SWEVT) Register Reset value Type Description Kept at its default value. Bit 15: 7 Reserved 0x000 resd Trigger event triggered by software This bit is set by software to generate a trigger event. - Page 207 AT32F425 Series Reference Manual －OWCDIR=1, C1ORAW is high once TMRx_ C1DT <TMRx_CVAL, else low. Note: In the configurations othern than 000’, the C1OUT is connected to C1ORAW. The C1OUT output level is not only subject to the changes of C1ORAW, but also the output polarity set by CCTRL.
-
Page 208: Tmr2 And Tmr3 Channel Mode Register2 (Tmrx_Cm2)
AT32F425 Series Reference Manual Channel 1 input divider This field defines Channel 1 input divider. 00: No divider. An input capture is generated at each active edge. Bit 3: 2 C1IDIV 01: An input compare is generated every 2 active edges... -
Page 209: Tmr2 And Tmr3 Channel Control Register (Tmrx_Cctrl)
AT32F425 Series Reference Manual This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: 00: Output 01: Input, C3IN is mapped on C3IRAW 10: Input, C3IN is mapped on C4IRAW 11: Input, C3IN is mapped on STCI. -
Page 210: Tmr2 And Tmr3 Division Value (Tmrx_Div)
AT32F425 Series Reference Manual 14.2.4.11 TMR2 and TMR3 division value (TMRx_DIV) Register Reset value Type Description Divider value The counter clock frequency f /(DIV[15: CK_CNT TMR_CLK Bit 15: 0 0x0000 0]+1). DIV contains the value written at an overflow event. -
Page 211: Tmr2 And Tmr3 Channel 4 Data Register (Tmrx_C4Dt)
AT32F425 Series Reference Manual Whether the written value takes effective immediately depends on the C3OBEN bit, and the corresponding output is generated on C3OUT as configured. 14.2.4.16 TMR2 and TMR3 channel 4 data register (TMRx_C4DT) Register Reset value Type Description... -
Page 212: Tmr13 And Tmr14 Functional Overview
AT32F425 Series Reference Manual Figure 14-32 Block diagram of general-purpose TMR13/14 CxDT Edge detector input C1IRAW C1IFP1 C1ORAW C1OUT Output TMRX_CH1 TMRx_CH1 prescaler control Input filter CxDT output Stop, clear Trigger TMRxCLK from RCC CNT Counter Period register controller DIV prescaler... -
Page 213: Tmr Input Function
AT32F425 Series Reference Manual Figure 14-35 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear 14.3.3.3 TMR input function Each timer of TMR13 and TMR14 has an independent channel that can be configured as input or output. -
Page 214: Tmr Output Function
AT32F425 Series Reference Manual 14.3.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. Figure 14-38 Capture/compare channel output stage (channel 1) -
Page 215: Debug Mode
AT32F425 Series Reference Manual Figure 14-39 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW Figure 14-40 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0]... -
Page 216: Tmr13 And Tmr14 Control Register1 (Tmrx_Ctrl1)
AT32F425 Series Reference Manual Table 14-7 TMR13 and TMR14 register map and reset value Register name Register Reset value TMRx_CTRL1 0x00 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CM1 0x18 0x0000 TMRx_CCTRL 0x20 0x0000 TMRx_CVAL 0x24 0x0000... -
Page 217: Tmr13 And Tmr14 Interrupt Status Register (Tmrx_Ists)
AT32F425 Series Reference Manual 14.3.4.3 TMR13 and TMR14 interrupt status register (TMRx_ISTS) Register Reset value Type Description Bit 15: 10 Reserved resd Kept at its default value. Channel 1 recapture flag This bit indicates whether a recapture is detected when C1IF=1. - Page 218 AT32F425 Series Reference Manual – OWCDIR=0, C1ORAW is high once TMRx_C1DT>TMRx_CVAL, else low; － OWCDIR=1, C1ORAW is low once TMRx_ C1DT <TMRx_CVAL, else high; 111: PWM mode B － OWCDIR=0, C1ORAW is low once TMRx_ C1DT >TMRx_CVAL, else high; － OWCDIR=1, C1ORAW is high once TMRx_ C1DT <TMRx_CVAL, else low.
-
Page 219: Tmr13 And Tmr14 Channel Control Register (Tmrx_Cctrl)
AT32F425 Series Reference Manual 00: No divider. An input capture is generated at each active edge. 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’... -
Page 220: Tmr13 And Tmr14 Channel 1 Data Register (Tmrx_C1Dt)
AT32F425 Series Reference Manual 14.3.4.10 TMR13 and TMR14 channel 1 data register (TMRx_C1DT) Register Reset value Type Description Channel 1 data register When the channel 1 is configured as input mode: The C1DT is the CVAL value stored by the last channel... -
Page 221: Tmr15 Functional Overview
AT32F425 Series Reference Manual Figure 14-42 TMR15 block diagram Clock failure event From clock control CSS(Clock Security System) Filter Polarity selection TMRx_BRK CxDT (INPUT) Edge detector TMRx_CH2 C2OUT C2ORAW Output C2IRAW Prescaler control TMRx_CH2 CxDT C1OUT TMRx_CH1 Input filter (OUTPUT) -
Page 222: Counting Mode
AT32F425 Series Reference Manual Figure 14-45 Counting in external clock mode A TMR_CLK C2IRAW CNT_CLK COUNTER STIS[2:0] C2IF[2:0] OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer. Set the STIS[2: 0] bit to select internal trigger signal to enable counting. -
Page 223: Tmr Input Function
AT32F425 Series Reference Manual Upcounting mode In upcounting mode, the counter counts from 0 to the value programmed in the TMR15_PR register, restarts from 0, and generates a counter overflow event, with the OVFIF bit being set. If the overflow event is disabled, the register is no longer reloaded with the preload and re-loaded value after counter overflow occurs, otherwise, the prescaler and re-loaded value will be updated at an overflow event. -
Page 224: Tmr Output Function
AT32F425 Series Reference Manual Input/output channel 1 main circuit Figure 14-50 TMR1_SWEVT Comparator Counter CVAL=C1DT C1SWTR CVAL>CIDT Output compare IC1PS mode Capture C1EN From time base unit Input Capture/compare mode C1OBEN Channel shadow register seletion C1OBEN TMR1_CM1 Capture/compare capture_transfer capture_transfer... -
Page 225: Figure 14-53 Channel 2 Output Stage
AT32F425 Series Reference Manual Figure 14-53 Channel 2 output stage CVAL = C2DT Output C2ORAW mode Polarity Output controller CVAL>C2DT selection enable C2OUT circuit To the master mode controller Output mode Write CxC[2: 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this... -
Page 226: Figure 14-54 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F425 Series Reference Manual Figure 14-54 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW Figure 14-55 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0]... -
Page 227: Tmr Break Function
AT32F425 Series Reference Manual If the delay is greater than the width of the active output, and if C1OUT and C1COUT are to generate corresponding pulses, the dead-time should be less than the width of the active output. Figure 14-57 gives an example of dead-time insertion when CxP=0, CxCP=0, OEN=1, CxEN=1 and CxCEN=1. -
Page 228: Tmr Synchronization
AT32F425 Series Reference Manual Figure 14-58 Example of TMR break function AOEN CxORAW CxEN CxCEN CxIOS CxCIOS CxOUT Delay CxCOUT Delay Delay 14.4.3.6 TMR synchronization The timers are linked together internnaly for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit;... -
Page 229: Debug Mode
AT32F425 Series Reference Manual Figure 14-60 Example of suspend mode TMR_CLK CI1F1 TMR_EN CNT_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] Slave mode: Trigger mode The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1) Figure 14-61... -
Page 230: Tmr15 Control Register1 (Tmr15_Ctrl1)
AT32F425 Series Reference Manual TMR15_DIV 0x28 0x0000 TMR15_PR 0x2C 0x0000 TMR15_RPR 0x30 0x0000 TMR15_C1DT 0x34 0x0000 TMR15_C2DT 0x38 0x0000 TMR15_BRK 0x44 0x0000 TMR15_DMACTRL 0x48 0x0000 TMR15_DMADT 0x4C 0x0000 14.4.4.1 TMR15 control register1 (TMR15_CTRL1) Register Reset value Type Description Bit 15: 10... -
Page 231: Tmr15 Slave Timer Control Register (Tmr15_Stctrl)
AT32F425 Series Reference Manual 100: C1ORAW signal 101: C2ORAW signal 110: C3ORAW signal 111: C4ORAW signal DMA request source Bit 3 0: Capture/compare event 1: Overflow event Channel control bit flash selection This only acts channels that have complementaryoutput. If the channel contro bits are... -
Page 232: Tmr15 Interrupt Status Register (Tmr15_Ists)
AT32F425 Series Reference Manual HALL DMA request enable Bit 13 HALLDE 0: Disabled 1: Enabled Reserved resd Kept at its default value. Bit 12: 11 Channel 2 DMA request enable Bit 10 C2DEN 0: Disabled 1: Enabled Channel 1 DMA request enable... -
Page 233: Tmr15 Software Event Register (Tmr15_Swevt)
AT32F425 Series Reference Manual Bit 4: 3 Reserved resd Kept at its default value. Channel 2 interrupt flag Bit 2 C2IF rw0c Please refer to C1IF description. Channel 1 interrupt flag If the channel 1 is configured as input mode: This bit is set by hardware on a capture event. - Page 234 AT32F425 Series Reference Manual Output compare mode: Register Reset value Type Description Bit 15 C2OSEN Channel 2 output switch enable Bit 14: 12 C2OCTRL Channel 2 output control Bit 11 C2OBEN Channel 2 output buffer enable Bit 10 C2OIEN Channel 2 output enable immediately...
-
Page 235: Tmr15 Channel Control Register (Tmr15_Cctrl)
AT32F425 Series Reference Manual This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C1EN=’0’: 00: Output 01: Input, C1IN is mapped on C1IRAW 10: Input, C1IN is mapped on C2IRAW 11: Input, C1IN is mapped on STCI. -
Page 236: Table 14-11 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function
AT32F425 Series Reference Manual Pleaser refer to C1P description. Channel 2 enable Bit 4 C2EN Pleaser refer to C1EN description. Channel 1 complementary polarity Bit 3 C1CP 0: C1COUT is active high. 1: C1COUT is active low. Channel 1 complementary enable... -
Page 237: Tmr15 Counter Value (Tmr15_Cval)
AT32F425 Series Reference Manual CxCOUT=CxCP, CxCEN=0; If the clock is present: after a dead-time, CxOUT=CxIOS，CxCOUT=CxCIOS, assuming that CxIOS and CxCIOS do not correspond to CxOUT and CxCOUT active level. Off-state (Output enabled with inactive level) Asynchronously: CxOUT =CxP, Cx_EN=1, CxCOUT=CxCP, CxCEN=1;... -
Page 238: Tmr15 Break Register (Tmr15_Brk)
AT32F425 Series Reference Manual When the channel 2 is configured as output mode: C2DT is the value to be compared with the CVAL value. Whether the written value takes effective immediately depends on the C2OBEN bit, and the corresponding output is generated on C2OUT as configured. -
Page 239: Tmr15 Dma Control Register (Tmr15_Dmactrl)
AT32F425 Series Reference Manual 01: Write protection level 3, and the following bits are write protected: TMRx_BRK: DTC, BRKEN, BRKV and AOEN TMRx_CTRL2: CxIOS and CxCIOS 10: Write protection level 2. The following bits and all bits in leve 3 are write protected:... -
Page 240: Tmr16 And Tmr17 Main Features
AT32F425 Series Reference Manual 14.5.2 TMR16 and TMR17 main features The main functions of general-purpose TMR16 and TMR17 include: Souce of counter clock: internal clock, external clock an internal trigger input 16-bit upcounter and 8-bit repetition counter ... -
Page 241: Tmr Input Function
AT32F425 Series Reference Manual Figure 14-64 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-65 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Repetition counter mode: The repletion counter mode is enabled when the repetition counter value is not equal to 0. In this mode, the repetition counter is decremented at each counter overflow. -
Page 242: Tmr Output Function
AT32F425 Series Reference Manual Channel 1 input stage Figure 14-68 Filter Downcounter C1IRAW Capture/ Polarity C1IPS C1IFP1 compare C1IN divider selection select C1IF_rising Edge detector C1IF_falling Input mode In input mode, the TMRx_CxDT registers latch the current counter values after the selected triggle signal is detected, and the capture compare interrupt flag bit (CxIF) is set. -
Page 243: Figure 14-70 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F425 Series Reference Manual Output compare mode: Set CxOCTRL=2’b001/010/011 to enable output compare mode. In this case, when the counter value matches the value of the CxDT register, the CxORAW is forced high, low or toggling. One-pulse mode: This is a particular case of PWM mode. Set OCMEN=1 to enable one-pulse mode. -
Page 244: Tmr Break Function
AT32F425 Series Reference Manual Figure 14-72 One-pulse mode Dead-time insertion The channel 1 of the TMR16 and TMR17 timers contains a set of reverse channel output. This function is enabled by the CxCEN bit and its polarity is defined by CxCP. Refer to Table 14-17 for more information about the output state of CxOUT and CxCOUT. -
Page 245: Debug Mode
AT32F425 Series Reference Manual CxCIOS bits are used to program the level after dead-time. Even in this case, the CxIOS and CxCIOS cannot be driven to their actival level a the same time. It should be note that because of synchronization on OEN, the dead-time duration is usually longer than usual (around 2 clk_tmr clock cycles) ―... -
Page 246: Tmr16 And Tmr17 Control Register1 (Tmrx_Ctrl1)
AT32F425 Series Reference Manual TMRx_C1DT 0x34 0x0000 TMRx_BRK 0x44 0x0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000 14.5.4.1 TMR16 and TMR17 control register1 (TMRx_CTRL1) Register Reset value Type Description Bit 15: 10 Reserved 0x00 resd Kept at its default value. Clock division... -
Page 247: Tmr16 And Tmr17 Dma/Interrupt Enable Register (Tmrx_Iden)
AT32F425 Series Reference Manual 0: CxEN, CxCEN and CxOCTRL bits are not buffered. 1: CxEN, CxCEN and CxOCTRL bits are not buffered. 14.5.4.3 TMR16 and TMR17 DMA/interrupt enable register (TMRx_IDEN) Register Reset value Type Description Kept at its default value. -
Page 248: Tmr16 And Tmr17 Software Event Register (Tmrx_Swevt)
AT32F425 Series Reference Manual Overflow interrupt flag This bit is set by hardware on an overflow event. It is cleared by software. 0: No overflow event occurs 1: Overflow event is generated. If OVFEN=0 and OVFS=0 Bit 0 OVFIF rw0c in the TMRx_CTRL1 register: −... - Page 249 AT32F425 Series Reference Manual － OWCDIR=1, C1ORAW is low once TMRx_ C1DT <TMRx_CVAL, else high; 111: PWM mode B － OWCDIR=0, C1ORAW is low once TMRx_ C1DT >TMRx_CVAL, else high; － OWCDIR=1, C1ORAW is high once TMRx_ C1DT <TMRx_CVAL, else low.
-
Page 250: Tmr16 And Tmr17 Channel Control Register (Tmrx_Cctrl)
AT32F425 Series Reference Manual 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’... -
Page 251: Tmr16 And Tmr17 Counter Value (Tmrx_Cval)
AT32F425 Series Reference Manual Off-state CxORAW + polarity, (Output enabled with CxCOUT= CxORAW xor inactive level) CxCP, CxCEN=1 CxOUT=CxP, Cx_EN=1 Off-state CxORAW + polarity, (Output enabled with CxOUT= CxORAW xor CxP, inactive level) Cx_EN=1 CxCOUT=CxCP, CxCEN=1 CxORAW CxORAW+ polarity+dead- inverted+polarity+dead-... -
Page 252: Tmr16 And Tmr17 Break Register (Tmrx_Brk)
AT32F425 Series Reference Manual When the channel 1 is configured as input mode: The C1DT is the CVAL value stored by the last channel 1 input event (C1IN) When the channel 1 is configured as output mode: C1DT is the value to be compared with the CVAL value. -
Page 253: Tmr16 And Tmr17 Dma Control Register (Tmrx_Dmactrl)
AT32F425 Series Reference Manual his field is used to enable write protection. 00: Write protection is OFF. 01: Write protection level 3, and the following bits are write protected: TMRx_BRK: DTC, BRKEN, BRKV and AOEN TMRx_CTRL2: CxIOS and CxCIOS 10: Write protection level 2. The following bits and all bits... -
Page 254: Tmr1 Main Features
AT32F425 Series Reference Manual 14.6.2 TMR1 main features Souce of counter clock: internal clock, external clock an internal trigger input 16-bit up, down, up/down, repetition and encoder mode counter Five independent channels for input capture, output compare, PWM generation, one-pulse mode output and embedded dead-time ... -
Page 255: Figure 14-77 Block Diagram Of External Clock Mode A
AT32F425 Series Reference Manual External clock (TRGIN/EXT) The counter clock can be provided by two external clock sources, namely, TRGIN and EXT signals. When SMSEL=3’111, external clock mode A is selected. Set the STIS[2: 0] bit to select TRGIN signal to drive the counter to start counting. -
Page 256: Counting Mode
AT32F425 Series Reference Manual Figure 14-80 Counting in external clock mode B TMR_CLK CNT_CLK COUNTER ESDIV[1:0] ESF[3:0] 0000 OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer. Set the STIS[2: 0] bit to select internal trigger signal to enable counting. -
Page 257: Figure 14-82 Overflow Event When Prben=0
AT32F425 Series Reference Manual restarts from 0, and generates a counter overflow event, with the OVFIF bit being set. If the overflow event is disabled, the register is no longer reloaded with the preload and re-loaded value after counter overflow occurs, otherwise, the prescaler and re-loaded value will be updated at an overflow event. -
Page 258: Figure 14-85 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32
AT32F425 Series Reference Manual Figure 14-85 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32 TMR_CLK COUNTER PR[15:0] DIV[15:0] TWCMSEL [1：0] OVFIF Clear Clear Clear Repetition counter mode: The repletion counter mode is enabled when the repetition counter value is not equal to 0. In this mode, the repetition counter is decremented at each counter overflow. -
Page 259: Tmr Input Function
AT32F425 Series Reference Manual 14.6.3.3 TMR input function The TMR1 has four independent channels. Each channel can be configured as input or output. As input, the channel can be used for the filtering, selection, division and input capture of the input signals. -
Page 260: Tmr Output Function
AT32F425 Series Reference Manual 14.6.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. The advanced-control timer output function varies from one channel to one channel. -
Page 261: Figure 14-92 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F425 Series Reference Manual gives an example of the combination between upcounting mode and PWM mode A. The Figure 14-93 output signal behaves when PR=0x32 but CxDT is configured with a different value. gives an example of the combination between up/down counting mode and PWM mode Figure 14-94 A. -
Page 262: Figure 14-95 One-Pulse Mode
AT32F425 Series Reference Manual Figure 14-95 One-pulse mode CxORAW clear When the CxOSEN bit is set, the CxORAW signal for a given channel is cleared by applying a high level to the EXT input. The CxORAW signal remains unchanged until the next overflow event. -
Page 263: Tmr Break Function
AT32F425 Series Reference Manual 14.6.3.5 TMR break function When the break function is enabled (BRKEN=1), the CxOUT 和 CxCOUT are jointly controlled by OEN, FCSODIS, FCSOEN, CxIOS and CxCIOS. But, CxOUT and CxCOUT cannot be set both to active level at the same time. -
Page 264: Debug Mode
AT32F425 Series Reference Manual Figure 14-99 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] CI1F1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low. -
Page 265: Tmr1 Registers
AT32F425 Series Reference Manual 14.6.4 TMR1 registers These peripheral registers must be accessed by word (32 bits). TMR1 and TMR8 register are mapped into a 16-bit addressable space. Table 14-16 TMR1 register map and reset value Register Offset Reset value... -
Page 266: Tmr1 Control Register2 (Tmr1_Ctrl2)
AT32F425 Series Reference Manual 11: Two-way counting mode3, count up and down alternately, the output flag bit is set when the counter counts up / down One-way count direction Bit 4 OWCDIR 0: Up； 1: Down One cycle mode enable... -
Page 267: Tmr1 Slave Timer Control Register (Tmr1_Stctrl)
AT32F425 Series Reference Manual This only acts channels that have complementaryoutput. If the channel contro bits are buffered: 0: Control bits are updated by setting the HALL bit 1: Control bits are updated by setting the HALL bit or a rising edge on TRGIN. -
Page 268: Tmr1 Dma/Interrupt Enable Register (Tmr1_Iden)
AT32F425 Series Reference Manual Pleaser refer to Table 14-3 and 14-5 for more information on ISx for each timer. Bit 3 Reserved resd Kept at its default value. Subordinate TMR mode selection 000: Slave mode is disabled 001: Encoder mode A... -
Page 269: Tmr1 Interrupt Status Register (Tmr1_Ists)
AT32F425 Series Reference Manual 1: Enabled Overflow interrupt enable Bit 0 OVFIEN 0: Disabled 1: Enabled 14.6.4.5 TMR1 interrupt status register (TMR1_ISTS) Register Reset value Type Description Bit 15: 13 Reserved resd Kept at its default value. Channel 4 recapture flag... -
Page 270: Tmr1 Software Event Register (Tmr1_Swevt)
AT32F425 Series Reference Manual − An overflow event is generated when the counter CVAL is reinitialized by a trigger event. 14.6.4.6 TMR1 software event register (TMR1_SWEVT) Register Reset value Type Description Bit 15: 8 Reserved 0x000 resd Kept at its default value. - Page 271 AT32F425 Series Reference Manual Channel 1 output switch enable 0: C1ORAW is not affected by EXT input. Bit 7 C1OSEN 1: Once a high level is detect on EXT input, clear C1ORAW. Channel 1 output control This field defines the behavior of the original signal C1ORAW.
-
Page 272: Tmr1 Channel Mode Register2 (Tmr1_Cm2)
AT32F425 Series Reference Manual 10: Input, C2IN is mapped on C1IRAW 11: Input, C2IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS. Channel 1 digital filter This field defines the digital filter of the channel 1. N stands for the number of filtering, indicating that the input edge can pass the filter only after N sampling events. -
Page 273: Tmr1 Channel Control Register (Tmr1_Cctrl)
AT32F425 Series Reference Manual Bit 7 C3OSEN Channel 3 output switch enable Bit 6: 4 C3OCTRL Channel 3 output control Bit 3 C3OBEN Channel 3 output buffer enable Bit 2 C3OIEN Channel 3 output enable immediately Channel 3 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’:... -
Page 274: Table 14-17 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function
AT32F425 Series Reference Manual 0: C1COUT is active high. 1: C1COUT is active low. Channel 1 complementary enable Bit 2 C1CEN 0: Output is disabled. 1: Output is enabled. Channel 1 polarity When the channel 1 is configured as output mode:... -
Page 275: Tmr1 Counter Value (Tmr1_Cval)
AT32F425 Series Reference Manual Off-state (Output enabled with inactive level) Asynchronously: CxOUT =CxP, Cx_EN=1, CxCOUT=CxCP, CxCEN=1; If the clock is present: after a dead-time, CxOUT=CxIOS，CxCOUT=CxCIOS, assuming that CxIOS and CxCIOS do not correspond to CxOUT and CxCOUT active level. Note: If the two outputs of a channel are not used (CxEN = CxCEN = 0), CxIOS, CxCIOS, CxP and CxCP must be cleared. -
Page 276: Tmr1 Channel 3 Data Register (Tmr1_C3Dt)
AT32F425 Series Reference Manual 14.6.4.16 TMR1 channel 3 data register (TMR1_C3DT) Register Reset value Type Description Channel 3 data register When the channel 3 is configured as input mode: The C3DT is the CVAL value stored by the last channel... -
Page 277: Tmr1 Dma Control Register (Tmr1_Dmactrl)
AT32F425 Series Reference Manual 0: Break input is disabled. 1: Break input is enabled. Frozen channel status when holistic output enable This bit acts on the channels that have complementary output. It is used to set the channel state when the timer... -
Page 278: Tmr1 Dma Data Register (Tmr1_Dmadt)
AT32F425 Series Reference Manual 14.6.4.20 TMR1 DMA data register (TMR1_DMADT) Register Reset value Type Description DMA data register A write/read operation to the DMADT register accesses Bit 15: 0 DMADT 0x0000 any TMR register located at the following address: TMRx peripheral address + ADDR*4 to TMRx peripheral address + ADDR*4 + DTB*4 14.6.4.21... -
Page 279: Window Watchdog Timer (Wwdt)
AT32F425 Series Reference Manual 15 Window watchdog timer (WWDT) 15.1 WWDT introduction The window watchdog downcounter must be reloaded in a limited time window to prevent the watchdog circuits from generating a system reset. The window watch dog is used to detect the occurrence of system malfunctions. -
Page 280: Debug Mode
AT32F425 Series Reference Manual Table 15-1 Minimum and maximum timeout value when PCLK1=72 MHz Prescaler Min. Timeout value Max. Timeout value 56.5μs 3.64ms 113.5μs 7.28ms 227.5μs 14.56ms 455μs 29.12ms Figure 15-2 Window watchdog timing diagram 15.4 Debug mode When the microcontroller enters debug mode (Cortex -M4 core halted), the WWDT counter stops counting by setting the WWDT_PAUSE in the DEBUG module. -
Page 281: Status Register (Wwdt_Sts)
AT32F425 Series Reference Manual 10: PCLK1 divided by 16384 11: PCLK1 divided by 32768 Window value if the counter is reloaded while its value is greater than the Bit 6: 0 0x7F window register value, a reset is generated. The counter must be reloaded between 0x40 and WIN[6: 0]. -
Page 282: Watchdog Timer (Wdt)
AT32F425 Series Reference Manual 16 Watchdog timer (WDT) 16.1 WDT introduction The WDT is driven by a dedicated low-speed clock (LICK). Due to the lower clock accuracy of LICK, the WDT is best suited to the applications that have lower timing accuracy and can run independently outside the main application. -
Page 283: Debug Mode
AT32F425 Series Reference Manual Figure 16-1 WDT block diagram power domain 1.2 V power domain Prescaler register 8-bit SYNC WDT_DIV prescaler Reload register 12-bit reload 12-bit SYNC WDT_RLD value downcounter Compare CNT=0 reset Windows register 12-bit windows SYNC WDT_WIN value reset reload at CNT>WIN... -
Page 284: Command Register (Wdt_Cmd)
AT32F425 Series Reference Manual 16.5.1 Command register (WDT_CMD) (Reset in Standby mode) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. Command register 0xAAAA: Reload counter Bit 15: 0 0x0000 0x5555: Unlock write-protected WDT_DIV and WDT_RLD 0xCCCC: Enable WDT. -
Page 285: Enhanced Real-Time Clock (Ertc)
AT32F425 Series Reference Manual 17 Enhanced real-time clock (ERTC) 17.1 ERTC introduction The real-time clock provides a calendar clock function. The time and date can be modified by modifying the ERTC_TIME and ERTC_DATE register. The RTC module is in battery powered domain, which means that it keeps running and free from the influence of system reset and VDD power off as long as VBAT is powered. -
Page 286: Ertc Initialization
AT32F425 Series Reference Manual The ck_a is used for subseond update, while the ck_b is usd for calendar update and periodic autowakeup. The clock frequencys of ck_a and ck_b can be obtained from thef following equation: ck_a ck_b To obtain ck_b with frequency of 1 Hz, DIVA=127, DIVB=255, and 32.768 kH LEXT should be used. This ck_b is then used for calendar update. - Page 287 AT32F425 Series Reference Manual Clock and calendar initialization After the register write protection is unlocked, follow the procedure below for clock and calendar initialization: 1. Set the IMEN bit to enter initialization mode 2. Wait until the initialization flag INITF bit is set 3.
-
Page 288: Periodic Automatic Wakeup
AT32F425 Series Reference Manual 1. Disable alarm clock A or alarm clock B (by setting ALAEN=0 or ALBEN=0) 2. Wait until the ALAWF or ALBWF bit is set to enable write access to the alarm clock A or B 3. Configure alarm clock A or B registers (ERTC_ALA/ERTC_ALASBS and ERTC_ALB/ERTC_ALBSBS) 4. -
Page 289: Time Stamp Function
AT32F425 Series Reference Manual 17.3.5 Time stamp function When time stamp event is detected on the tamper pin (valid edge is detected), the current calendar value will be stored to the time stamp register. When a time stamp event occurs, the time stamp flag bit (TSF) in the ERTC_STS register will be set. If a new time stamp event is detected when time stamp flag (TSF) is already set, then the time stamp overflow flag (TSOF) will be set, but the time stamp registers will remain the result of the last event. -
Page 290: Multiplexed Function Output
AT32F425 Series Reference Manual 17.3.7 Multiplexed function output ERTC provides a set of multiplexed function output for the following events: Clocks calibrated (OUTSEL=0 and CALOEN=1) Output 512Hz (CALOSEL=0) Output 1Hz (CALOSEL=1) Alarm clock A (OUTSEL=1) Wakeup events (OUTSEL=3) When alarm clock or wakeup events are selected (OUTSEL≠0), it is possible to select output type (open-... -
Page 291: Ertc Registers
AT32F425 Series Reference Manual 17.4 ERTC registers These peripheral registers must be accessed by words (32 bits). ERTC registers are 16-bit addressable registers. Table 17-4 ERTC register map and reset values Register name Offset Reset value ERTC_TIME 0x00 0x0000 0000... -
Page 292: Ertc Control Register (Ertc_Ctrl)
AT32F425 Series Reference Manual 0: Forbidden 1: Monday 2: Tuesday 3: Wednesday 4: Thursday 5: Friday 6: Saturday 7: Sunday Bit 12 Month tens Bit 11: 8 Month units Bit 7: 6 Reserved resd Kept at its default value. Bit 5: 4... -
Page 293: Ertc Initialization And Status Register (Ertc_Sts)
AT32F425 Series Reference Manual 1: Wakeup timer enabled Bit 9 Reserved resd Kept at its default value. Alarm A enable Bit 8 ALAEN 0: Alarm A disabled 1: Alarm A enabled Bit 7 Reserved resd Kept at its default value. -
Page 294: Ertc Divider Register (Ertc_Div)
AT32F425 Series Reference Manual 1: Wakeup timer event occurs Note: The clearing operation of this bit takes effect after two APB_CLK cycles. Bit 9 Reserved resd Kept at its default value. Alarm clock A flag 0: No alarm clock event... -
Page 295: Ertc Wakeup Timer Register (Ertc_Wat)
AT32F425 Series Reference Manual 17.4.6 ERTC wakeup timer register (ERTC_WAT) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. Bit 15: 0 VAL 0xFFFF Wakeup timer reload value 17.4.7 ERTC alarm clock A register (ERTC_ALA) -
Page 296: Ertc Time Stamp Time Register (Ertc_Tstm)
AT32F425 Series Reference Manual This bit can be written only when TADJF=0. It is intended to be used with DECSBS in order to fine-tune the time. Bit 30: 15 Reserved 0x0000 resd Kept at its default value DECSBS[14: 0]: Decrease sub-second value... -
Page 297: Ertc Tamper Configuration Register (Ertc_Tamp)
AT32F425 Series Reference Manual 16 second calibration period Bit 13 CAL16 0: No effect 1: 16-second calibration Bit 12: 9 Reserved resd Kept at its default value Decrease ERTC clock DEC out of ERTC_CLK cycles are masked during the 220... -
Page 298: Ertc Alarm Clock A Subsecond Register (Ertc_Alasbs)
AT32F425 Series Reference Manual 1: High Tamper detection 1 enable Bit 0 TP1EN 0: Tamper detection 1 disabled 1: Tamper detection 1 enabled 17.4.16 ERTC alarm clock A subsecond register (ERTC_ ALASBS) Register Reset value Type Description Bit 31: 28 Reserved... -
Page 299: Analog-To-Digital Converter (Adc)
AT32F425 Series Reference Manual 18 Analog-to-digital converter (ADC) 18.1 ADC introduction The ADC is a peripheral that converts an analog input signal into a 12-bit digital signal. Its sampling rate is as high as 2 MSPS. It has up to 18 channels for sampling and conversion. -
Page 300: Adc Functional Overview
AT32F425 Series Reference Manual Figure 18-1 ADC1 block diagram ADCDIV OCTESEL ADC prescaler PCLK2 ADCCLK TMR1_TRGOUT TMR1_CH4 TMR2_TRGOUT OCTEN TMR3_TRGOUT TMR15_TRGOUT TMR1_CH1 EXINT11 ADC_IN0 OCSWTRG Trigger ADC_IN1 detection GPIO Ordinary ADC_IN15 conversion start INTRV Channel manegement Ordinary Analog-to- channels V DDA... -
Page 301: Internal Reference Voltage
AT32F425 Series Reference Manual If the preempted channel trigger occurs during the ordinary channel conversion, then the ordinary channel conversion is interrupted, giving the priority to the preempted channel, and the ordinary channel continues its conversion at the end of the preempted channel conversion. If the ordinary channel trigger occurs during the preempted channel conversion, the ordinary channel conversion won’t start until the... -
Page 302: Trigger
AT32F425 Series Reference Manual value will not set the OCCE flag, or generate interrupts or DMA requests. Figure 18-3 ADC power-on and calibration The ADCEN The ADCAL bit is set by bit is set by software. software. ADCCLK ADCEN STAB... -
Page 303: Conversion Sequence Management
AT32F425 Series Reference Manual 18.4.3 Conversion sequence management Only one channel is converted at each trigger event by default, that is, OSN1-defined channel or PSN4- defined channel. The detailed conversion sequence modes are described in the following sections. With this, the channels can be converted in a specific order. -
Page 304: Repetition Mode
AT32F425 Series Reference Manual 18.4.3.3 Repetition mode The repetition mode is enabled by setting the RPEN bit in the ADC_CTRL2 register. When a trigger signal is detected, the ordinary channels will be converted repeatedly. This mode can work with the ordinary channel conversion in the sequence mode to enable the repeated conversion of the ordinary group. -
Page 305: Oversampling Of Ordinary Group Of Channels
AT32F425 Series Reference Manual Oversampling shift is selected through the OSSSEL bit in the ADC_OVSP register, which is performed by right shift If the averaged data is greater than 16 bits, then only pick up the right-aligned 16-bit data and put them... -
Page 306: Oversampling Of Preempted Group Of Channels
AT32F425 Series Reference Manual Figure 18-8 Ordinary oversampling restart mode selection Sampling OCLEN=0, OSN1=ADC_IN0 Conversion PCLEN=1, PSN3=ADC_IN4, PSN4=ADC_IN5 Continue mode：OOSEN = 1, POSEN = 0, = 0, OOSRSEL OOSTREN Ordinary Preempted trigger trigger ADC_IN0 ADC_IN0 ADC_IN0 ADC_IN0 ADC_IN0 Ordinary Oversampling... -
Page 307: Data Management
AT32F425 Series Reference Manual Figure 18-10 Oversampling of preempted group of channels Sampling OCLEN=0, OSN1=ADC_IN0 PCLEN=1, PSN3=ADC_IN4, PSN4=ADC_IN5 Conversion OOSEN = 1, POSEN = 1, OOSRSEL = 0, OOSTREN = 0, PCAUTOEN = 1, SQEN = 1 Ordinary trigger ADC_IN0... -
Page 308: Status Flag And Interrupts
AT32F425 Series Reference Manual 18.4.7 Status flag and interrupts Each of the ADCs has its dedicated ADCx_STS reisters, that is, OCCS (ordinary channel conversion start flag), PCCS (preempted channel conversion start flag), PCCE (preempted channel conversion end flag), OCCE (ordinary channel conversion end flag) and VMOR (voltage monitor out of range). -
Page 309: Adc Control Register1 (Adc_Ctrl1)
AT32F425 Series Reference Manual Preempted channel conversion start flag This bit is set by hardware and cleared by software (writing Bit 3 PCCS rw0c 0: No preempted channel conversion started 1: Preempted channel conversion has started Preempted channel end of conversion flag... -
Page 310: Adc Control Register2 (Adc_Ctrl2)
AT32F425 Series Reference Manual Sequence mode enable 0: Sequence mode disabled (a single channel is converted) 1: Sequence mode enabled (the selected multiple Bit 8 SQEN channels are converted) Note: If this mode is enabled and the CCEIEN/PCCEIEN is set, a CCE or PCCE interrupt is generated only at the end of conversion of the last channel. - Page 311 AT32F425 Series Reference Manual 111: OCSWTRG Kept at its default value Bit 16 Reserved resd Trigger mode enable for preempted channels conversion 0: Disabled Bit 15 PCTEN 1: Enabled Trigger event select for preempted channel conversion 000: TMR1 CH2 event...
-
Page 312: Adc Sampling Time Register 1 (Adc_Spt1)
AT32F425 Series Reference Manual 18.5.4 ADC sampling time register 1 (ADC_SPT1) Accessed by words. Register Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value. Sample time selection of channel ADC_IN17 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles... -
Page 313: Adc Sampling Time Register 2 (Adc_Spt2)
AT32F425 Series Reference Manual 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN11 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 5: 3 CSPT11 100: 41.5 cycles... - Page 314 AT32F425 Series Reference Manual 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN6 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 20: 18 CSPT6 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles...
-
Page 315: Adc Preempted Channel Data Offset Register
AT32F425 Series Reference Manual 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN0 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 2: 0 CSPT0 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles... -
Page 316: Adc Ordinary Sequence Register 2 (Adc_ Osq2)
AT32F425 Series Reference Manual Number of 13th conversion in ordinary sequence Note: The number can be from 0 to 17. For example, if the Bit 4: 0 OSN13 0x00 number is set to 3, it means that the 13 conversion is ADC_IN3 channel. -
Page 317: Adc Preempted Data Register X (Adc_ Pdtx) (X=1
AT32F425 Series Reference Manual conversion follows the sequence : 4, 5, 6, not 3, 4,5. 18.5.13 ADC preempted data register x ( ADC_ PDTx) (x=1..4) Accessed by words. Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value... -
Page 318: Adc Oversampling Register (Adc_ Ovsp)
AT32F425 Series Reference Manual 18.5.15 ADC oversampling register (ADC_ OVSP) Accessed by words. Register Reset value Type Description Bit 31: 11 Reserved 0x0000 resd Kept at its default value. Ordinary oversampling restart mode select When the ordinary oversampling is interrupted by preempte conversions, this bit can be used to select where to resume ordinary conversions. -
Page 319: Controller Area Network (Can)
AT32F425 Series Reference Manual 19 Controller area network (CAN) 19.1 CAN introduction CAN (Controller Area Network) is a distributed serial communication protocol for real-time and reliable data communication among various nodes. It supports the CAN protocol version 2.0A and 2.0B. - Page 320 AT32F425 Series Reference Manual Baud rate formula: ���������������� = Nomal Bit Timimg ���������� ������ ������������ = t ��������_������ ��������1 ��������2 where = 1 x t ��������_������ �� = (1 + BTS1[3: 0]) x t ��������1 �� = (1 + BTS2[2: 0]) x t ��������2...
-
Page 321: Figure 19-2 Transmit Interrupt Generation
AT32F425 Series Reference Manual Figure 19-2 Transmit interrupt generation Inter-frame Inter-frame space or Data frame (standard identifier) space overload frame 44 + 8* N Ack field Data field Arbitration field Control field CRC field 8* N Inter-frame Inter-frame space or... -
Page 322: Interrupt Management
AT32F425 Series Reference Manual 19.4 Interrupt management The CAN controller contains four interrupt vectors that can be used to enable or disable interrups by setting the CAN_INTEN register. Figure 19-3 Transmit interrupt generation Figure 19-4 Receive interrupt 0 generation RF0MN != 00... -
Page 323: Functional Overview
AT32F425 Series Reference Manual depending on the CANx_PAUSE bit in the DEBUG_CTRL register or the PTD bit in the CAN_MCTRL register. Time triggered communication The timer triggered communication is used to improve the real-time performance so as to avoid bus competition. -
Page 324: Test Modes
AT32F425 Series Reference Manual Exit Sleep mode in two ways: The CAN controller can be woke up by hardware clearing the DZEN bit when the AEDEN bit in the CAN_MCTRL register and the CAN bus activity is detected. It can also be woke up by software clearing the DZEN bit. -
Page 325: Figure 19-8 32-Bit Identifier Mask Mode
AT32F425 Series Reference Manual 32-bit fliter register CAN_FiFBx includes the SID[10: 0], EID[17: 0], IDT and RTR bits. CAN_FiFB1[31: 21] CAN_FiFB1[20: 3] CAN_FiFB1[2: 0] CAN_FiFB2[31: 21] CAN_FiFB2[20: 3] CAN_FiFB2[2: 0] SID[10: 0]/EID[28: 18] EID[17: 0] Two 16-bit filter register CAN_FiFBx includes SID[10: 0], IDT, RTR and EID[17: 15] bits... - Page 326 AT32F425 Series Reference Manual Filter match number 14 filter banks have different filtering effects dependent on the bit width mode. For example, 32-bit identifier mask mode contains the filters numbered n while 16-bit identifier list mode contains the filters numbered n, n+1, n+2 and n+3. When a frame of message passes through the filter number N, the number N is stored in the RFFMN[7: 0] bit in the CAN_RFCx register.
-
Page 327: Message Transmission
AT32F425 Series Reference Manual The filter x is associated with FIFO0 or FIFO1 by setting the FRFSELx bit in the CAN_FRF register. The filter banks x are activated by setting FAENx=1 in the CAN_FACFG register. Configure 0~27 filter banks by writing to the CAN_FiFBx register (i=0…27; x=1,2). -
Page 328: Message Reception
AT32F425 Series Reference Manual TMxTSF =1. TMxALF bit: Transmission arbitration lost flag, indicating that the data transmission arbitration is lost when TMxALF=1. TMxTEF bit: Transmission error flag, indicating that the data transmission failed due to bus error, and an error frame is sent when TMxTEF=1. -
Page 329: Error Management
AT32F425 Series Reference Manual 19.6.7 Error management The status of CAN nodes is indicated by the receive error counter (TEC) and transmit error counter (REC) bits in the CAN_ESTS register. In the meantime, the ETR[6: 4] bit in the CAN_ESTS register is used to record the last error source, and the corresponding interrupts will be generated when the CAN_INTEN register is enabled. -
Page 330: Can Control And Status Registers
AT32F425 Series Reference Manual RFDTH0 1BCh 0xXXXX XXXX RFI1 1C0h 0xXXXX XXXX RFC1 1C4h 0xXXXX XXXX RFDTL1 1C8h 0xXXXX XXXX RFDTH1 1CCh 0xXXXX XXXX Reserved 1D0h~1FFh FCTRL 200h 0x2A1C 0E01 FMCFG 204h 0x0000 0000 Reserved 208h FSCFG 20Ch 0x0000 0000... -
Page 331: Can Master Status Register (Can_Msts)
AT32F425 Series Reference Manual hardware will automatically leave bus-off mode as soon as an exit timing is detected on the CAN bus. When Automatic exit bus-off mode is disabled, the software must enter/leave the freeze mode once more, and then the bus-off state is left only when an exit timing is detected on the CAN bus. - Page 332 AT32F425 Series Reference Manual starts, and it is cleared by hardware at the end of reception. Current transmit status 0: No transmit occurs 1: ransmit is in progress Bit 8 CUSS Note: This bit is set by hardware when the CAN transmission starts, and it is cleared by hardware at the end of transmission.
-
Page 333: Can Transmit Status Register (Can_Tsts)
AT32F425 Series Reference Manual 19.7.1.3 CAN transmit status register (CAN_TSTS) Register Reset value Type Description Transmit mailbox 2 lowest priority flag 0: Mailbox 2 is not given the lowest priority. Bit 31 TM2LPF 1: Lowest priority (This indicates that more than one mailboxes are pending for transmission, the mailbox 2 has the lowest priority.) - Page 334 AT32F425 Series Reference Manual 0: Transmission failed 1: Transmission was successful. Note: This bit indicates whether the mailbox 2 transmission is successful or not. It is cleared by software writing 1. Transmit mailbox 2 transmission completed flag 0: Transmission is in progress...
-
Page 335: Can Receive Fifo 0 Register (Can_Rf0)
AT32F425 Series Reference Manual 0: No error 1: Mailbox 0 transmission error Note: This bit is set when the mailbox 0 transmission error occurred. It is cleared by software writing 0 or by hardware at the start of the next transmission... -
Page 336: Can Receive Fifo 1 Register (Can_Rf1)
AT32F425 Series Reference Manual in the FIFO 0. RF0ML bit is incremented by one each time a new message has been received and passed the fitler while the FIFO 0 is not full. RF0ML bit is decremented by one each time the software releases the receive FIFO 0 by writing 1 to the RF0R bit. - Page 337 AT32F425 Series Reference Manual 1: Error interrupt enabled Note:The flag bit of this interrupt is the EOIF bit. An interrupt is generated when both this bit and EOIF bit are set. Bit 14: 12 Reserved resd Kept at its default value.
-
Page 338: Can Error Status Register (Can_Ests)
AT32F425 Series Reference Manual 19.7.1.7 CAN error status register (CAN_ESTS) Register Reset value Type Description Receive error counter This counter is implemented in accordance with the Bit 31: 24 0x00 receive part of the falut confinement mechanism of the CAN protocol. -
Page 339: Can Mailbox Registers
AT32F425 Series Reference Manual Note: This field defines the number of time unit in Bit time segment 2. Bit time segment 1 tBTS1 = tCAN x (BTS1[3: 0] + 1) Bit 19: 16 BTS1 Note: This field defines the number of time unit in Bit time segment 1. -
Page 340: Transmit Mailbox Data Length And Time Stamp Register
AT32F425 Series Reference Manual 19.7.2.2 Transmit mailbox data length and time stamp register (CAN_TMCx) (x=0..2) All the bits in the register are write protected when the mailbox is not in empty state. Register Reset value Type Description Transmit mailbox time stamp... -
Page 341: Receive Fifo Mailbox Data Length And Time Stamp Register
AT32F425 Series Reference Manual 19.7.2.6 Receive FIFO mailbox data length and time stamp register (CAN_RFCx) (x=0..1) Note: All the receive mailbox registers are read only. Register Reset value Type Description Receive FIFO time stamp Bit 31: 16 RFTS 0xXXXX Note: This field contains the value of the CAN timer sampled at the start of a receive frame. -
Page 342: Can Filter Bit Width Configuration Register (Can_ Fbwcfg)
AT32F425 Series Reference Manual 19.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG) Note: This register can be written only when FCS=1 in the CAN_FCTRL register (The filter is in configuration mode) Register Reset value Type Description Bit 31: 14... -
Page 343: Universal Serial Bus Full-Seed Device Interface (Otgfs)
AT32F425 Series Reference Manual 20 Universal serial bus full-seed device interface (OTGFS) The OTGFS software copyright is owned by Synopsys, Inc. All rights reserved. Used with permission. As a full-speed dual-role device, the OTGFS is fully compliant with the Universal Serial Bus Specification Revision2.0. -
Page 344: Otgfs Clock And Pin Configuration
AT32F425 Series Reference Manual The OTGFS supports SOF and OE pulse features: a SOF pulse generates at a SOF packet, the pulse can output to pins and the timer 2; an OE pulse generates when the OTGFS outputs data, the pulse can output to pins. -
Page 345: Otgfs Interrupts
AT32F425 Series Reference Manual 20.4 OTGFS interrupts Figure 20-2 shows the OTGFS interrupt hierarchy. Refer to the OTGFS interrupt register (OTGFS_GINTSTS) and OTGFS interrupt mask register (OTGFS_GINTMSK). Figure 20-2 OTGFS interrupt hierarchy CORE Interrupt Global Interrupt Mask (Bit 0) AHB Configuration... -
Page 346: Otgfs Fifo Configuration
AT32F425 Series Reference Manual 2. Program the following fields in the global AHB configuration register: OTGFS_GINTMSK.RXFLVLMSK = 0x0 3. Program the following fields in the OTGFS_GUSBCFG register: Full-speed timeout standard bit USB turnaround time bit 4. The software must unmask the following bits in the OTGFS_GINTMSK register: ... -
Page 347: Host Mode
AT32F425 Series Reference Manual 3. Device IN endpoint transmit FIFO#1 size register (OTGFS_DIEPTXF1) OTGFS_DIEPTXF1.INEPTXFSTADDR = OTGFS_GNPTXFSIZ.NPTXFSTADDR + tx_fifo_size[0] 4. Device IN endpoint transmit FIFO#2 size register (OTGFS_DIEPTXF2) OTGFS_DIEPTXF2.INEPTXFSTADDR = OTGFS_DIEPTXF1.INEPTXFSTADDR + tx_fifo_size[1] 5. Device IN endpoint transmit FIFO#i size register (OTGFS_DIEPTXFi) ... -
Page 348: Refresh Controller Transmit Fifo
AT32F425 Series Reference Manual OTGFS_GNPTXFSIZ.NPTXFDEP = tx_fifo_size[0]； OTGFS_GNPTXFSIZ. NPTXFSTADDR = rx_fifo_size； 3. OTGFS host periodic transmit FIFO size register (OTGFS_HPTXFSIZ) OTGFS_HPTXFSIZ.PTXFSIZE = tx_fifo_size[1]； OTGFS_HPTXFSIZ.PTXFSTADDR = OTGFS_GNPTXFSIZ.NPTXFSTADDR + tx_fifo_size[0]； 4. After SRAM allocation, refresh transmit FIFO and receive FIFO to ensure normal FIFO running. -
Page 349: Otgfs Channel Initialization
AT32F425 Series Reference Manual 20.5.3.2 OTGFS channel initialization To communicate with the device, the application must enable and initialize at least one channel according to the following steps: 1. Unmask the following interrupts by setting the OTGFS_GINTMSK register: Non-periodic transmit FIFO empty for OUT transfers ... -
Page 350: Figure 20-3 Writing The Transmit Fifo
AT32F425 Series Reference Manual request queue before starting to write to the the transmit FIFO. The application must always write to the transmit FIFO in DWORDs. If the packet size is not aligned with DWORD, the application must use padding. The OTGFS host determines the actual packet size according to the programmed maximum packet size and transfer size. -
Page 351: Special Cases
AT32F425 Series Reference Manual Figure 20-4 Reading the receive FIFO Start RXFLVL interrupt? Unmask RXFLVL Unmask RXFLVL Mask RXFLVL interrupt interrupt interrupt Read the received packet from the Read Receive FIFO GRXSTSP PKTSTS=0x2 ? BCNT > 0? 20.5.3.5 Special cases （1）Handling babble conditions... -
Page 352: Figure 20-5 Hfir Behavior When Hfirrldctrl=0X0
AT32F425 Series Reference Manual Figure 20-5 shows the HFIR behavior when the HFIRRLDCTRL is set to 0x0 in the OTGFS_HFIR register. Figure 20-5 HFIR behavior when HFIRRLDCTRL=0x0 (3)SOF Lost Synchronization Due to HFIR Reload HFIR DN 0 400 399 0 400... -
Page 353: Initialize Bulk And Control In Transfers
AT32F425 Series Reference Manual Figure 20-6 HFIR behavior when HFIRRLDCTRL=0x1 (3)SOF Lost Synchronization NOT Lost Due to HFIR Reload HFIR DN 0 400 399 0 400 ******************** 1 ******************** ******************** Counter Application Load Of HFIR HFIR (6)SOF back in (2)HFIR Reloaded... - Page 354 AT32F425 Series Reference Manual receive FIFO 7. The application must read the receive packet status, and ignore it when the receive packet status is not an IN data packet 8. The controller generats the XFERC interrupt as soon as the receive packet is read 9.
-
Page 355: Initialize Bulk And Control Out/Setup Transfers
AT32F425 Series Reference Manual Mask ACK else if (DATATGLERR) Reset Error Count 20.5.3.8 Initialize bulk and control OUT/SETUP transfers Figure 20-7 shows a typical bulk or control transfer OUT/SETUP transfer operation. Refer to channel 1 (ch_1) for more information. It is necessary to send two bulk transfer OUT packets. The control transfer SETUP operation is the same, just the fact that it has only one packet. -
Page 356: Figure 20-7 Example Of Common Bulk/Control Out/Setup And Bulk/Control In Transfer
AT32F425 Series Reference Manual Figure 20-7 Example of common Bulk/Control OUT/SETUP and Bulk/Control IN transfer Application Host Device init_reg(ch_1) Non-periodic Request init_reg(ch_2) Queue write_tx_fifo Assume that this queue can (ch_1) hold 4 entries. set_ch_en(ch_2) write_tx_fifo (ch_1) ch_1 set_ch_en(ch_2) ch_2 ch_1... -
Page 357: Initialize Interrupt In Transfers
AT32F425 Series Reference Manual Unmask CHHLTD Disable Channel if (XactErr) Increment Error Count Unmask ACK else Reset Error Count else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (Do ping protocol for HS) - Page 358 AT32F425 Series Reference Manual 4. The OTGFS host attempts to send an IN token in the next frame (odd) 5. The OTGFS host generates a RXFLVL interrupt as soon as an IN packet is received and written to the receive FIFO 6.
-
Page 359: Initialize Interrupt Out Transfers
AT32F425 Series Reference Manual Unmask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) Reset Error Count Mask ACK The application can only write a request to the same channel when the remaining space in the request queue reaches the number defined in the MC field, before switching to other channles (if any). -
Page 360: Figure 20-8 Shows An Example Of Common Interrupt Out/In Transfers
AT32F425 Series Reference Manual Figure 20-8 shows an example of common interrupt OUT/IN transfers Application Host Device init_reg(ch_1) Periodic Request Queue init_reg(ch_2) Assume that this queue write_tx_fifo can hold 4 entries. (ch_1) set_ch_en(ch_2) ch_1 ch_2 Odd (micro) frame DATA0 XFERC... -
Page 361: Initialize Synchronous In Transfers
AT32F425 Series Reference Manual Reset Error Count Mask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) Reset Error Count... -
Page 362: Initialize Synchronous Out Transfers
AT32F425 Series Reference Manual an IN packet (GRXSTSR.PKTSTS!= 0x0010) 8. The controller generates an XFERC interrupt as soon as the receive packet is read 9. To handle the XFERC interrupt, read the PKTCN bit in the OTGFS_HCTSIZ2 register. If the PKTCNT bit in the OTGFS_HCTSIZ2 is not equal to 0, disable the channel before re-initializing the channel for the next transfer. -
Page 363: Figure 20-9 Example Of Common Synchronous Out/In Transfers
AT32F425 Series Reference Manual 1. Initialize channel 1 (according to OTGFS channel initialization requirements). The application must set the ODDFRM bit in the OTGFS_HCCHAR2 register 2. Write the first packet to the channel 1 3. Along with the last DWORD write of each packet, the host writes a reques to the periodic request queue 4. -
Page 364: Otgfs Device Mode
AT32F425 Series Reference Manual else if (CHHLTD) Mask CHHLTD De-allocate Channel 20.5.4 OTGFS device mode 20.5.4.1 Device initialization The application must perform the following steps to initialize the controller during power-on or after switching a mode from host to device: 1. -
Page 365: Endpoint Initialization On Enumeration Completion
AT32F425 Series Reference Manual OTGFS_DOEPTSIZ0.SUPCNT = 0x3(to receive up to 3 consecutive SETUP packets) At this point, all initialization required to receive SETUP packets is done. 20.5.4.3 Endpoint initialization on enumeration completion This section describes the operations required for the application to perform when an enumeration completion interrupt signal is detected: ... -
Page 366: Usb Endpoint Deactivation
AT32F425 Series Reference Manual 2. Once the endpoint is activated, the controller starts deconding the tokens issued to this endpoint and sends out a valid handshake for each valid token received for the endpoint 20.5.4.7 USB endpoint deactivation This section describes how to deactivate an existing endpoint. Disable the suspended transfer before performing endpoint deactivation. -
Page 367: Control Transfers (Setup/Status In)
AT32F425 Series Reference Manual The application can receive up to 64-byte data for a single IN data transfer of control endpoint 0. If the application expects to receive more than 64-byte data during data IN stage, it must re-enable... -
Page 368: Out Data Transfers
AT32F425 Series Reference Manual endpoint, and the start of the data stage. After this request is popped from the receive FIFO, the controller triggers a Setup interrupt on the speficied control OUT endpoint Data OUT packet mode: PKTSTS = DataOUT, BCnt =size of the received data OUT packet (0 ≤... - Page 369 AT32F425 Series Reference Manual of the NAK status bit and EPENA bit in the OTGFS_DOEPCTLx register. The SUPCNT bit is decremented each time the control endpoint receives a SETUP packet. If the SUPCNT bit is not programmed to a proper value before receiving a SETUP packet, the controller still receives the SETUP packet and decrementes the SUPCNT bit, but the application may not be able to determine the exact number of SETUP packets received in the SETUP stage of a control transfer.
-
Page 370: In Data Transfers
AT32F425 Series Reference Manual Figure 20-11 SETUP data packet flowchart Waiting for DOEPINTn.SETUP B2BSTUP Interrupt bit set? rem_supcnt = setup_addr = rd_reg(DOEPTSIZn) rd_reg(DOEPDMAn) setup_cmd[31:0] = mem[4-2* rem_supcnt] setup_cmd[31:0] = mem[setup_addr-8] setup_cmd[63:32] = mem[5-2* rem_supcnt] setup_cmd[63:32] = mem[setup_addr-4] Find setup cmd type... -
Page 371: Non-Periodic (Bulk And Control) In Data Transfers
AT32F425 Series Reference Manual application can first write into the endpoint control register before writing the data into the data FIFO. Normally, except for setting the endpoint enable bit, the application must do a read modify write on the OTGFS_DIEPCTLx register to avoid modifying the contents of the register. If the space is enough, the application can write multiple data packets for the same endpoint into the transmit FIFO. -
Page 372: Non-Synchronous Out Data Transfers
AT32F425 Series Reference Manual 6. If there are no data in the FIFO on a received IN token and the packet count for the endpoint is 0, the controller generates an “IN token received when FIFO is empty” interrupt, and the NAK bit for the endpoint is not set. - Page 373 AT32F425 Series Reference Manual If there is no space in the receive FIFO, synchronous or non-synchronous data packets are ignored and not written to the receive FIFO. Besides, the non-synchronous OUT tokens receive a NAK handshake response. In all the above-mentioned cases, the packet count is not decremented because no data is written to the receive FIFO.
-
Page 374: Synchronous Out Data Transfers
AT32F425 Series Reference Manual Figure 20-12 BULK OUT transfer block diagram Host Device Application XFERSIZE = 512bytes int_out_ep PKTCNT = 1 wr_reg(DOEPTSIZn) EPENA = 1 CNAK = 1 wr_reg(DOEPCTLn) 512 bytes xact_1 idle until intr On new xfer or RXFIFO not... -
Page 375: Enable Synchronous Endpoints
AT32F425 Series Reference Manual 2. For synchronous OUT data transfers, the transfer size and packet count must be set to the number of the largest-packet-size packets that can be received in a single frame and not exceed this size. Synchronous OUT data transfer cannot span more than one frame. - Page 376 AT32F425 Series Reference Manual endpoint of the frame before the frame to be transmitted. For example, to send data on the frame n, enable the endpoint of the frame n-1. Additionally, the OTGFS controller schedules the synchronous transfers by setting Even/Odd frame bits.
-
Page 377: Incomplete Synchronous Out Data Transfers
AT32F425 Series Reference Manual The INCOMPISOIN interrupt in the OTGFS_GINTSTS register is a global interrupt. Therefore, when more than one synchronous endpoints are in active state, the application must determine which one of the synchronous IN endpoints has not yet completed data transfers. -
Page 378: Incomplete Synchronous In Data Transfers
AT32F425 Series Reference Manual 6. Wait for the endpoint disable interrupt in the OTGFS_DOEPINTx register, and enable the endpoint to receive new data in the next frame by following the steps listed in “SETUP/Data IN/Status OUT”. Because the controller can take some time to disable the endpoint, the application may not be able to receive the data in the next frame after receiving wrong synchronous data. - Page 379 AT32F425 Series Reference Manual The application cannot transmit a zero-length data packet at the end of a transfer. But it can transmit a single zero-length data packet in itself, provided packet count [epnum] = 1, mc[epnum] = packet count [epnum] 2.
-
Page 380: Otgfs Control And Status Registers
AT32F425 Series Reference Manual reading the OTGFS_DIEPTSIZx register, only transfer size =0 and packet count =0 indicate that all data are transmitted on the USB line. 8. The assertion of the XFERC interrupt in the OTGFS_DIEPINTx register, with or without the INTKNTXFEMP interrupt, indicates the successful completion of an interrupt IN transfer. -
Page 381: Otgfs Register Address Map
AT32F425 Series Reference Manual The OTGFS control and status registers contain OTGFS global register, host mode register, device mode register, data FIFO register, power and clock control register. 1. OTGFS global registers: They are active in both host and device modes. The register acronym is 2. - Page 382 AT32F425 Series Reference Manual OTGFS_DIEPTXF11 0x12C 0x0200 0400 OTGFS_DIEPTXF12 0x130 0x0200 0400 OTGFS_DIEPTXF13 0x134 0x0200 0400 OTGFS_DIEPTXF14 0x138 0x0200 0400 OTGFS_DIEPTXF15 0x13C 0x0200 0400 OTGFS_DIEPTXF16 0x140 0x0200 0400 OTGFS_HCFG 0x400 0x0000 0000 OTGFS_HFIR 0x404 0x0000 EA60 OTGFS_HFNUM 0x408 0x0000 3FFF...
- Page 383 AT32F425 Series Reference Manual OTGFS_HCCHAR7 0x5E0 0x0000 0000 OTGFS_HCINT7 0x5E8 0x0000 0000 OTGFS_HCINTMSK7 0x5EC 0x0000 0000 OTGFS_HCTSIZ7 0x5F0 0x0000 0000 OTGFS_HCCHAR8 0x600 0x0000 0000 OTGFS_HCINT8 0x608 0x0000 0000 OTGFS_HCINTMSK8 0x60C 0x0000 0000 OTGFS_HCTSIZ8 0x610 0x0000 0000 OTGFS_HCCHAR9 0x620 0x0000 0000...
- Page 384 AT32F425 Series Reference Manual OTGFS_DAINT 0x818 0x0000 0000 OTGFS_DAINTMSK 0x81C 0x0000 0000 OTGFS_DIEPEMPMSK 0x834 0x0000 0000 OTGFS_DIEPCTL0 0x900 0x0000 0000 OTGFS_DIEPINT0 0x908 0x0000 0080 OTGFS_DIEPTSIZ0 0x910 0x0000 0000 OTGFS_DTXFSTS0 0x918 0x0000 0200 OTGFS_DIEPCTL1 0x920 0x0000 0000 OTGFS_DIEPINT1 0x928 0x0000 0080...
-
Page 385: Otgfs Global Registers
AT32F425 Series Reference Manual OTGFS_DOEPCTL2 0xB40 0x0000 0000 OTGFS_DOEPINT2 0xB48 0x0000 0080 OTGFS_DOEPTSIZ2 0xB50 0x0000 0000 OTGFS_DOEPCTL3 0xB60 0x0000 0000 OTGFS_DOEPINT3 0xB68 0x0000 0080 OTGFS_DOEPTSIZ3 0xB70 0x0000 0000 OTGFS_DOEPCTL4 0xB80 0x0000 0000 OTGFS_DOEPINT4 0xB88 0x0000 0080 OTGFS_DOEPTSIZ4 0xB90 0x0000 0000... -
Page 386: Otgfs Ahb Configuration Register (Otgfs_Gahbcfg)
AT32F425 Series Reference Manual 20.6.3.3 OTGFS AHB configuration register (OTGFS_GAHBCFG) This register is used to configure the controller after power-on or mode change. This register mainly contains AHB-related parameters. Do not change this register after the initial configuration. The application must configure this register before starting transmission on either the AHB or USB. -
Page 387: Otgfs Reset Register (Otgfs_Grstctl)
AT32F425 Series Reference Manual USB Turnaround Time This field sets the turnaround time in PHY clocks. It defines the response time when the MAC sends a request to the packet FIFO controller (PFC) to fetch data from the DFIFO (SPRAM). These bits must be configured as follows:... - Page 388 AT32F425 Series Reference Manual ensures that the controller is not reading from the FIFO Write: AHBIDLE bit in GRSTCTL ensures that the controller is not writing to the FIFO. For FIFO reprogramming, it is usually recommended to carry out flushing operaton.
-
Page 389: Otgfs Interrupt Register (Otgfs_Gintsts)
AT32F425 Series Reference Manual this register is set (AHB master is in idle state) before performing other operations. Typically, the software set is used during software development and also when the user dynamically changes the PHY selection bits in the above-listed USB configuration registers. - Page 390 AT32F425 Series Reference Manual Control and Status register to clear this bit. Bit 23: 22 Reserved resd Kept at its default value. Incomplete periodic transfer Accesible in host mode only In host mode, the controller sets this interrupt bit when there are incomplete periodic transfers still pending in the current frame.
- Page 391 AT32F425 Series Reference Manual Accesible in device mode only USB Reset Bit 12 USBRST rw1c The controller sets this bit to indicate that a reset is detected on the USB bus. Accesible in device mode only USB Suspend The controller sets this bit to indicate that a suspend is...
-
Page 392: Otgfs Interrupt Mask Register (Otgfs_Gintmsk)
AT32F425 Series Reference Manual set after power-on reset, the application can clear this bit. Accesible in both host and device modes OTG interrupt The controller sets this bit to indicate that an OTG protocol event is generated. The application must read the... -
Page 393: Otgfs Receive Status Debug Read/Otg Status Read And Pop Registers (Otgfs_Grxstsr / Otgfs_Grxstsp)
AT32F425 Series Reference Manual Bit 16 Reserved resd Kept at its default value. Accesible in device mode only Bit 15 EOPFMSK End of periodic frame interrupt mask Device only isochronous OUT packet dropped interrupt Bit 14 ISOOUTDROPMSK mask Accesible in device mode only... -
Page 394: Otgfs Receive Fifo Size Register (Otgfs_Grxfsiz)
AT32F425 Series Reference Manual Device mode: Register Reset value Type Description Bit 31: 25 Reserved 0x00 resd Kept at its defaut value. Frame number Indicates the least significant 4 bits of the frame number of Bit 24: 21 the data packet received on the USB bus. This field is applicable only when the synchronous OUT endpoints are supported. -
Page 395: Otgfs Non-Periodic Tx Fifo Size/Request Queue Status Register
AT32F425 Series Reference Manual IN Endpoint FIFO0 transmit SRAM start address Bit 15: 0 INEPT0TXSTADDR 0x0200 ro/rw This field contains the memory start address of the IN Endpoint FIFO0 transmit SRAM. 20.6.3.11 OTGFS non-periodic Tx FIFO size/request queue status register (OTGFS_GNPTXSTS) This register is valid in host mode only. -
Page 396: Otgfs Controller Id Register (Otgfs_Guid)
AT32F425 Series Reference Manual 1: Low-power mode Power down This bit is used activate the transceiver transmission/reception. It must be pre-configured to allow Bit 16 PWRDOWN USB communication. 0: Power down enable 1: Power down disable (Transceiver active) Bit 15: 0... -
Page 397: Otgfs Host Frame Interval Register (Otgfs_Hfir)
AT32F425 Series Reference Manual connected device supports high-speed communication. Do not change this bit after initial programming. 0: FS/LS, depending on the largest speed supported by the connected device. 1: FS/LS-only, even if the onnected device supports high- speed. FS/LS PHY clock select... -
Page 398: Otgfs Host Periodic Tx Fifo/Request Queue Register (Otgfs_Hptxsts)
AT32F425 Series Reference Manual 20.6.4.4 OTGFS host periodic Tx FIFO/request queue register (OTGFS_HPTXSTS) This is a ready-only register containing the free space information of the perioid Tx FIFO and the periodic transmit request queue. Register Reset value Type Description Top of the periodic transmit request queue) Indicates that the MAC is processing the request from the perioic tranmit request queue. -
Page 399: Otgfs Host Port Control And Status Register (Otgfs_Hprt)
AT32F425 Series Reference Manual 20.6.4.7 OTGFS host port control and status register ( OTGFS_HPRT) This register is valid only in host mode. Currently, the OTG host supports only one port. This register contains USB port-relatd information such as USB reset, enable, suspend, resume, connect... -
Page 400: Otgfs Host Channelx Characteristics Register (Otgfs_Hccharx) (X = 0
AT32F425 Series Reference Manual resume/remote wakeup detected interrupt disconnect detected interrupt bit in the controller interrupt register. The controller can still clear this bit, even if the device is disconnected with the host. 0: Port not in suspend mode 1: Port in suspend mode... -
Page 401: Otgfs Host Channelx Interrupt Register (Otgfs_Hcintx)
AT32F425 Series Reference Manual that channel is complete. The application must wait for the generation of the channel disabled interrupt before treating the channel as disabled. Odd frame This bit is set / cleared by the application to indicate that the OTG host must perform a transfer in an odd frame. -
Page 402: Otgfs Host Channelx Interrupt Mask Register (Otgfs_Hcintmskx)
AT32F425 Series Reference Manual bus: CRC check failure Timeout Bit stuffing error EOP error This bit can only be set by the controller. The application must write 1 to clear this bit. Bit 6 Reserved resd Kept at its default value. -
Page 403: Device-Mode Registers
AT32F425 Series Reference Manual indicate normal completion of the transfer. Transfer size For an OUT transfer, this field indicates the number of data bytes the host sends during a transfer. For an IN transfer, this field indicates the buffer size that... -
Page 404: Table 20-5 Minimum Duration For Software Disconnect
AT32F425 Series Reference Manual Writing 1 to this bit clears the global OUT NAK. Set global OUT NAK Wrting to this bit sets the global OUT NAK. The application uses this bit to send a NAK handshake on Bit 9 SGOUTNAK all OUT endpoints. -
Page 405: Otgfs Device Status Register (Otgfs_Dsts)
AT32F425 Series Reference Manual No idle or suspend Full speed 2.5us (performing transfers) 20.6.5.3 OTGFS device status register (OTGFS_DSTS) This register indicates the status of the controller related to OTGFS events. It must be read on interrupt events from the device all interrupts register (OTGFS_DAINT). -
Page 406: Otgfs Device Out Endpoint Common Interrupt Mask Register (Otgfs_Doepmsk)
AT32F425 Series Reference Manual IN token received when TxFIFO empty mask Bit 4 INTKNTXFEMPMSK 0x0 0: Interrupt masked 1: Interrupt unmasked Timeout condition mask (Non-isochronous endpoints)) Bit 3 TIMEOUTMSK 0: Interrupt masked 1: Interrupt unmasked Bit 2 Reserved resd Kept at its defaut value. -
Page 407: Otgfs All Endpoints Interrupt Mask Register (Otgfs_Daintmsk)
AT32F425 Series Reference Manual endpoint 7. 20.6.5.7 OTGFS all endpoints interrupt mask register (OTGFS_DAINTMSK) When an event occurs on a device endpoint, the device endpoint interrupt mask register works with the device endpoint interrupt register to interrupt the application. However, the device all endpoints interrupt register corresponding to this interrupt is still set. -
Page 408: Otgfs Device In Endpoint -X Control Register (Otgfs_Diepctlx)
AT32F425 Series Reference Manual A write to this bit clears the NAK bit for the endpoint. TxFIFO number Bit 25: 22 TXFNUM The endpoint 0 can only use FIFO0. STALL handshake The application sets this bit, and the controller clears this... - Page 409 AT32F425 Series Reference Manual frame 1: Set DATA1 PID enabled or forced odd frame Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this bit sets the endpoint data PID bit in this register to DATA0. Set Even frame...
-
Page 410: Otgfs Device Control Out Endpoint 0 Control Register
AT32F425 Series Reference Manual EOFRNUM Applies to interrupt/bulk IN endpoints only. This bit contains the PID of the packet to be transmitted on this endpoint. The application must program the PID of the initial data packet to be received or transmitted on this endpoint, after the endpoing is enabled. -
Page 411: Otgfs Device Control Out Endpoint-X Control Register
AT32F425 Series Reference Manual responds to SETUP data packets, regardless of whether this bit is set or not. Snoop mode This bit configures the endpint to Snoop mode. In this Bit 20 mode, the controller does not check the correctness of OUT packets before transmitting OUT packets to the application memory. - Page 412 AT32F425 Series Reference Manual frame 1: Set DATA1 PID enabled or forced odd frame Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this bit sets the endpoint data PID bit in this register to DATA0. Set Even frame...
-
Page 413: Otgfs Device In Endpoint -X Interrupt Register (Otgfs_Diepintx)
AT32F425 Series Reference Manual this endpoint. The application must program the PID of the initial data packet to be received or transmitted on this endpoint, after the endpoing is enabled. The application programs DATA0 or DATA1 PID through the SetD1PID and SetD0PID of this register. -
Page 414: Otgfs Device Out Endpoint-X Interrupt Register
AT32F425 Series Reference Manual Timeout condition Applies to control IN endpoints only. This bit indicates that Bit 3 TIMEOUT rw1c the controller has detected a timeout condition for the last IN token on this endpoint. Bit 2 Reserved resd Kept at its default value. -
Page 415: Otgfs Device Out Endpoint 0 Transfer Size Register
AT32F425 Series Reference Manual controller interrupts the application when the transfer size becomes 0. The transfer size can be set to the maximum packet size of the endpoint at the end of eack packet. The controller decrements this field every time a packet from the external memory is written to the transmit FIFO. -
Page 416: Otgfs Device In Endpoint Transmit Fifo Status Register
AT32F425 Series Reference Manual Transfer Size Indicates the transfer size (in bytes) for the current endpoint. The controller interrupts the application when the transfer size becomes 0. The transfer size can be set to Bit 18: 0 XFERSIZE 0x00000 the maximum packet size of the endpoint, to be interrupted at the end of eack packet. -
Page 417: Power And Clock Control Registers
AT32F425 Series Reference Manual 20.6.6 Power and clock control registers 20.6.6.1 OTGFS power and clock gating control register (OTGFS_PCGCCTL) This register is available in host and device modes. Register Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at its default value. -
Page 418: Hick Auto Clock Calibration (Acc)
AT32F425 Series Reference Manual 21 HICK auto clock calibration (ACC) 21.1 ACC introduction HICK auto clock calibration (HICK ACC), which uses the SOF signal (1 ms of period) generated as a reference signal, implements the sampling and calibration for the HICK clocks. -
Page 419: Figure 21-2 Acc Block Diagram
AT32F425 Series Reference Manual CRM_HICKCAL: the HICKCAL bit in the CRM module. This signal is used to calibrate the HICK in bypass mode. The value is defined by the HICKCAL[7: 0] in the CRM_CTRL register. CRM_HICKTRIM: the HICKTRIM bit in the CRM module. This signal is used to calibrate the HICK in bypass mode. -
Page 420: Principle
AT32F425 Series Reference Manual 21.5 Principle USB_SOF period signal: 1ms of period must be accurate, which is a prerequisite of the normal operaion of an auto calibration module. cross-return algorithm: This is used to calculate a calibration value closest to the theoretic value. In theory, the actual frequency after calibration can be adjusted to be within an accuracy range of about 0.5 steps from the target frequency (8MHz) -
Page 421: Register Description
AT32F425 Series Reference Manual 21.6 Register description Refer to the list of abbreviations used in register descriptions. These peripheral registers must be accessed by words (32 bits). 21.6.1 ACC register map Table 21-2 ACC register map and reset values Register name... -
Page 422: Control Register 2 (Acc_Ctrl2)
AT32F425 Series Reference Manual Bit 7: 6 Reserved Forced by hardware to 0 CALRDY interrupt enable This bit is set or cleared by software. Bit 5 CALRDYIEN 0: Interrupt generation disabled 1: ACC interrupt is generated when CALRDY=1 in the... -
Page 423: Compare Value 2 (Acc_C2)
AT32F425 Series Reference Manual 21.6.6 Compare value 2 (ACC_C2) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Forced to 0 by hardware Compare 2 This value defines the number of clocks sampled for 8MHz (ideal frequency) clock in 1ms period , and its default value... -
Page 424: Infrared Timer (Irtmr)
AT32F425 Series Reference Manual 22 Infrared timer (IRTMR) The IRTMR (Infrared Timer) is used to generate the IR_OUT signal that drives the infrared LED so as to achieve infrared control. The IR_OUT signals consists of a low-frequency modulation envelope and high-frequency carrier signals. -
Page 425: Debug (Debug)
AT32F425 Series Reference Manual 23 Debug (DEBUG) 23.1 Debug introduction Cortex™-M4 core provides poweful debugging features including halt and single step support, as well as trace function that is used for checking the details of the program execution. The debug features are implemented with a serial wire debug interface. -
Page 426: Debug Control Register (Debug_Ctrl)
AT32F425 Series Reference Manual PID [31: 0] AT32 part number FLASH size Packages 0x5009_2100 AT32F425R8T7 64KB 64LQFP (10 x10) 0x5009_2081 AT32F425R6T7 32KB 64LQFP (10 x10) 0x5009_2103 AT32F425R8T7-7 64KB 64LQFP (7 x 7) 0x5009_2084 AT32F425R6T7-7 32KB 64LQFP (7 x 7) 0x5009_2106... - Page 427 AT32F425 Series Reference Manual 1: TMR3 stops running TMR2 debug control bit Bit 11 TMR2_PAUSE 0: TMR2 runs normally 1: TMR2 stops running TMR1 debug control bit Bit 10 TMR1_PAUSE 0: TMR1 runs normally 1: TMR1 stops running WDT pause control bit...
-
Page 428: Revision History
AT32F425 Series Reference Manual 24 Revision history Document Revision History Date Version Revision Note Initial release. 2022.01.12 2.00 Added contents and book marks. 2022.03.30 2.01 2022.03.30 Page 428 Ver 2.01... - Page 429 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previous representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third party’s products or services...
Need help?
Do you have a question about the AT32F425 Series and is the answer not in the manual?
Questions and answers