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ARTERY AT32F403A Getting Started

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Introduction
This application note is written to help users with rapid project development using AT32F403Axx
/AT32F407xx (compared with AT32F403A, AT32F407 is featured with Ethernet media access
control (EMAC) additionally).
Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by
Artery. For other versions of BSP, please pay attention to the differences in usage.
Applicable products:
Part number
2022.10.21
Getting Started with AT32F403A & AT32F407
Getting Started with AT32F403A & AT32F407
AT32F403Axx
AT32F407xx
1
AN0023
Application Note
Ver 2.0.3

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Summary of Contents for ARTERY AT32F403A

  • Page 1 /AT32F407xx (compared with AT32F403A, AT32F407 is featured with Ethernet media access control (EMAC) additionally). Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by Artery. For other versions of BSP, please pay attention to the differences in usage. Applicable products: AT32F403Axx...

  • Page 2: Table Of Contents

    1.1.2 Programming tools and software................6 1.1.3 AT32 development environment................7 1.1.4 How to replace SXX ....................12 AT32F403A /AT32F407 chip enhanced functions ............13 1.2.1 PLL clock settings ....................13 1.2.2 How to enable FPU function................... 15 1.2.3 AT32F403A /AT32F407 zero-wait/non-zero-wait Flash and embedded SRAM configurations ........................
  • Page 3 Getting Started with AT32F403A & AT32F407 List of Tables Table 1. Document revision history ....................34 2022.10.21 Ver 2.0.3...
  • Page 4 Figure 14. IAR Debug option ......................12 Figure 15. IAR CMSIS-DAP option ....................12 Figure 16. Use SXX to output 240 MHz clock on AT32F403A /AT32F407 ........13 Figure 17. AT32F403A /AT32F407 crm_pll_output_range parameter ..........13 Figure 18. New Clock Configuration....................14 Figure 19.
  • Page 5 Getting Started with AT32F403A & AT32F407 Figure 34. Disable access protection in ISP Programmer.............. 23 Figure 35. Enable erase and program protection in ICP Programmer ........... 24 Figure 36. Disable erase and program protection in ICP Programmer ........... 24 Figure 37. Encrypt external memory in ICP Programmer .............. 26 Figure 38.

  • Page 6: Preliminary Environment Requirements

    Build AT32 development environment 1.1.1 Debug tools and evaluation board The AT32F403A /AT32F407 evaluation board has an AT-Link-EZ debug tool, as shown in the red box in Figure 1 below. The AT-Link-EZ can be disassembled and used with other circuit boards, supporting IDE online debugging, online programming and USB-to-serial port.

  • Page 7: At32 Development Environment

    Getting Started with AT32F403A & AT32F407  party programming tools: J-Link, Armfly, Alientek, XWOPEN, ICWORKSHOP, ZLG, MaxWiz, Amomcu, Acroview, Forcreat, Galecomm, Prosystems, Rx-prog, Sinaen, XELTEK, Zhifeng, etc. ARTERY’s official website→SUPPORT→Hardware Development Note: For more information, please visit Tool and 3 Party Writer.

  • Page 8: Figure 5. Keil_V5 Templates

    Getting Started with AT32F403A & AT32F407 AT32F403A_407_Firmware_Library_V2.x.x\project\at_start_f4xx\templates. Open the project folder and click on the project file to open the corresponding IDE project. The example of Keil_v5 template project is shown below. Figure 5. Keil_v5 templates Contents in the project: ①...

  • Page 9: Figure 6. Pack Download

    Getting Started with AT32F403A & AT32F407 Figure 6. Pack download For Keil compiling system, keil 4.74 /5.23 or above is recommended. If Keil_v5 is used, please unzip Keil5_AT32MCU_AddOn and install the corresponding ArteryTek.AT32F403A_407_DFP. If Keil_v4 is used, please install Keil4_AT32MCU_AddOn. By default, the Keil installation path can be recognized automatically during installation.

  • Page 10: Figure 9. Pack Installer Icon In Keil

    Getting Started with AT32F403A & AT32F407 Figure 9. Pack Installer icon in Keil For IAR compiling system, IAR7.0 or IAR6.1 above is recommended. It is necessary to install IAR_AT32MCU_AddOn. By default, the IAR installation path can be recognized automatically during installation.

  • Page 11: Figure 11. Keil Debug Option

    Getting Started with AT32F403A & AT32F407 Figure 11. Keil Debug option Go to Debug and click on Settings to enter the Cortex-M Target Driver Setup interface. Select AT-Link(WinUSB)-CMSIS-DAP/AT-Link-CMSIS-DAP; Note: For details about WinUSB, please refer to FAQ0136_How to use AT-LINK WinUSB to improve download (ARTERY’s official...

  • Page 12: How To Replace Sxx

    AT32F403A_407 Firmware BSP&Pack User Guide. Path: →Mainstream→AT32F4xx; download and unzip BSP (\AT32F403A_407_Firmware_Library_Vx.x.x\document). 1.1.4 How to replace SXX  Compare the peripheral specifications, Flash size and SRAM size, etc.; unsolder SXX32F103 and replace it with the corresponding AT32F403A/AT32F407 part; 2022.10.21 Ver 2.0.3...

  • Page 13: At32F403A /At32F407 Chip Enhanced Functions

    When the SXX32F103 BSP is used, the PLL setting example (HEXT=8 MHz, PLL=72 MHz) RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); If the user wants to use SXX32F103 program to output a lock greater than 72 MHz on AT32F403A /AT32F407, it is necessary to configure the PLLRANGE bit.

  • Page 14: Figure 18. New Clock Configuration

    Figure 18. New Clock Configuration 1.2.1.2 Auto step-by-step clock switch When the internal PLL of AT32F403A /AT32F407 is set to 108 MHz and above, it is necessary to perform auto step-by-step clock switch function. When the SXX32F103 program is used, the user needs to open system_Sxx32f10x.c, find out the current system clock frequency configuration function (go through Section 1.2.1.1 PLL settings),...

  • Page 15: How To Enable Fpu Function

    Getting Started with AT32F403A & AT32F407 When AT32F403A /AT32F407 BSP is used, the example of PLL auto step-by-step switch is shown below: Figure 20. AT32 PLL auto step-by-step switch configurations /* enable auto step mode */ crm_auto_step_mode_enable(TRUE); /* select pll as system clock source */ crm_sysclk_switch(CRM_SCLK_PLL);...

  • Page 16: Figure 22. Add Fpu Enabling Codes In Keil

    Getting Started with AT32F403A & AT32F407 Figure 22. Add FPU enabling codes in Keil /* Enable FPU*/ #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U * 2U) | /* set CP10 Full Access */ (3U << 11U * 2U)

  • Page 17: At32F403A /At32F407 Zero-Wait/Non-Zero-Wait Flash And Embedded Sram Configurations

    The core reads the command code stored in zero-wait Flash without any latency, and it is unnecessary to insert any wait state. For example, if the system clock is 240 MHz and AT32F403A zero-wait Flash is 256 KB, the first 256 KB of 512 KB bin file can be executed at 240 MHz, and the later 256 KB bin file is stored in the non-zero wait area and executed at 96 MHz, which is faster than 72 MHz (the maximum frequency of SXX32F10X).

  • Page 18: Figure 26. Select Sram Size In User System Data

    Getting Started with AT32F403A & AT32F407 Figure 26. Select SRAM size in user system data  Artery ISP Programmer (BOOT0=1, BOOT1=0) Connect UART or USB to MCU—Click on “Next” until enter the final interface—Select “Edit User system data”—Next— Select EOPB0 96 KB/224 KB (complete other relevant settings if any) —...

  • Page 19: Figure 28. User System Data Setting In Isp Multi-Port Programmer

    Getting Started with AT32F403A & AT32F407  Artery ISP Multi-Port Programmer (BOOT0=1, BOOT1=0) Select the port to be used—download user system data file after the port is recognized successfully—Edit—Select 16 KB/32 KB/64 KB—Save to file (create a user system data program file)—Close—Start, or download user system data file—Open (the saved user system...

  • Page 20: Figure 30. Define Extend_Sram(Void) Function In At32 Program

    Getting Started with AT32F403A & AT32F407 When the AT32F403A/ AT32F407 is used: Extend_SRAM(void) function in Figure 30. Define AT32 program #define SRAM_96k 0xFF #define SRAM_224k 0xFE static uint32_t f_eopb0; f_eopb0=*(uint32_t*)(0x1FFFF810); void Extend_SRAM(void) if((f_eopb0 & 0xFF) != 0xFE) // check if RAM has been set to 224K, if not, change EOPB0 flash_unlock();...

  • Page 21: Figure 32. Modify Sram Size In Iar Startup File

    Getting Started with AT32F403A & AT32F407 SP, R0 R0, =Extend_SRAM MOV32 R0, #0x08000000 SP, [R0] R0, =SystemInit R0, =__main ENDP Add the codes in bold (as shown in Figure 32) to the IAR startup file. Modify SRAM size in IAR startup file Figure 32.

  • Page 22: Encryption Mode (Access Protection /Erase And Program Protection /External Flash Encryption)

    The ICP/ISP tool can be used to enable and disable IC access protection, as shown below:  Artery ICP Programmer (BOOT0=0, BOOT1=0) Enable access protection: Open Artery ICP Programmer—Access protection—Enable (Y). Disable access protection: Open Artery ICP Programmer-- Access protection—Disable (Y).  Artery ISP Programmer (BOOT0=1, BOOT1=0) Enable access protection: Protection/Enable/Access protection--Next—Yes, encrypted.

  • Page 23: Figure 34. Disable Access Protection In Isp Programmer

     Artery ICP Programmer (BOOT0=0, BOOT1=0) Enable erase and program protection: Open Artery ICP Programmer —User system data—Tick the sectors that require erase and program protection—Apply to device. Disable erase and program protection: Open Artery ICP Programmer —User system data—...

  • Page 24: Figure 35. Enable Erase And Program Protection In Icp Programmer

    Getting Started with AT32F403A & AT32F407 Figure 35. Enable erase and program protection in ICP Programmer Figure 36. Disable erase and program protection in ICP Programmer 2022.10.21 Ver 2.0.3...
  • Page 25 Getting Started with AT32F403A & AT32F407  Artery ISP Programmer (BOOT0=1, BOOT1=0) Enable erase and program protection: Protection/Enable/Erase and program protection— Next—Yes, erase and program protection enabled. Disable erase and program protection: Protection/Disable/Erase and program protection — Next—Yes, erase and program protection disabled.

  • Page 26: Recognize At32 Mcu In Program

    Getting Started with AT32F403A & AT32F407 Figure 37. Encrypt external memory in ICP Programmer  Artery ISP Programmer (BOOT0=1, BOOT1=0) Edit user system data—Next—Modify the encryption key—Apply to device. Figure 38. Encrypt external memory in ISP Programmer  Artery ISP Multi-Port Programmer (BOOT0=1, BOOT1=0) Download user system data file—Edit—Modify the encryption key—Save to file—Start.

  • Page 27: Figure 39. Read Cortex Id

    Figure 40. Read PID and UID /* Get the base address of AT32 MCU PID/UID */ #define DEVICE_ID_ADDR1 0x1FFFF7F3 // Define Artery MCU part number, UID base address #define DEVICE_ID_ADDR2 0xE0042000 // Define MCU device number, PID base address /* Used to store ID */ uint8_t ID[5] = {0};...

  • Page 28: Faqs In Downloading/Compiling

    Please refer to FAQ0008_ J-Link cannot find IC SUPPORT→FAQ→FAQ0008). (ARTERY’s official website→  Please refer to FAQ0132_Add Artery MCU to J-Link SUPPORT→FAQ→FAQ0132). Problems in program downloading 2.3.1 Error: Flash Download failed–“Cortex-M4” The following pop-up window appears in KEIL emulation or downloading: 2022.10.21...

  • Page 29: No Debug Unit Device Found

     Replace with better USB-to-serial port tools, i.e., CH340 chip. 2.3.5 Resume download When using AT32F403A /AT32F407, the user may not be able to download the program again in the following conditions:  After disabling JTAG/SWD PIN in the program, the program cannot be downloaded and 2022.10.21...

  • Page 30: Figure 43. Operate Configjlink_V1.0.0 In Keil

    Solutions in KEIL and IAR are as follows:  Solution 1: Use the ConfigureJLink.exe provided by ARTERY.  Solution 2: Switch boot mode: switch to Boot[1:0]=01b or Boot[1:0]=11b, and then press “Reset” button to resume download (note: switch back to Boot[1:0]=00b). Similarly, ISP download can be resumed.

  • Page 31: Figure 44. Configjlink_V1.0.0 Execution Progress In Keil

    Note 3: If the MCU enters Standby mode every time the program is downloaded, perform the preceding steps before the chip is powered on. Note 4: In Keil, AT32F403A /AT32F407 enters Standby mode, the solution using ConfigureJLink.exe is invalid. 2.3.5.2 Solutions in IAR Use the ConfigJLink_V1.0.0.exe provided by ARTERY.

  • Page 32: Security Library (Slib)

    Getting Started with AT32F403A & AT32F407 Figure 46. ConfigJLink_V1.0.0 execution progress in IAR Note 1: Make sure that SEGGER J-Link interface DLL is not lower than V6.14. Note 2: If JTAG/SWD PIN is disabled every time the program is downloaded, perform the preceding steps before downloading the program.

  • Page 33: Security Library Application

    Getting Started with AT32F403A & AT32F407 security library protection. When the security library protection is disabled, the chip will perform a mass erase on the main Flash memory (including the contents of security library). Therefore, even if the code defined by the software solution provider is leaked, the program code will not be leaked.

  • Page 34: Revision History

    Getting Started with AT32F403A & AT32F407 Revision history Table 1. Document revision history Date Version Revision note 2021.12.27 2.0.0 Initial release 2022.08.03 2.0.1 Updated 3 party programming tools. 2022.10.08 2.0.2 Added description of development environment and file path. 2022.10.21 2.0.3 Optimized description of UID and PID.
  • Page 35 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previou s representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third...

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