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ARTERY AT32F421 Series Getting Started

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Introduction
This application note is written to help users with rapid project development using AT32F421xx.
Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by
Artery. For other versions of BSP, please pay attention to the differences in usage.
Applicable products:
Part number
2022.10.21
Getting Started with AT32F421
Getting Started with AT32F421
AT32F421xx
1
AN0024
Application Note
Ver 2.0.4

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Summary of Contents for ARTERY AT32F421 Series

  • Page 1 This application note is written to help users with rapid project development using AT32F421xx. Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by Artery. For other versions of BSP, please pay attention to the differences in usage. Applicable products:...

  • Page 2: Table Of Contents

    Getting Started with AT32F421 Contents Preliminary environment requirements ............... 5 Build AT32 development environment ..............5 Debug tools and evaluation board ................5 Programming tools and software ................. 5 AT32 development environment .................. 6 How to replace SXX ....................11 AT32F421 chip enhanced functions ...............
  • Page 3 Getting Started with AT32F421 List of Tables Table 1. Document revision history ....................26 2022.10.21 Ver 2.0.4...
  • Page 4 Getting Started with AT32F421 List of Figures Figure 1. AT-START-F421 evaluation board with AT-Link-EZ ............5 Figure 2. AT-START-F421 evaluation board package ................. 5 Figure 3. ICP/ISP/AT-Link-Family ......................6 Figure 4. BSP package ........................6 Figure 5. Keil_v5 templates ......................... 7 Figure 6.

  • Page 5: Preliminary Environment Requirements

    Getting Started with AT32F421 Preliminary environment requirements Download development environment  ARTERY's official website Build AT32 development environment Debug tools and evaluation board The AT32F421 supports AT-Link/J-Link, and the evaluation board has an AT-Link-EZ debug tool (as shown in the red box in Figure 1 below), which can be disassembled and used with other circuit boards, supporting IDE online debugging, online programming and USB-to-serial port.

  • Page 6: At32 Development Environment

    Getting Started with AT32F421 EZ, ICP/ISP.  party programming tools: J-Link, Armfly, Alientek, XWOPEN, ICWORKSHOP, ZLG, MaxWiz, Amomcu, Acroview, Forcreat, Galecomm, Prosystems, Rx-prog, Sinaen, XELTEK, Zhifeng, etc. ARTERY’s official website→SUPPORT→Hardware Development Note: For more information, please visit Tool and 3 Party Writer. ...

  • Page 7: Figure 5. Keil_V5 Templates

    Except for templates, BSP also includes code examples (Keil_v5 project files) in terms of peripherals for reference. Path: AT32F421_Firmware_Library_V2.x.x\project\at_start_f4xx\examples. Note: For more details about BSP, please refer to “Section 4 BSP application” of AT32F421 Firmware ARTERY’s official website→PRODUCTS→Value line→AT32F4xx; download BSP&Pack User Guide. Path: and unzip, and get the “\AT32F421_Firmware_Library_Vx.x.x\document”.

  • Page 8: Figure 6. Pack Download

    Figure 7. Set up ArteryTek.AT32F421 _DFP Figure 8. Set up Keil4_AT32MCU_AddOn You can also open keil and click on “Pack Installer” icon; then click on the top left “file” and select “import” to import the corresponding pack downloaded from ARTERY's official website. 2022.10.21 Ver 2.0.4...

  • Page 9: Figure 9. Pack Installer Icon In Keil

    If the path is not recognized or incorrect, you need to manually select the IAR installation path. Figure 10. Set up IAR_AT32MCU_AddOn Note: For more details about Pack setup, please refer to “Section 2 Pack setup” of AT32F421 Firmware ARTERY’s official website→PRODUCTS→Value line→AT32F4xx; download BSP&Pack User Guide. Path: and unzip BSP, and get the “\AT32F421_Firmware_Library_Vx.x.x\document”.

  • Page 10: Figure 11. Keil Debug Option

    Go to Debug and click on Settings to enter the Cortex-M Target Driver Setup interface. Select AT-Link(WinUSB)-CMSIS-DAP/AT-Link-CMSIS-DAP. Note: For details about WinUSB, please refer to FAQ0136_How to use AT-LINK WinUSB to improve download (ARTERY’s official website→SUPPORT→FAQ→FAQ0136). speed Find Port, select SW and then tick SWJ;...

  • Page 11: How To Replace Sxx

    Figure 14. IAR Debug option Figure 15. IAR CMSIS-DAP option Note: For details about Flash algorithm file, MCU switch and solutions for “J-Link cannot find MCU”, please ARTERY’s official website→PRODUCTS→Value refer to AT32F421 Firmware BSP&Pack User Guide. Path: line→AT32F4xx; download and unzip BSP, and get the “\AT32F421_Firmware_Library_Vx.x.x\document”.

  • Page 12: At32F421 Chip Enhanced Functions

    If the program still cannot run properly after completing the above steps, please refer to other sections of this application note or contact the agent and ARTERY technicians for help. Note: Compared with SXX32F0xx, AT32F421 is more flexible to achieve better performance. Please refer to (ARTERY’s official...

  • Page 13: Pll Clock Settings

    PLL_NS=59, PLL_MS=1, CRM_PLL_FR_4 (0x02, divided by four) represents the PLL_FR value. Please refer to AN0116_AT32F421_CRM_Start_Guide (ARTERY's official website→SUPPORT →AP Note→AN0116) for more details about AT32F421 clock source settings and modification and learn how to use New Clock Configuration (ARTERY's official website→PRODUCTS→Value...

  • Page 14: Figure 19. Sxx Pll Auto Step-By-Step Switch Configurations

    Getting Started with AT32F421 Auto step-by-step switch When the internal PLL of AT32F421 is set to 108 MHz and above, it is necessary to perform auto step-by-step switch. When the SXX32F0xx BSP is used, the user needs to open system_sxx32f0xx.c and find out the current system clock configuration function (go through Section 1.2.2.1 PLL settings), and add the following codes in Italic black to the static void SetSysClockToxxM(void) function: Figure 19.

  • Page 15: Encryption Mode

    The ICP/ISP tool can be used to enable and disable IC access protection, as shown below:  Artery ICP Programmer (BOOT0=0) Enable access protection: Open Artery ICP Programmer—Access protection—Enable access/high-level access protection. Disable access protection: Open Artery ICP Programmer—Access protection—Disable.

  • Page 16: Figure 22. Enable Access Protection In Isp Programmer

    Getting Started with AT32F421 Figure 22. Enable access protection in ISP Programmer Disable access protection in Figure 23. ISP Programmer Note: Once enabled, the access protection cannot be disabled through erase operation. 2022.10.21 Ver 2.0.4...

  • Page 17: Figure 24. Enable Erase And Program Protection In Icp Programmer

    The user can use ICP/ISP tool to enable/disable erase and program protection, as shown below:  Artery ICP Programmer (BOOT0=0) Enable erase and program protection: Open Artery ICP Programmer—User system data—Tick the sectors that require erase and program protection—Apply to device.

  • Page 18: Set Boot Memory As Main Flash Memory Extension Area

    Set boot memory as main Flash memory extension area By default, boot memory stores the original boot codes in BOOT mode. For AT32F421 series MCUs, the boot memory also can be used as the main Flash memory extension area (AP mode) to store user-defined codes.

  • Page 19: Figure 26. Set Ap Mode In Icp Programmer

    “Flash info” interface will display a success or failure message. Figure 27. AP mode enabling in ICP Programmer The user can use Artery ICP Programmer to set the boot memory as the main Flash memory extension area (in mass production) as follows: ...

  • Page 20: Figure 28. Offline Config Settings In Icp Programmer

    Getting Started with AT32F421  Open Artery ICP programmer and select AT-Link to connect;  AT-Link Setting—AT-Link offline config settings;  Generate an offline project as follows: Click on “Create”; Enter project name; Select MCU part number; Add .hex file Select SWD as the download interface;...

  • Page 21: Recognize At32 Mcu In Program

     Refer AN0066_config_boot_memory_as_extension_of_main_memory (AP_mode) website→SUPPORT→AP Note→AN0066) for more information about the (ARTERY's official memory extension.  Refer to BSP for the demo of running user application in boot memory. Path: ARTERY's official website→PRODUCTS→Value line→AT32F4x; download and unzip BSP, and then get the “AT32F421_Firmware_Library_V2.x.x\utilities\at32f421_boot_memory_ap_demo”.

  • Page 22: Figure 31. Read Cortex Id

    Figure 32. Read PID and UID /* Get the base address of AT32 MCU PID/UID */ #define DEVICE_ID_ADDR1 0x1FFFF7F3 // Define Artery MCU part number, UID base address #define DEVICE_ID_ADDR2 0xE0042000 // Define MCU device number, PID base address /* Used to store ID */ uint8_t ID[5] = {0};...

  • Page 23: Faqs In Downloading/Compiling

     Please refer to FAQ0008_ J-Link cannot find IC SUPPORT→FAQ→FAQ0008). (ARTERY’s official  Please refer to FAQ0132_Add Artery MCU to J-Link website→ SUPPORT→FAQ→FAQ0132). Errors in program downloading Flash Download failed–“Cortex-M4” The following pop-up window appears in KEIL emulation or downloading: Figure 33.

  • Page 24: No Debug Unit Device Found

    Getting Started with AT32F421 No Debug Unit Device found  The download port is occupied. For example, ICP is connecting to the target device.  JTAG/SWD connection error or not connected. RDDI-DAP Error  Compiler optimization level is too high. For example, the default optimization level of Keil AC6 is –Oz, which should be modified to -O0/-O1.

  • Page 25: Security Library (Slib)

    IP-Codes (such as core algorithms) developed by software solution providers. The AT32F421 series is designed with a security library (sLib) to protect important IP-Codes against being changed or read by the end user’s program.

  • Page 26: Revision History

    Getting Started with AT32F421 Revision history Table 1. Document revision history Date Version Revision note 2021.12.29 2.0.0 Initial release Added description of BOOT1 and a prompt of high-level access protection cannot 2022.05.09 2.0.1 be disabled; optimized contents. 2022.07.15 2.0.2 Optimized contents. Updated 3 party programming tools and added description of development 2022.10.10...
  • Page 27 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previous representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third...

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