Table of Contents
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®
ARM
-based 32-bit Cortex
USB, 2 CANs, 12 timers, 3 ADCs, 13 communication interfaces
Feature
®
Core: ARM
32-bit Cortex
− 200 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
− Floating Point Unit (FPU)
− DSP instructions
Memories
− 64 to 256 KBytes of Flash memory
− sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
− SPIM interface: extra interfacing up to 16 Mbytes of
external SPI Flash (as instruction/data memory)
− Up to 64 KBytes of SRAM
Clock, Reset, and Power management
− 2.6 V ~ 3.6 V application suppy and I/Os
− Power on reset (POR)/ low voltage reset (LVR), and
power voltage monitor (PVM)
− 4 to 25 MHz crystal (HEXT)
− Internal 48 MHz factory-trimmed RC (accuracy 1%
at T
=25 °C, 2.5 % at T
A
automatic clock calibration (ACC)
− Internal 40 kHz RC oscillator (LICK)
− 32.768 kHz crystal oscillator (LEXT)
Low power consumption
− Sleep, Deepsleep, and Standby modes
− V
supply for RTC and 42 x 16-bit battery powered
BAT
registers (BPR)
2 x 12-bit 0.5 μs A/D converters, up to 16 channels
− Conversion range: 0 V to 3.6 V
− Dual sample and hold capability
− Temparature sensor
DMA: 12-channel DMA controller
− Peripherals supported: timers, ADCs, SDIOs,
I
2
Ss, SPIs, I
2
Cs, and USARTs
Debug mode
−
Serial wire debug
Up to 55 fast I/O Interfaces
2022.06.27
®
-M4F MCU+FPU with 64 to 25 KB Flash, sLib,
®
-M4F CPU with FPU
=-40 to +105 °C), with
A
(SWD) and JTAG
interface
AT32F413 Series Reference Manual
− 27/39/55 multifunctional and bidirectional I/Os, all
mappable to 16 external interrupt vectors and almost 5
V-tolerant
− All fast I/Os, control registers accessable with f
Up to 12 Timers
− Up to 5 x 16-bit timers + 2 x 32-bit timers; each with 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input.
− Up to 2 x 16-bit motor control PWM advanced timers
with dead-time generator and emergency brake
− 2 x Watchdog timers
− SysTick timer: 24-bit downcounter
Up to 13 Communication Interfaces
− Up to 2 x I
2
C interfaces (SMBus/PMBus)
− Up to 5 x USARTs (ISO7816 interface, LIN, IrDA
capability, and modem control)
− Up to 2 x SPIs (can be used as I
− Up to 2 x CAN interfaces (2.0B Active)
− USB2.0 full-speed interface supporting Crystal-less
− SDIO
CRC Calculation Unit
96-bit unique ID (UID)
Packages
− LQFP64 10x10 mm
− LQFP64 7x7 mm
− QFN48 6 x 6 mm
− QFN32 4x4 mm
List of Models
Internal Flash
AT32F413RCT7, AT32F413CCT7,
256 KBytes
AT32F413CCU7, AT32F413KCU7
AT32F413RBT7, AT32F413CBT7,
128 KBytes
AT32F413CBU7, AT32F413KBU7
64 KBytes
AT32F413C8T7
Page 1
speed
AHB
2
S)
Model
Rev 2.00
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Table of Contents
Related Manuals for ARTERY AT32F413RCT7
Summarization of Contents
Microcontroller Features
Core: ARM Cortex-M4F CPU with FPU
Details about the ARM Cortex-M4F CPU core, including FPU, frequency, MPU, and hardware division.
Memory Organization
Details on Flash memory size, sLib configuration, SPIM interface, and SRAM size.
Clock, Reset, and Power Management
Covers application supply voltage, POR/LVR, PVM, crystal oscillators, and RC oscillators.
Low Power Consumption Modes
Describes Sleep, Deepsleep, and Standby modes, and VBAT supply for RTC and BPR.
Analog-to-Digital Converters (ADCs)
Details on 2x 12-bit ADCs, conversion range, dual sample and hold, and temperature sensor.
DMA Controller
Information on the 12-channel DMA controller and supported peripherals.
Debug Interfaces
Details on Serial Wire Debug (SWD) and JTAG interface support.
General Purpose I/Os (GPIOs)
Covers multifunctional and bidirectional I/Os, mappable to interrupt vectors, and fast I/O features.
Timers
Details on 12 timers, including 16-bit, 32-bit, motor control PWM timers, and watchdog timers.
Communication Interfaces
Lists 13 interfaces including I2C, USART, SPI, CAN, and USBFS.
CRC Calculation Unit
Provides CRC calculation functionality.
Unique ID (UID)
Provides a 96-bit unique identifier for the device.
Available Packages
Lists available package options: LQFP64 (10x10mm), LQFP64 (7x7mm), QFN48, and QFN32.
Product Models
Lists microcontroller models based on internal Flash memory size.
System Architecture Overview
System Overview
Provides a general description of the AT32F413 series microcontrollers and their peripherals.
ARM Cortex-M4F Processor
Describes the Cortex-M4F processor features: low power, low gate count, low interrupt latency, and low-cost debug.
System Reset
System Reset Overview
Lists system reset sources: NRST pin, WDT, WWDT, CPU software, low-power management, POR, LVR, and Standby exit.
Battery Powered Domain Reset
Details reset sources for the battery powered domain: software reset via BPDRST and VDD/VBAT power on.
Memory Resources
Internal Memory Address Map
Shows the address mapping for program memory (Flash), data memory (SRAM), and peripheral registers.
Flash Memory Details
Flash Memory Organization (256KB)
Describes the main memory (Bank 1) and external memory organization for 256KB Flash.
Flash Memory Organization (128KB)
Describes the main memory (Bank 1) and external memory organization for 128KB Flash.
User System Data Area
Flash Memory Operations
How to program and manage Flash memory.
Flash Memory Unlock/Lock
Details the procedure to unlock and lock Flash memory blocks using KEY1 and KEY2.
Flash Memory Erase Operation
Explains page erase and mass erase operations, including procedures and status checks.
User System Data Area Operations
Flash Memory Protection
Security feature for flash memory.
Flash Memory Access Protection
Details access protection enabled by nFAP and FAP bytes, read-only access, and debug mode considerations.
Flash Memory Erase/Program Protection
Describes erase/program protection for 256K and 128K Flash, and protection against program crash.
Flash Memory Special Functions
Security Library Settings
Details the security library area, its protection by code, advantages, and programming requirements.
Flash Memory Registers
Flash Performance Select Register (FLASH_PSR)
Describes the reserved bits in the FLASH_PSR register.
General Purpose I/Os (GPIOs)
GPIO Introduction
Describes AT32F413 support for bidirectional I/O pins, grouping, and main features.
GPIO Function Overview
Details GPIO structure, input modes (floating, pull-up/down, analog) and output modes (push-pull, open-drain).
GPIO Registers
GPIO Configuration Register Low (GPIOx_CFGLR)
Describes bits for GPIOx function configuration (input/output) and mode configuration.
Multiplexed Function I/Os (IOMUX)
IOMUX Introduction
Introduces IOMUX support for bidirectional I/O pins, grouping, and main features.
IOMUX Function Overview
Details GPIO structure, input modes (floating, pull-up/down, analog) and output modes (push-pull, open-drain).
IOMUX Pin Mapping Priority
Hardware Preemption for IOMUX
Lists pins occupied by specific hardware functions regardless of GPIO configuration.
Debug Port Priority in IOMUX
Explains that programmed debug pins retain state during debugging, and remap configuration can be changed.
Other Peripheral Output Priority
Describes output priority rules: non-timer peripherals over timers, and overlapping outputs for non-timer peripherals.
IOMUX Registers
IOMUX Event Output Control Register (IOMUX_EVTOUT)
Describes bits for EVOEN, SELPORT, and SELPIN for event output configuration.
External Interrupt/Event Controller (EXINT)
EXINT Introduction
Introduces EXINT lines for generating interrupts or events via edge detection or software trigger.
EXINT Function Overview and Configuration
Describes EXINT lines, GPIO sources, edge detection modes, software trigger, and interrupt status.
EXINT Registers
EXINT Interrupt Enable Register (EXINT_INTEN)
Describes the INTENx bits for enabling or disabling interrupt requests on line x.
EXINT Event Enable Register (EXINT_EVTEN)
Describes the EVTENx bits for enabling or disabling event requests on line x.
EXINT Polarity Configuration Register 1 (EXINT_POLCFG1)
Describes the RPx bits for selecting rising edge to trigger an interrupt and event on line x.
EXINT Polarity Configuration Register 2 (EXINT_POLCFG2)
Describes the FPx bits for selecting falling edge to trigger an interrupt and event on line x.
DMA Controller (DMA)
DMA Controller Introduction
Introduces DMA controller for enhancing system performance and reducing interrupts via direct memory access.
DMA Controller Main Features
Lists features like AMBA compliance, support for 7 channels, transfer types, hardware handshake, and data transfer widths.
DMA Function Overview
DMA Channel Configuration
Details steps for configuring DMA: peripheral/memory addresses, data count, channel settings, and enabling transfer.
DMA Handshake Mechanism
Explains the handshake mechanism where peripherals send requests and DMA sends acknowledge signals.
DMA Arbiter
Describes the arbiter's role in restarting arbitration after data transfer and serving channels based on priority.
CRC Calculation Unit (CRC)
CRC Calculation Introduction
Introduces the CRC peripheral, following CRC32 standard, for checking data integrity.
CRC Registers
Lists CRC registers: CRC_DT, CRC_CDT, CRC_CTRL, and CRC_IDT.
CRC Data Register (CRC_DT)
Describes the DT bits used as input register for new data and for reading CRC calculation results.
Common Data Register (CRC_CDT)
Describes the CDT bits used to store 1-byte data temporarily.
I2C Interface
I2C Introduction
Introduces the I2C bus interface for microcontroller communication, supporting master/slave modes and speeds.
I2C Main Features
Lists features like master/slave modes, multi-master, address modes, DMA transfer, SMBus, and PMBus support.
I2C Function Overview
Describes the I2C bus, data/clock lines, speed modes, start/stop conditions, and data transmission.
I2C Interface Details
I2C Clock Configuration
Explains I2C clocking via APB1/APB2 and division using CLKFREQ[7:0] in I2C_CTRL2.
I2C Operation Modes
Describes master and slave modes, switching between them, and master/slave transmitter/receiver roles.
I2C Communication Process
Details master mode communication (start, address, Tx/Rx, stop) and slave mode communication (address match, Tx/Rx, stop).
I2C Address Control
Explains 7-bit and 10-bit addressing modes, and slave address modes (single/dual address).
I2C Registers
I2C Control Register 1 (I2C_CTRL1)
Describes bits for reset, SMBus alert, PEC transfer, master ACK control, acknowledge enable, GENSTOP, GENSTART, STRETCH, GCAEN, PECEN, ARPEN, SMBMODE, PERMODE, and I2CEN.
Universal synchronous/asynchronous receiver/transmitter (USART)
USART Introduction
Introduces USART for communication, supporting various configurations and protocols.
Full-duplex/half-duplex Selector
Enables USART to perform data exchanges in full-duplex or half-duplex mode.
Mode Selector
Allows USART to operate in different modes: NRZ, LIN, IrDA, Smartcard, RS-232, silent, synchronous.
Configuration Procedure
Details configuration steps for LIN, Smartcard, and Infrared modes.
DMA Transfer Introduction
Transmission using DMA
Explains the sequence for enabling transmit data buffer using DMA.
Reception using DMA
Explains the sequence for enabling receive data buffer using DMA.
Baud Rate Generation
Baud Rate Generation Introduction
Describes the baud rate generator using an internal counter based on PCLK.
Baud Rate Configuration
Explains programming the baud rate by setting system clocks and values in USART_BAUDR.
Transmitter
Transmitter Introduction
Details the TEN control bit, transmit data buffer (TDR), and shift register.
Transmitter Configuration
Guides on USART enable, duplex mode, mode selection, frame format, interrupts, DMA, and baud rate.
Receiver
Receiver Introduction
Details the REN control bit, baud rate generator, receive data buffer (RDR), and receive shift register.
Receiver Configuration
Outlines configuration steps: USART enable, duplex mode, mode, frame format, interrupts, DMA, baud rate, and receiver enable.
Character Reception
Explains RDBF bit status, interrupts, error flags, and RDBF clearing.
Break Frame Reception
Describes break frame handling in non-LIN and LIN modes.
Idle Frame Reception
Describes idle frame reception handling.
Start Bit and Noise Detection
Start Bit and Noise Detection Data Sampling
Details data sampling over start bit and noise detection.
USART Registers
Status Register (USART_STS)
Describes bits for CTS flag (CTSCF), break frame (BFF), transmit data buffer empty (TDBE), transmit data complete (TDC), receive data buffer full (RDBF), idle flag (IDLEF), receiver overflow error (ROERR), noise error (NERR), framing error (FERR), and parity error (PERR).
Data Register (USART_DT)
Describes the Data value register.
Baud Rate Register (USART_BAUDR)
Describes the divider bits for baud rate generation.
Control Register 1 (USART_CTRL1)
Describes bits for USART enable (UEN), data bit number (DBN), wakeup mode (WUM), parity enable (PEN), parity selection (PSEL), PERR interrupt enable (PERRIEN), TDBE interrupt enable (TDBEIEN), TDC interrupt enable (TDCIEN), RDBF interrupt enable (RDBFIEN), IDLE interrupt enable (IDLEIEN), transmitter enable (TEN), receiver enable (REN), receiver mute (RM), and send break frame (SBF).
Serial Peripheral Interface (SPI)
SPI Introduction
Introduces the SPI interface, supporting SPI and I2S protocols.
SPI Description
Describes SPI configuration as host/slave, duplex/half-duplex modes, DMA transfer, and CRC function.
SPI IO Connection
SPI Two-Wire Unidirectional Full-Duplex Connection
Details the SPI connection for two-wire unidirectional full-duplex mode.
Single-Wire Unidirectional Receive-Only Mode
Describes SPI operation in single-wire unidirectional receive-only mode.
Chip Select Controller
CS Hardware Configuration Procedure
Details CS hardware control in master mode (output/input).
CS Software Configuration Procedure
Details CS software control in master and slave modes.
DMA Transfer
Transmission with DMA
Describes DMA transfer for SPI transmission.
Reception with DMA
Describes DMA transfer for SPI reception.
Transmission using CPU
Describes data transmission using CPU.
Reception using CPU
Describes data reception using CPU.
Transmitter
Transmitter Configuration Procedure
Guides on configuring duplex mode, chip select, SPI_SCK, CRC, DMA, frame format, and SPI enable.
Receiver
Receiver Configuration Procedure
Guides on configuring duplex mode, chip select, SPI_SCK, DMA, and frame format.
I2S Functional Description
I2S Introduction
Introduces the I2S interface, supporting master/slave reception/transmission and four audio protocols.
Operation Mode Selector
Details operation modes for I2S: slave transmit, slave receive, master transmit, and master receive.
SPI Registers
SPI Control Register 1 (SPI_CTRL1)
Describes bits for SLBEN, SLBTD, CCEN, NTC, FBN, ORA, SWCSEN, SWCSIL, LTF, SPIEN, MDIV, MSTEN, CLKPOL, CLKPHA.
SPI Control Register 2 (SPI_CTRL2)
Describes bits for MDIV, TDBEIE, RDBFIE, ERRIE for SPI control.
SPI Status Register (SPI_STS)
Describes bits for Busy flag (BF), overflow error (ROERR), mode error (MMERR), CRC error (CCERR), underload error (TUERR), audio channel state (ACS), TDBE, and RDBF.
SPI Data Register (SPI_DT)
Describes the Data value register.
SPICRC Register (SPI_CPOLY)
Describes the CPOLY bits for CRC polynomial configuration.
SPIRxCRC Register (SPI_RCRC)
Describes the RCRC bits for storing computed CRC value for received data.
SPITxCRC Register (SPI_TCRC)
Describes the TCRC bits for storing computed CRC value for transmitted data.
SPI_I2S Register (SPI_I2SCTRL)
Describes bits for I2S mode select (I2SMSEL), I2S enable (I2SEN), operation mode select (OPERSEL), and PCM frame synchronization (PCMFSSEL).
SPI_I2S Prescaler Register (SPI_I2SCLKP)
Describes bits for I2SMCLKOE, I2SODD, I2SDIV, and I2SCBN for clock configuration.
Timer
TMR Functional Comparison
Compares functions of Advanced control, General purpose, and TMR10/11 timers.
General-purpose Timer (TMR2 to TMR5)
Introduces TMR2 to TMR5 timers, their modes, capture/compare registers, and channels.
TMRx Functional Overview
Count Clock
Explains count clock sources: internal, external clock modes A/B, and internal trigger input.
Counting Mode
Upcounting Mode
Describes counter behavior in upcounting mode, including overflow events.
TMR Input Function
Input Mode
Details input mode configuration, including trigger signal detection and capture compare interrupt flag.
Timer Input XOR function
Explains using XOR gate for Hall sensors to calculate position and speed.
TMR Synchronization
Slave mode: Reset mode
Describes counter reset by trigger signal and overflow event generation.
Slave mode: Suspend mode
Explains counter control by trigger input, starting when high and stopping when low.
Slave mode: Trigger mode
Describes counter start on rising edge of selected trigger input.
TMRx Registers
TMR1 and TMR8 Register Map
Lists registers for TMR1 and TMR8, including CTRL1, CTRL2, STCTRL, IDEN, ISTS, SWEVT, CM1, CM2, CCTRL, CVAL, DIV, PR, C1DT, C2DT, C3DT, C4DT, BRK, DMACTRL, DMADT.
General-purpose Timer (TMR9 to TMR11)
TMRx Introduction
Introduces TMR9 to TMR11 timers, supporting upcounting mode and synchronization.
TMRx Main Features
Lists main functions for TMR9/TMR12 and TMR10/TMR11.
TMR9 Main Features
Details TMR9 functions: counter clock source, up counter, channels, synchronization, and interrupts.
TMR10 and TMR11 Main Features
Details TMR10/TMR11 functions: counter clock source, up counter, channels, synchronization, and interrupts.
TMRx Functional Overview
Count Clock
Explains count clock sources for general-purpose timers: internal, external clock mode A, and internal trigger input.
Counting Mode
Upcounting Mode
Describes counter behavior in upcounting mode, including overflow events.
TMR Input Function
Input Mode
Details input mode configuration, including trigger signal detection and capture compare interrupt flag.
Timer Input XOR function
Explains using XOR gate for Hall sensors to calculate position and speed.
TMR Synchronization
Slave mode: Reset mode
Describes counter reset by trigger signal and overflow event generation.
Slave mode: Suspend mode
Explains counter control by trigger input, starting when high and stopping when low.
Slave mode: Trigger mode
Describes counter start on rising edge of selected trigger input.
TMR9 Registers
Control Register 1 (TMR9_CTRL1)
Describes bits for clock divider, period buffer enable, one cycle mode, overflow event source, overflow event enable, and TMR enable.
Slave Timer Control Register (TMR9_STCTRL)
Describes bits for external signal polarity, external clock mode B, external signal divide, external signal filter, subordinate TMR synchronization, input selection, and subordinate TMR mode selection.
DMA/interrupt Enable Register (TMR9_IDEN)
Describes bits for trigger DMA, HALL DMA, channel DMA, overflow DMA request enables, and interrupt enables.
Interrupt Status Register (TMR9_ISTS)
Describes bits for channel recapture flags, trigger interrupt flag, HALL interrupt flag, channel interrupt flags, and overflow interrupt flag.
Software Event Register (TMR9_SWEVT)
Describes bits for trigger event, channel events, and overflow event triggered by software.
Channel Mode Register 1 (TMR9_CM1)
Describes bits for channel output control, buffer enable, output enable immediately, channel configuration, and output buffer enable.
TMR1 and TMR8 Registers
TMR1 and TMR8 Control Register 1 (TMRx_CTRL1)
Describes bits for clock division, period buffer enable, two-way counting mode, count direction, one cycle mode, and overflow event source/enable.
TMR1 and TMR8 Control Register 2 (TMRx_CTRL2)
Describes bits for idle output state, complementary idle output state, enable, C1IN selection, master timer output selection, DMA request source, and channel control bit flash selection.
TMR1 and TMR8 Slave Timer Control Register (TMRx_STCTRL)
Describes bits for external signal polarity, external clock mode B, external signal divide, external signal filter, subordinate TMR synchronization, input selection, and subordinate TMR mode selection.
TMR1 and TMR8 DMA/interrupt Enable Register (TMRx_IDEN)
Describes bits for trigger DMA, HALL DMA, channel DMA request enables, and interrupt enables.
TMR1 and TMR8 Interrupt Status Register (TMRx_ISTS)
Describes bits for channel recapture flags, break interrupt flag, trigger interrupt flag, HALL interrupt flag, channel interrupt flags, and overflow interrupt flag.
Software Event Register (TMRx_SWEVT)
Describes bits for break event, trigger event, HALL event, channel events, and overflow event triggered by software.
Channel Mode Register 1 (TMRx_CM1)
Describes bits for channel output switch enable, control, buffer enable, output enable immediately, and channel configuration.
Channel Mode Register 2 (TMRx_CM2)
Describes bits for channel configuration (input/output) and input pin selection.
Channel Control Register (TMRx_CCTRL)
Describes bits for channel polarity, complementary polarity, and channel enable.
Counter Value (TMRx_CVAL)
Describes the counter value register.
Division Value (TMRx_DIV)
Describes the divider value register for counter clock frequency.
Period Register (TMRx_PR)
Describes the period value register for the TMRx counter.
Channel 1 Data Register (TMRx_C1DT)
Describes the Channel 1 data register for input and output modes.
Channel 2 Data Register (TMRx_C2DT)
Describes the Channel 2 data register for input and output modes.
Channel 3 Data Register (TMRx_C3DT)
Describes the Channel 3 data register for input and output modes.
Channel 4 Data Register (TMRx_C4DT)
Describes the Channel 4 data register for input and output modes.
TMR1 and TMR8 Break Register (TMRx_BRK)
Describes bits for output enable, automatic output enable, break input validity, and break enable.
Window Watchdog Timer (WWDT)
WWDT Introduction
Introduces the window watchdog downcounter for preventing system reset.
WWDT Main Features
Lists features: 7-bit downcounter, clocking by LICK, and system reset on counter reaching 0.
WWDT Functional Overview
Explains system reset conditions and counter reloading requirements.
WWDT Registers
Configuration Register (WWDT_CFG)
Describes bits for reload counter interrupt, clock division, and window value.
Status Register (WWDT_STS)
Describes the RLDF bit for reload counter interrupt flag.
Watchdog Timer (WDT)
WDT Introduction
Introduces WDT driven by LICK clock, suited for low timing accuracy applications.
WDT Main Features
Lists features: 12-bit downcounter, clocked by LICK, and system reset on counter reaching 0.
WDT Functional Overview
Explains WDT enabling via software/hardware, reset conditions, write protection, and clock source.
WDT Registers
Command Register (WDT_CMD)
Describes command register for reload counter, unlock, and enable operations.
Divider Register (WDT_DIV)
Details the clock division value for LICK clock.
Reload Register (WDT_RLD)
Describes the reload value register, which is write-protected.
Status Register (WDT_STS)
Describes RLDF and DIVF flags for reload value and division value update completion.
Real-time Clock (RTC)
RTC Introduction
Introduces the RTC for calendar clock function, with a 32-bit incremental counter.
RTC Main Features
Lists features: 20-bit prescaler, 32-bit counter, RTC clock sources, and interrupts.
RTC Structure
Describes RTC structure consisting of APB1 interface and RTC counter logic.
RTC Functional Overview
Explains configuring RTC registers after power-on, and the procedure for configuring DIV, CNT, and ALA registers.
RTC Registers
RTC Control Register High (RTC_CTRLH)
Describes bits for overflow interrupt enable (OVFIEN), time alarm interrupt enable (TAIEN), and time second interrupt enable (TSIEN).
RTC Control Register Low (RTC_CTRLL)
Describes bits for RTC configuration finish (CFGF), configuration enable (CFGEN), update finish flag (UPDF), overflow flag (OVFF), time alarm flag (TAF), and time second flag (TSF).
RTC Divider Register (RTC_DIVH/RTC_DIVL)
Describes the DIV bits for defining counter clock frequency.
Battery Powered Registers (BPR)
BPR Introduction
Introduces battery powered registers located in the battery powered domain.
BPR Main Features
Lists features: forty-two 16-bit registers, reset at tamper event, and PC13 pin multiplexed function.
BPR Functional Overview
Explains enabling access to BPR registers and tamper detection function.
BPR Registers
Lists BPR registers: BPR_DT1 to BPR_DT13, BPR_RTCCAL, BPR_CTRL, BPR_CTRLSTS.
Analog-to-Digital Converter (ADC)
ADC Introduction
Introduces the ADC peripheral, converting analog to digital signals.
ADC Main Features
Lists analog part features (resolution, calibration, conversion time) and digital control features.
ADC Structure
Shows the block diagram of ADC1 and differences between ADC1 and ADC2.
ADC Functional Overview
Channel Management
Details analog signal channel inputs for ADCs, including external and internal sources.
Internal Temperature Sensor
Describes the temperature sensor connected to ADC1_IN16 and how to obtain temperature.
Internal Reference Voltage
Details the internal reference voltage connected to ADC1_IN17.
Channel Conversion
Explains conversion groups (ordinary, preempted), priority, and sequence programming.
ADC Operation Process
Shows the basic operation process: power-on, calibration, trigger, conversion, and read data.
Power-on and Calibration
Details enabling ADC clocks, programming ADCCLK, supplying ADC, and calibration procedure.
Trigger
Describes ADC triggers: ordinary, preempted, software, timer, and pin triggers.
Sampling and Conversion Sequence
Explains configuring sampling period and calculating conversion time.
Conversion Sequence Management
Describes sequence modes: sequence mode, automatic preempted group conversion, repetition mode, and partition mode.
Sequence Mode
Explains enabling sequence mode via SQEN and configuring channels using ADC_OSQx and ADC_PSQ registers.
Automatic Preempted Group Conversion Mode
Details enabling automatic preempted group conversion via PCAUTOEN bit.
Repetition Mode
Explains enabling repetition mode via RPEN bit for repeated conversions.
Partition Mode
Describes enabling partition mode for ordinary and preempted groups.
Data Management
Data Alignment
Details data alignment (right/left) and offset adjustment for preempted group data.
Data Read
Explains reading converted data from ADC_ODT and ADC_PDTx registers.
Master/Slave Mode
Data Management in Master/Slave Mode
Explains storing ordinary channel data in ADC_ODT and using OCDMAEN for DMA requests.
Regular Simultaneous Mode
Describes selecting regular group simultaneous conversion mode via MSSEL bit.
Interleaved Trigger Mode of Preempted Group
Explains selecting interleaved preempted-group trigger mode via MSSEL bit.
CAN
CAN Introduction
Introduces CAN protocol for real-time data communication.
CAN Main Features
Lists features like baud rates, time-triggered communication, interrupt handling, and transmission/reception capabilities.
Baud Rate Configuration
Explains nominal bit time components: Synchronization, Bit Segment 1, and Bit Segment 2.
CAN Registers
CAN Master Control Register (CAN_MCTRL)
Describes bits for PTD, SPRST, TTCEN, AEBOEN, AEDEN, PRSFEN, MDRSEL, MMSSR, DZEN, and FZEN.
CAN Master Status Register (CAN_MSTS)
Describes bits for RX pin level, sample level, receive/transmit status, error flags, and mode control.
CAN Transmit Status Register (CAN_TSTS)
Describes bits indicating mailbox priority, empty status, transmission success, and cancellation.
CAN Receive FIFO 0 Register (CAN_RF0)
Describes bits for FIFO release, overflow flag, full flag, and message count.
CAN Receive FIFO 1 Register (CAN_RF1)
Describes bits for FIFO release, overflow flag, full flag, and message count.
CAN Interrupt Enable Register (CAN_INTEN)
Describes bits for enabling interrupts related to doze mode, errors, FIFO status, and transmit mailbox.
CAN Error Status Register (CAN_ESTS)
Describes REC, TEC, error type record (ETR), bus-off flag (BOF), error passive flag (EPF), and error active flag (EAF).
CAN Bit Timing Register (CAN_BTMG)
Describes bits for Listen-Only mode, Loop back mode, Resynchronization width, Bit time segment 2, Bit time segment 1, and Baud rate division.
CAN Mailbox Registers
Describes transmit and receive mailbox registers.
CAN Filter Registers
Describes CAN filter configuration registers.
CAN Filter Control Register (CAN_FCTRL)
Describes the FCS bit for enabling filter banks.
CAN Filter Mode Configuration Register (CAN_FMCFG)
Describes the FMSELx bit for selecting identifier mask or list mode.
CAN Filter Bit Width Configuration Register (CAN_FBWCFG)
Describes the FBWSELx bit for configuring filter bit width.
CAN Filter FIFO Association Register (CAN_FRF)
Describes the FRFSELx bit for associating filter banks with FIFO0 or FIFO1.
CAN Filter Activation Control Register (CAN_FACFG)
Describes the FAENx bit for enabling filter banks.
CAN Filter Bank i Filter Bit Register (CAN_FiFBx)
Describes the FFDB bits for filter configuration in identifier list and mask modes.
Universal Serial Bus Full-Speed Device Interface (USBFS)
USBFS Introduction
Introduces the USBFS implementing USB2.0 full-speed protocols, supporting various transfers and endpoints.
USBFS Clock and Pin Configuration
Details USB clock sources (HICK 48M, PLL) and pin configuration for DP/DM and SOF.
USBFS Functional Description
Explains USB initialization steps: clearing registers, enabling core, configuring interrupts, and enabling USB PHY.
USB Buffer
Buffer Size Configuration Table
Lists buffer mapping address and size based on working conditions (USBBUFS, CAN status).
Double-buffered Endpoints
Bulk Transfer Endpoints
Enables double-buffered feature for bulk transfer.
Isochronous Transfer Endpoints
Enables double-buffered feature for isochronous transfer.
USBFS Registers
USBFS Endpoint n Register (USBFS_EPTn)
Describes Rx transaction completion (RXTC), Rx data toggle (RXDTS), Rx status (RXSTS), setup transaction completion (SETUPTC), and transfer type (TRANS_TYPE).
USBFS Control Register (USBFS_CTRL)
Describes bits for transmission complete interrupt (TCIEN), FIFO overrun (UCFORIEN), bus error (BEIEN), wakeup (WKIEN), suspend (SPIEN), reset (RSTIEN), SOF (SOFIEN), and lost SOF (LSOFIEN) interrupt enables.
USBFS Interrupt Status Register (USBFS_INTSTS)
Describes bits for transaction completed (TC), FIFO overrun (UCFOR), bus error (BE), wakeup (WK), bus suspend (SP), bus reset (RST), start of frame (SOF), and lost start of frame (LSOF).
USBFS SOF Frame Number Register (USBFS_SOFRNUM)
Describes bits for D+ status (DPSTS), D- status (DMSTS), Connect Locked (CLCK), and Lost SOF number (LSOFNUM).
USBFS Device Address Register (USBFS_DEVADDR)
Details the CEN bit for USB Core Enable and ADDR bits for host assigned device address.
USBFS Buffer Table Address Register (USBFS_BUFTBL)
Describes BTADDR bits for endpoint buffer table start address.
USBFS CFG Control Register (USBFS_CFG)
Describes PUO bit for DP pull-up control and SOFOUTEN bit for SOF output enable.
HICK Auto Clock Calibration (ACC)
ACC Introduction
Introduces HICK auto clock calibration using USB SOF signal for 48MHz clock.
Main Features
Lists features: programmable center frequency, boundary frequency, precision, status flags, error flags, and calibration modes.
Interrupt Requests
Lists ACC interrupt events: Calibration ready and Reference signal lost.
Functional Description
HICK Auto Clock Calibration (HICK ACC) Description
Explains HICK ACC for HICK clock calibration using USB SOF, achieving ±0.25% precision.
Principle
USB_SOF Period Signal
Highlights the importance of accurate USB_SOF period signal for auto calibration.
Cross-return Algorithm
Explains calculating calibration value closest to the theoretical value for frequency adjustment.
Register Description
Status Register (ACC_STS)
Describes RSLOST flag for reference signal loss.
Control Register 1 (ACC_CTRL1)
Describes bits for STEP, CALRDYIEN, EIEN, ENTRIM, and CALON for calibration control.
Compare Value 1 (ACC_C1)
Describes C1 bits as the lower boundary for triggering calibration.
Compare Value 2 (ACC_C2)
Describes C2 bits as the center point for calculating calibration value.
Compare Value 3 (ACC_C3)
Describes C3 bits as the upper boundary for triggering calibration.
SDIO Interface
SDIO Introduction
Introduces SDIO interface for MMC, SD memory cards, and SDIO cards.
SDIO Main Features
Lists features like compatibility with SD/MMC specs, DMA transfer, speed, and interrupt requests.
SDIO Main Features
Card Functional Description
Describes communication control via commands and responses, and card operational modes.
Card Identification Mode
Details card identification process: reset, voltage validation, and RCA setting.
Data Transfer Mode
Explains host entering data transfer mode, CMD9 for CSD, and data block/stream transfer.
Protection Management
Mechanical Write Protect Switch
Describes the mechanical sliding switch for write protection.
Internal Card Write Protection
Explains permanent or temporary write protection via CSD bits.
Commands and Responses
Commands
Lists command types: Broadcast, Broadcast with response, Addressible, Addressible data transfer.
Command Description
Explains general commands (GEN_CMD) and application-specific commands (ACMD).
Data Block Read Commands
Lists commands for reading data blocks: CMD16, CMD17, CMD18.
Data Stream Read/Write Commands
Lists commands for data stream transfer: CMD11, CMD20.
Data Block Write Commands
Lists commands for writing data blocks: CMD16, CMD23, CMD24, CMD25, CMD26, CMD27.
Block-based Write Protect Commands
Lists commands for setting and clearing write protection: CMD28, CMD29, CMD30.
Erase Commands
Lists erase commands: CMD35, CMD36, CMD38.
I/O Mode Commands
Lists I/O mode commands: CMD39, CMD40.
Card Lock Commands
Lists card lock commands: CMD42.
Response Formats
R1 (Normal Response Command)
Details the R1 response format, including code length and field descriptions.
R1b
Describes R1b response, same as R1 but with an optional busy signal.
R2 (CID & CSD registers)
Details the R2 response format for CID and CSD registers.
R3
Details the R3 response format for OCR register.
R4 (Fast I/O)
Details the R4 response format for Fast I/O.
R4b
Details the R4b response for SD I/O card.
SDIO Functional Description
SDIO Adapter
Describes the SDIO adapter block, including control unit, command path, and data path.
SDIO Pin Definitions
Lists SDIO pin definitions for clock, command, and data bus.
Control Unit
Describes the control unit's power and clock management subunits.
Data Channel State Machine (DCSM)
Send Mode
Describes DCSM states in send mode: Idle, Wait_S, and Send.
Data BUF
Transmit BUF
Details the transmit BUF for data output and its sequence.
Receive BUF
Details the receive BUF for data input and its sequence.
SDIO AHB Interface
SDIO Interrupts
Explains SDIO interrupt feature for signaling host or MultiMedia card.
SDIO Registers
SDIO Power Control Register (SDIO_PWRCTRL)
Describes PS bits for defining card clock power-off/on state.
SDIO Clock Control Register (SDIO_CLKCTRL)
Describes bits for clock division, hardware flow control, edge selection, bus width, clock divider bypass, power saving, and clock output enable.
SDIO Argument Register (SDIO_ARG)
Describes the ARGU bits for the command argument.
SDIO Command Register (SDIO_CMD)
Describes bits for IOSUSP, CCSMEN, PNDWT, INTWT, RSPWT, and CMDIDX.
SDIO Response 1..4 Register (SDIO_RSPx)
Describes CARDSTS bits for card status.
SDIO Data Timer Register (SDIO_DTTMR)
Contains the data timeout period in card bus clock cycles.
SDIO Data Length Register (SDIO_DTLEN)
Contains the number of data bytes to be transferred.
SDIO Data Control Register (SDIO_DTCTRL)
Controls the data channel state machine (DCSM).
SDIO Data Counter Register (SDIO_DTCNTR)
Contains the number of words to be written to or read from the BUF.
SDIO Status Register (SDIO_STS)
Contains static and dynamic flags indicating SDIO operation status.
SDIO Clear Interrupt Register (SDIO_INTCLR)
Clears corresponding bits in the SDIO_STS register when writing 1.
SDIO Interrupt Mask Register (SDIO_INTEN)
Determines which status bit generates an interrupt by setting the corresponding bit.
Debug (DEBUG)
Debug Introduction
Introduces Cortex-M4F debugging features: halt, single step, and trace function.
Debug and Trace
Describes supporting debugging for peripherals and low-power mode debugging.
I/O Pin Control
Explains SWJ-DP support and releasing I/O pins for general use.
DEBUG Registers
DEBUG Device ID (DEBUG_IDCODE)
Provides MCU ID code for revision identification, accessible via JTAG or SWD port.
DEBUG Control Register (DEBUG_CTRL)
Controls pause behavior for TMRs, CAN, and I2C during debug mode.
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