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ARM
®
-based 32-bit Cortex
1 ADC, 18 communication interfaces (CAN and OTGFS)
Core: ARM®32-bit Cortex
− 150 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
− Floating Point Unit (FPU)
− DSP instructions
Memories
− 64 to 256 Kbytes of Flash memory
− 20 Kbytes of boot memory used as a Bootloader or
as a general instruction/data memory (one-time
configured)
− sLib: configurable part of main Flash as a library
area with code executable but secured, non-
readable
− Up to 48 Kbytes of SRAM
− External memory controller (XMC) with 16-bit data
bus supporting multiplexed PSRAM and NOR
memories
XMC as LCD parallel interface, 8080/6800 modes
Power control (PWC)
− 2.4 V to 3.6 V power supply
− Power-on reset (POR)/low-voltage reset (LVR), and
power voltage monitor (PVM)
− Low-power modes: Sleep, Deepsleep and Standby
modes
− 20 x 32-bit battery powered registers (ERTC_BPR)
Clock and reset management (CRM)
− 4 to 25 MHz crystal (HEXT)
− 48 MHz internal factory-trimmed HICK (± 1% at
TA=25 ° C, ± 2.5% at TA=-40 to +105 ° C), with
automatic clock calibration (ACC)
− 32 kHz crystal (LEXT)
− Low speed internal clock (LICK)
Analog
− 1 x 12-bit 5.33 MSPS A/D converter, up to 24 input
channels, 12/10/8/6-bit configurable resolution;
hardware over-sampling up to equivalent 16-bit
resolution
− Temperature sensor (V
(V
)
INTR
− 2 x 12-bit D/A converters
DMA: 14-channel DMA controller
Up to 87 fast GPIOs
− All mappable on 16 external interrupts (EXINT)
− Almost 5 V-tolerant
Up to 15 timers (TMR)
− 1 x 16-bit 7-channel advanced timer with dead-time
generator and emergency break
− Up to 8 x16-bit and 1x 32-bit general-purpose
2023.04.25
AT32F423 Series Reference Manual
TM
-M4F MCU, 64 to 256 KB Flash, sLib, 15 timers,
TM
-M4F CPU with FPU
), internal reference voltage
TS
timers, each with up to 4 IC/OC/PWM or pulse
counter and quadrature (incremental) encoder input
− 2 x 16-bit basic timers
− 2 x watchdog timers (general WDT and windowed
WWDT)
− SysTick timer: a 24-bit downcounter
ERTC: enhanced RTC with auto wakeup, alarm,
subsecond accuracy, hardware calendar and
calibration feature
Up to 18 communication interfaces
− Up to 3 x I
2
C interfaces (SMBus/PMBus)
− Up to 3 x SPIs (36 Mbit/s), all with multiplexed half-
2
duplex I
S; 2 x half-duplex I
duplex support
− Up to 8 x USARTs support master synchronization
SPI and modem control, ISO7816 interface, LIN,
IrDA, and RS485 drive enable, TX/RX swap
− Up to 2 x CAN (2.0B Active), each with dedicated
256KB buffer
− USB OTG full speed controller with on-chip PHY,
dedicated 1280KB buffer, supporting crystal-less in
device mode
− Infrared transmitter (IRTMR)
CRC calculation unit
96-bit ID (UID)
Debug mode
− SWD and JTAG interfaces
Temperature range: -40 to +105℃
Packaging
− LQFP100 14 x 14 mm LQFP64 10 x 10 mm
LQFP64 7 x 7 mm
QFN48 6 x 6 mm
QFN32 4 x 4 mm
List of models
Internal Flash
64 Kbytes
128 Kbytes
256 Kbytes
Page 1
2
S combined for full-
LQFP48 7 x 7 mm
QFN36 6 x 6 mm
Model
AT32F423K8U7-4 AT32F423T8U7
AT32F423C8U7 AT32F423C8T7
AT32F423R8T7-7 AT32F423R8T7
AT32F423V8T7
AT32F423KBU7-4 AT32F423TBU7
AT32F423CBU7 AT32F423CBT7
AT32F423RBT7-7 AT32F423RBT7
AT32F423VBT7
AT32F423KCU7-4 AT32F423TCU7
AT32F423CCU7 AT32F423CCT7
AT32F423RCT7-7 AT32F423RCT7
AT32F423VCT7
Rev 2.01
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Related Manuals for ARTERY AT32F423 Series
Summary of Contents for ARTERY AT32F423 Series
- Page 1 AT32F423 Series Reference Manual ® -based 32-bit Cortex -M4F MCU, 64 to 256 KB Flash, sLib, 15 timers, 1 ADC, 18 communication interfaces (CAN and OTGFS) Core: ARM®32-bit Cortex -M4F CPU with FPU timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input −...
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Page 2: Table Of Contents
AT32F423 Series Reference Manual Contents System architecture ..............34 System overview ................35 1.1.1 ARM Cortex -M4F processor ............35 1.1.2 Bit band ..................35 1.1.3 Interrupt and exception vectors ............ 38 1.1.4 System Tick (SysTick) ..............41 1.1.5 Reset ..................41 List of abbreviations for registers .......... -
Page 3: Ahb Peripheral Clock Enable In Low Power Mode Register
AT32F423 Series Reference Manual 4.1.2 System clock ................58 4.1.3 Peripheral clock ................58 4.1.4 Clock fail detector ............... 58 4.1.5 Auto step-by-step system clock switch .......... 58 4.1.6 Internal clock output ..............58 4.1.7 Interrupts ..................59 Reset ..................59 4.2.1 System reset ................ - Page 4 AT32F423 Series Reference Manual 4.3.21 Battery powered domain control register (CRM_BPDC) ....74 4.3.22 Control/status register (CRM_CTRLSTS) ........75 4.3.23 Additional register 1 (CRM_MISC1) ..........76 4.3.24 Additional register 2 (CRM_MISC2) ..........77 Flash memory controller (FLASH) ..........78 FLASH introduction ..............78 Flash memory operation ...............
- Page 5 AT32F423 Series Reference Manual 5.8.8 Erase/program protection status register (FLASH_EPPS) ....92 5.8.9 Flash security library status register 0 (SL IB_STS0) ...... 93 5.8.10 Flash security library status register 1 (SLIB_STS1) ...... 93 5.8.11 Security library password clear register (SLIB_PWD_CLR) .... 94 5.8.12 Security library additional status register (SLIB_MISC_STS) ..
- Page 6 AT32F423 Series Reference Manual 6.3.5 GPIO input data register (GPIOx_IDT) (x=A..F) ......112 6.3.6 GPIO output data register (GPIOx_ODT) (x=A..F) ......113 6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A.. F) ......113 6.3.8 GPIO write protection register (GPIOx_WPR) (x=A..F) ....113 6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..F) ...
- Page 7 AT32F423 Series Reference Manual Function overview ..............123 9.3.1 DMA configuration ..............123 9.3.2 Handshake mechanism ............... 124 9.3.3 Arbiter ..................124 9.3.4 Programmable data transfer width ..........124 9.3.5 Errors ..................125 9.3.6 Interrupts ................... 126 DMA multiplexer (DMAMUX) ............126 9.4.1 DMAMUX function overview ............
- Page 8 AT32F423 Series Reference Manual C interface ................141 11.1 I C instruction ................141 11.2 I C main features ............... 141 11.3 I C function overview ..............141 11.4 I C interface ................142 11.4.1 I C timing control ............... 144 11.4.2 Data transfer management ............
- Page 9 AT32F423 Series Reference Manual 12.3.1 Introduction................176 12.3.2 Configuration procedure ............. 176 12.4 USART frame format and configuration ........179 12.5 DMA transfer introduction ............181 12.5.1 Transmission using DMA ............181 12.5.2 Reception using DMA ..............182 12.6 Baud rate generation ..............182 12.6.1 Introduction................
- Page 10 AT32F423 Series Reference Manual 13.2.1 SPI description ................195 13.2.2 Full-duplex/half-duplex selector ..........196 13.2.3 Chip select controller ..............198 13.2.4 SPI_SCK controller ..............198 13.2.5 CRC ..................199 13.2.6 DMA transfer ................200 13.2.7 TI mode ..................200 13.2.8 Transmitter ................201 13.2.9 Receiver ..................
- Page 11 AT32F423 Series Reference Manual Timer ..................219 14.1 Basic timer (TMR6 and TMR7) ............ 220 14.1.1 TMR6 and TMR7 introduction ............220 14.1.2 TMR6 and TMR7 main features ........... 220 14.1.3 TMR6 and TMR7 function overview ..........220 14.1.3.1 Counting clock ..............220 14.1.3.2 Counting mode ..............
- Page 12 AT32F423 Series Reference Manual 14.2.4.9 Channel control register (TMRx_CCTRL) ........ 248 14.2.4.10 Counter value (TMRx_CVAL) ..........249 14.2.4.11 Frequency division value (TMRx_DIV) ........ 249 14.2.4.12 Period register (TMRx_PR) ..........249 14.2.4.13 Channel 1 data register (TMRx_C1DT) ....... 249 14.2.4.14 Channel 2 data register (TMRx_C2DT) ....... 251 14.2.4.15...
- Page 13 AT32F423 Series Reference Manual 14.3.4.16 TMR9 and TMR12 DMA control register (TMRx_DMACTRL) .. 278 14.3.4.17 TMR9 and TMR12 DMA data register (TMRx_DMADT) ..278 14.4 General-purpose timer (TMR10/11/13/14) ........279 14.4.1 TMRx introduction ..............279 14.4.2 TMRx main features ..............279 14.4.3 TMRx functional overview ............
- Page 14 AT32F423 Series Reference Manual 14.5.3.5 TMR break function ............... 313 14.5.3.6 TMR synchronization ............. 314 14.5.3.7 Debug mode ................. 316 14.5.4 TMR1 registers ................316 14.5.4.1 TMR1 control register1 (TMR1_CTRL1) ........316 14.5.4.2 TMR1 control register2 (TMR1_CTRL2) ........317 14.5.4.3 TMR1 slave timer control register (TMR1_STCTRL) ....318 14.5.4.4 TMR1 DMA/interrupt enable register (TMR1_IDEN) ....
- Page 15 AT32F423 Series Reference Manual Watchdog timer (WDT) ..............334 16.1 WDT introduction ............... 334 16.2 WDT main features ..............334 16.3 WDT functional overview ............334 16.4 Debug mode ................335 16.5 WDT registers ................335 16.5.1 Command register (WDT_CMD) ..........336 16.5.2 Divider register (WDT_DIV) ............
- Page 16 AT32F423 Series Reference Manual 17.4.9 ERTC write protection register (ERTC_WP) ......... 350 17.4.10 ERTC subsecond register (ERTC_SBS) ........350 17.4.11 ERTC time adjustment register (ERTC_TADJ) ......350 17.4.12 ERTC time stamp time register (ERTC_TSTM) ......350 17.4.13 ERTC time stamp date register (ERTC_TSDT) ......351 17.4.14 ERTC time stamp subsecond register (ERTC_TSSBS) ....
- Page 17 AT32F423 Series Reference Manual 18.4.7 Voltage monitoring ..............364 18.4.7.1 Status flag and interrupts ............365 18.5 ADC registers ................365 18.5.1 ADC status register (ADC_STS) ..........366 18.5.2 ADC control register1 (ADC_CTRL1) ........... 366 18.5.3 ADC control register2 (ADC_CTRL2) ........... 368 18.5.4 ADC sampling time register 1 (ADC_SPT1) ........
- Page 18 AT32F423 Series Reference Manual 19.5.1 DAC control register (DAC_CTRL) ..........382 19.5.2 DAC software trigger register (DAC_SWTRG) ......385 19.5.3 DAC1 12-bit right-aligned data holding register (DAC_D1DTH12R) 385 19.5.4 DAC1 12-bit left-aligned data holding register (DAC_D1DTH12L) .. 385 19.5.5 DAC1 8-bit right-aligned data holding register (DAC _D1DTH8R) ... 385 19.5.6 DAC2 12-bit right-aligned data holding register (DAC_D2DTH12R) 385...
- Page 19 AT32F423 Series Reference Manual 20.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ........ 406 20.7.1.6 CAN interrupt enable register (CAN_INTEN) ......407 20.7.1.7 CAN error status register (CAN_ESTS) ........409 20.7.1.8 CAN bit timing register (CAN_BTMG) ........409 20.7.2 CAN mailbox registers ..............410 20.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ..
- Page 20 AT32F423 Series Reference Manual 21.5.3.1 Host initialization ..............419 21.5.3.2 OTGFS channel initialization ..........420 21.5.3.3 Halting a channel ..............420 21.5.3.4 Queue depth ................. 420 21.5.3.5 Special cases ............... 422 21.5.3.6 Host HFIR feature ..............422 21.5.3.7 Initialize bulk and control IN transfers ........424 21.5.3.8 Initialize bulk and control OUT/SETUP transfers ......
- Page 21 AT32F423 Series Reference Manual 21.6.3.1 OTGFS status and control register ( OTGFS_GOTGCTL) ..457 21.6.3.2 OTGFS interrupt status control register (OTGFS_GOTGINT) ..457 21.6.3.3 OTGFS AHB configuration register (OTGFS_GAHBCFG) ..457 21.6.3.4 OTGFS USB configuration register (OTGFS_GUSBCFG) ..458 21.6.3.5 OTGFS reset register (OTGFS_GRSTCTL) ......459 21.6.3.6 OTGFS interrupt register (OTGFS_GINTSTS) ......
- Page 22 AT32F423 Series Reference Manual 21.6.5 Device-mode registers ..............474 21.6.5.1 OTGFS device configure register (OTGFS_DCFG) ....474 21.6.5.2 OTGFS device control register (OTGFS_DCTL) ....... 475 21.6.5.3 OTGFS device status register (OTGFS_DSTS) ......476 21.6.5.4 OTGFS device OTGFSIN endpoint common interrupt mask register (OTGFS_DIEPMSK) ................
- Page 23 AT32F423 Series Reference Manual 22.1 ACC introduction ............... 491 22.2 Main features ................491 22.3 Interrupt requests ..............491 22.4 Functional description ..............491 22.5 Principle..................493 22.6 Register description ..............494 22.6.1 ACC register map ............... 494 22.6.2 Status register (ACC_STS) ............494 22.6.3 Control register 1 (ACC_CTRL1) ..........
- Page 24 AT32F423 Series Reference Manual 25.1 Debug introduction ..............512 25.2 Debug and Trace ............... 512 25.3 I/O pin control................512 25.4 DEGUB registers ............... 512 25.4.1 DEBUG device ID (DEBUG_IDCODE) .......... 513 25.4.2 DEBUG control register (DEBUG_CTRL) ........513 25.4.3 DEBUG APB1 pause register (DEBUG_ APB1_PAUSE) ....514 25.4.4 DEBUG APB2 pause register (DEBUG_ APB2_PAUSE) ....
- Page 25 AT32F423 Series Reference Manual List of figures Figure 1-1 AT32F423 series microcontrollers system architecture ............. 34 Figure 1-2 Internal block diagram of Cortex -M4F ..................35 Figure 1-3 Comparison between bit-band region and its alias region: image A ......... 36 Figure 1-4 Comparison between bit-band region and its alias region: image B .........
- Page 26 AT32F423 Series Reference Manual Figure 11-15 SMBus master transmission flow ..................159 Figure 11-16 SMBus master transmission timing ..................160 Figure 11-17 SMBus master receive flow ....................160 Figure 11-18 SMBus master receive timing ....................161 Figure 11-19 SMBus slave transmission flow .................... 163 Figure 11-20 SMBus slave transmission timing ..................
- Page 27 AT32F423 Series Reference Manual Figure 14-2 Control circuit with CK_INT divided by 1 ................220 Figure 14-3 Basic structure of a counter ....................221 Figure 14-4 Overflow event when PRBEN=0 .................... 221 Figure 14-5 Overflow event when PRBEN=1 .................... 221 Figure 14-6 Counting timing diagram when the prescaler division is 4 ............
- Page 28 AT32F423 Series Reference Manual Figure 14-47 Counter timing diagram with internal clock divided by 4 ............. 256 Figure 14-48 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32....257 Figure 14-49 OVFIF in upcounting mode and central-aligned mode ............258 Figure 14-50 Encoder mode structure .......................
- Page 29 AT32F423 Series Reference Manual Figure 14-92 Counter timing with prescaler value changing from 1 to 4 ..........301 Figure 14-93 Basic structure of a counter ....................302 Figure 14-94 Overflow event when PRBEN=0 ..................302 Figure 14-95 Overflow event when PRBEN=1 ..................302 Figure 14-96 Counter timing diagram with internal clock divided by 4 .............
- Page 30 AT32F423 Series Reference Manual Figure 20-1 Bit timing ..........................387 Figure 20-2 Frame type ..........................389 Figure 20-3 Transmit interrupt generation ....................390 Figure 20-4 Receive interrupt 0 generation ....................390 Figure 20-5 Receive interrupt 1 generation ....................390 Figure 20-6 Status error interrupt generation .................... 390 Figure 20-7 CAN block diagram ........................
- Page 31 Table 1-1 Bit-band address mapping in SRAM ................... 37 Table 1-2 Bit-band address mapping in the peripheral area ............... 37 Table 1-3 AT32F423 series vector table ...................... 38 Table 1-4 List of abbreviations for registers ....................43 Table 1-5 Base address and reset value of registers .................. 43 Table 2-1 Flash memory organization (256 KB) ..................
- Page 32 AT32F423 Series Reference Manual Table 12-3 Data sampling over valid data and noise detection ..............185 Table 12-4 USART interrupt requests ......................187 Table 12-5 USART register map and reset value ..................188 Table 13-1 Audio frequency precision using system clock ................. 211 Table 13-2 SPI register map and reset value ....................
- Page 33 AT32F423 Series Reference Manual Table 24-5 Data access width vs. external memory data width ..............501 Table 24-6 NOR/PSRAM parameter registers................... 502 Table 24-7 Multiplexed mode — SRAM/NOR Flash chip select control register ........502 Table 24-8 Multiplexed mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) configuration ................................
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Page 34: System Architecture
AT32F423 Series Reference Manual System architecture AT32F423 series microcontrollers consist of 32-bit ARM ®Cortex -M4F processor, multiple 16-bit and 32-bit timers, infrared transmitter (IRTMR), DMA controller, ERTC, communication interfaces such as SPI, I C and USART, CAN bus controller, external memory controller (XMC), USB2.0 OTG full-speed interface, HICK with automatic clock calibration (ACC), 12-bit ADC, 12-bit DAC, programmable voltage monitor (PVM) and other peripherals. -
Page 35: System Overview
AT32F423 Series Reference Manual 1.1 System overview 1.1.1 ARM Cortex -M4F processor Cortex -M4 processor is a low-power consumption processor featuring with low gate count, low interrupt latency and low-cost debug. It supports DSP instruction set and FPU, and it is applicable to deeply embedded applications that require quicker response to interruption. -
Page 36: Figure 1-3 Comparison Between Bit-Band Region And Its Alias Region: Image A
AT32F423 Series Reference Manual Figure 1-3 Comparison between bit-band region and its alias region: image A 0x200F_FFFC 0x2000_0000 bitband region address (total 1M bytes) 0x2000_0008 0x2000_0004 0x2000_0000 0x2000_0080 0x2000_002C 0x2000_0010 0x2000_0000 bitband alias region address Figure 1-4 Comparison between bit-band region and its alias region: image B... -
Page 37: Table 1-1 Bit-Band Address Mapping In Sram
AT32F423 Series Reference Manual AliasAddr = 0x4200_0000+ (A-0x4000_0000)*32+n*4 Table 1-1 shows the mapping between bit-band region and alias region in SRAM: Table 1-1 Bit-band address mapping in SRAM Bit-band region Equivalent alias address 0x2000_0000.0 0x2200_0000.0 0x2000_0000.1 0x2200_0004.0 0x2000_0000.2 0x2200_0008.0 …... -
Page 38: Interrupt And Exception Vectors
AT32F423 Series Reference Manual 1.1.3 Interrupt and exception vectors Table 1-3 AT32F423 series vector table Pos. Priority Priority type Name Description Address Reserved 0x0000_0000 Fixed Reset Reset 0x0000_0004 Non-maskable interrupt Fixed CRM clock fail detector (CFD) is linked to 0x0000_0008... - Page 39 AT32F423 Series Reference Manual Configurable DMA1 channel 7 DMA1 channel 7 global interrupt 0x0000_0084 Configurable ADC ADC global interrupt 0x0000_0088 Configurable CAN1_TX CAN1 sent interrupt 0x0000_008C Configurable CAN1_RX0 CAN1 received 0 interrupt 0x0000_0090 Configurable CAN1_RX1 CAN1 received 1 interrupt 0x0000_0094...
- Page 40 AT32F423 Series Reference Manual Configurable SPI3 SPI3 global interrupt 0x0000_010C Configurable USART4 USART4 global interrupt 0x0000_0110 Configurable USART5 USART5 global interrupt 0x0000_0114 TMR6 global interrupt Configurable TMR6_DAC 0x0000_0118 DAC1 DAC2 underflow error interrupt Configurable TMR7 TMR7 global interrupt 0x0000_011C Configurable DMA2 channel 1...
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Page 41: System Tick (Systick)
AT32F423 Series Reference Manual 0x0000_0194 0x0000_0198 0x0000_019C 0x0000_01A0 0x0000_01A4 0x0000_01A8 0x0000_01AC 0x0000_01B0 0x0000_01B4 Configurable DMAMUX DMAMUX overflow interrupt 0x0000_01B8 0x0000_01BC 0x0000_01C0 0x0000_01C4 0x0000_01C8 0x0000_01CC 0x0000_01D0 0x0000_01D4 0x0000_01D8 Configurable ACC ACC global interrupt 0x0000_01DC 1.1.4 System Tick (SysTick) The System Tick is a 24-bit downcounter. It will be reloaded with the initial value automatically when it is decremented to zero. -
Page 42: Figure 1-6 Example Of Msp And Pc Initialization
0x0000_0000 0x2000_8000 In the AT32F423 series, the main Flash memory, boot memory or SRAM can be remapped to the CODE area between 0x0000_0000 and 0x07FF_FFFF. nBOOT1 corresponds to the value of the bit nBOOT1 in the SSB of the User System Data (USD). nBOOT1 and BOOT0 are used to set the specific memory from which CODE starts. -
Page 43: List Of Abbreviations For Registers
AT32F423 Series Reference Manual 1.2 List of abbreviations for registers Table 1-4 List of abbreviations for registers Register type Description Software can read and write to this bit. Software can only read this bit. Software can only write to this bit. Reading it returns to its reset value. -
Page 44: Memory Resources
0x0000_0000 0x0000_0000 2.2 Flash memory AT32F423 series provide up to 256 KB of on-chip Flash memory, supporting a single-cycle 32-bit read operation. Refer to Chapter 5 for more details about Flash memory controller and register configuration. Flash memory organization (256 KB) The main memory contains bank 1 (256 Kbytes), including 128 sectors, 2 Kbytes per sector. -
Page 45: Table 2-1 Flash Memory Organization (256 Kb)
AT32F423 Series Reference Manual Table 2-1 Flash memory organization (256 KB) Bank Name Address range Sector 0 0x0800 0000 – 0x0800 07FF Sector 1 0x0800 0800 – 0x0800 0FFF Sector 2 0x0800 1000 – 0x0800 17FF Bank1 Sector 3 0x0800 1800 – 0x0800 1FFF... -
Page 46: Sram Memory
AT32F423 Series Reference Manual 2.3 SRAM memory The AT32F423 series contain a 48-KB on-chip SRAM that starts at the address of 0x2000_0000. It can be accessed by bytes, half-words (16-bit) or words (32-bit). 2.4 Peripheral address map Table 2-4 Peripheral boundary address... - Page 47 AT32F423 Series Reference Manual 0x4001 3800 - 0x4001 3BFF SCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI1/I2S1 0x4001 2400 - 0x4001 2FFF Reserved 0x4001 2000 - 0x4001 23FF 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF...
- Page 48 AT32F423 Series Reference Manual 0x4000 0800 - 0x4000 0BFF TMR4 timer 0x4000 0400 - 0x4000 07FF TMR3 timer 0x4000 0000 - 0x4000 03FF TMR2 timer 2023.04.25 Page 48 Rev 2.01...
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Page 49: Power Control (Pwc)
AT32F423 Series Reference Manual Power control (PWC) 3.1 Introduction For AT32F423 series, its operating voltage supply is 2.4 V ~ 3.6 V, with a temperature range of -40~+105 C. To reduce power consumption, this series provides three types of power saving modes, including Sleep, Deepsleep and Standby modes so as to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption. -
Page 50: Power Voltage Monitor (Pvm)
AT32F423 Series Reference Manual Figure 3-2 Power-on reset/Low voltage reset waveform hysteresis Temporization tRESTTEMPO Reset 3.4 Power voltage monitor (PVM) The PVM is used to monitor the power supply variations. It is enabled by setting the PVMEN bit in the power control register (PWC_CTRL), and the threshold value for voltage monitor is selected with the PVMSEL[2:0]. -
Page 51: Power Domain
PWC_LDOOV register. The maximum operating frequency for the system depends on the selected output voltage. Refer to AT32F423 Series Datasheet for details. Note: The LDO output voltage is changeable only when the HEXT or HICK is used as system clock. - Page 52 AT32F423 Series Reference Manual The wakeup event can be generated by the following: Enabling a peripheral interrupt (it is not enabled in the NVIC) and enabling the SEVONPEND bit. When the MCU resumes, the peripheral interrupt pending bit and NVIC channel pending bit must be cleared.
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Page 53: Pwc Registers
AT32F423 Series Reference Manual The MCU exits the Standby mode when a rising edge on the WKUP pin, a rising edge of an ERTC alarm event, an ERTC tamper event, ERTC timestamp, ERTC periodic automatic wakeup, an external reset (NRST pin) or a WDT reset occurs. -
Page 54: Power Control/Status Register (Pwc_Ctrlsts)
AT32F423 Series Reference Manual 0: Enter Deepsleep mode 1: Enter Standby mode Voltage regulator state select when Deepsleep mode Bit 0 VRSEL 0: Enabled 1: Low-power consumption mode 3.7.2 Power control/status register (PWC_CTRLSTS) Name Reset value Type Description Bit 31:15... -
Page 55: Ldo Output Voltage Select Register (Pwc_Ldoov)
AT32F423 Series Reference Manual 3.7.3 LDO output voltage select register (PWC_LDOOV) Name Reset value Type Description Bit 31:5 Reserved 0x0000000 resd Kept at its default value. Voltage regulator extra low power mode enable This bit works together with the LPSEL... -
Page 56: Clock And Reset Manage (Crm)
HICK clock is 48 MHz. Although it is less accurate, its startup time is shorter than the HEXT crystal oscillator. The HICK clock frequency of each device is calibrated by ARTERY to ±1% accuracy (25°C) in factory. The factory-trimmed value is loaded in the HICKCAL[7: 0] bit of the clock control register. The 2023.04.25... - Page 57 AT32F423 Series Reference Manual RC oscillator speed may be affected by voltage or temperature variations. Thus the HICK frequency can be trimmed by setting the HICKTRIM[5: 0] bit in the clock control register. The HICK clock signal is not released until it becomes stable.
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Page 58: System Clock
AT32F423 Series Reference Manual 4.1.2 System clock After a system reset, the HICK oscillator is selected as system clock. The system clock can make flexible switch among HICK oscillator, HEXT oscillator and PLL clock. However, a switch from one clock source to another occurs only if the target clock source becomes stable. -
Page 59: Interrupts
If a failure is detected on the HEXT clock, the CFD interrupt is generated. Such interrupt is directly linked to CPU NMI. 4.2 Reset 4.2.1 System reset AT32F423 series provide the following system reset sources: NRST reset: on the external NRST pin WDT reset: watchdog overflow ... -
Page 60: Crm Registers
AT32F423 Series Reference Manual 4.3 CRM registers These peripheral registers have to be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits). Table 4-1 CRM register map and reset values Register Offset Reset value CRM_CTRL 0x000 0x0000 XX83... -
Page 61: Pll Clock Configuration Register (Crm_Pllcfg)
AT32F423 Series Reference Manual Clock Failure Detection enable Bit 19 CFDEN 0: Disabled 1: Enabled High speed external crystal bypass This bit can be set by software only when the HEXT is Bit 18 HEXTBYPS disabled. 0: Disabled 1: Enabled High speed external crystal stable This bit is set by hardware after HEXT becomes stable. -
Page 62: Clock Configuration Register (Crm_Cfg)
AT32F423 Series Reference Manual PLL post-division PLL_FR range (0~5) 000: PLL post-division=1 001: PLL post-division=2 010: PLL post-division=4 011: PLL post-division=8 Bit 18:16 PLL_FR 100: PLL post-division=16 101: PLL post-division=32 Others: Reserved Attention should be paid to the correlation between the PLL_FR value and post-division factor. - Page 63 AT32F423 Series Reference Manual Clock output division1 0xx: CLKOUT 100: CLKOUT/2 Bit 29:27 CLKOUTDIV1 101: CLKOUT/3 110: CLKOUT/4 111: CLKOUT/5 Kept at its default value. Bit 26:21 Reserved 0x00 resd HEXT division for ERTC clock This field is set and cleared by software to divide the HEXT for ERTC clock.
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Page 64: Clock Interrupt Register (Crm_Clkint)
AT32F423 Series Reference Manual 4.3.4 Clock interrupt register (CRM_CLKINT) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Kept at its default value. Bit 31:24 Reserved 0x00 resd Clock failure detection interrupt clear Writing 1 by software to clear CFDF. -
Page 65: Ahb Peripheral Reset Register 1 (Crm_Ahbrst1)
AT32F423 Series Reference Manual 0: LEXT is not ready 1: LEXT is ready LICK stable flag Set by hardware. Bit 0 LICKSTBLF 0: LICK is not ready 1: LICK is ready 4.3.5 AHB peripheral reset register 1 (CRM_AHBRST1) Access: 0 wait state, accessible by words, half-words and bytes. -
Page 66: Ahb Peripheral Reset Register 3 (Crm_Ahbrst3)
AT32F423 Series Reference Manual 4.3.7 AHB peripheral reset register 3 (CRM_AHBRST3) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Kept at its default value. Bit 31:1 Reserved 0x00000000 resd XMC reset 0: Does not reset XMC... -
Page 67: Apb2 Peripheral Reset Register (Crm_Apb2Rst)
AT32F423 Series Reference Manual Window watchdog reset 0: Does not reset window watchdog Bit 11 WWDTRST 1: Reset window watchdog Kept at its default value. Bit 10:9 Reserved resd Timer14 reset 0: Does not reset Timer14 Bit 8 TMR14RST 1: Reset Timer14... -
Page 68: Ahb Peripheral Clock Enable Register 1 (Crm_Ahben1)
AT32F423 Series Reference Manual 1: Reset USART6 USART1 reset) 0: Does not reset USART1 Bit 4 USART1RST 1: Reset USART1 Kept at its default value. Bit 3:1 Reserved resd TMR1 timer reset) 0: Does not reset TMR1 Bit 0 TMR1RST 1: Reset TMR1 4.3.10 AHB peripheral clock enable register 1 (CRM_AHBEN1) -
Page 69: Ahb Peripheral Clock Enable Register 3 (Crm_Ahben3)
AT32F423 Series Reference Manual 4.3.12 AHB peripheral clock enable register 3 (CRM_AHBEN3) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Kept at its default value. Bit 31:1 Reserved 0x00000000 resd XMC clock enable... -
Page 70: Apb2 Peripheral Clock Enable Register (Crm_Apb2En)
AT32F423 Series Reference Manual 0: Disabled 1: Enabled Kept at its default value. Bit 10:9 Reserved resd Timer14 clock enable 0: Disabled Bit 8 TMR14EN 1: Enabled Timer13 clock enable 0: Disabled Bit 7 TMR13EN 1: Enabled Timer12 clock enable... -
Page 71: Ahb Peripheral Clock Enable In Low Power Mode Register
AT32F423 Series Reference Manual USART1 clock enable 0: Disabled Bit 4 USART1EN 1: Enabled Kept at its default value. Bit 3:1 Reserved resd TMR1 timer clock enable 0: Disabled Bit 0 TMR1EN 1: Enabled 4.3.15 AHB peripheral clock enable in low power mode register (CRM_AHBLPEN1) Access: 0 wait state, accessible by words, half-words and bytes. -
Page 72: (Crm_Ahblpen2)
AT32F423 Series Reference Manual 4.3.16 AHB peripheral clock enable in low power mode register 2 (CRM_AHBLPEN2) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Kept at its default value. Bit 31:8 Reserved 0x000000... -
Page 73: Apb2 Peripheral Clock Enable In Low Power Mode Register (Crm_Apb2Lpen)
AT32F423 Series Reference Manual USART3 clock enable in Sleep mode 0: Disabled Bit 18 USART3LPEN 1: Enabled USART2 clock enable in Sleep mode 0: Disabled Bit 17 USART2LPEN 1: Enabled Kept at its default value. Bit 16 Reserved resd SPI3 clock enable in Sleep mode... -
Page 74: Peripheral Independent Clock Select Register (Crm_Piclks)
AT32F423 Series Reference Manual Kept at its default value. Bit 15 Reserved resd SCFG clock enable in Sleep mode 0: Disabled Bit 14 SCFGLPEN 1: Enabled Kept at its default value. Bit 13 Reserved resd SPI1 clock enable in Sleep mode... -
Page 75: Control/Status Register (Crm_Ctrlsts)
AT32F423 Series Reference Manual Name Reset value Type Description Kept at its default value. Bit 31:17 Reserved 0x0000 resd Battery powered domain software reset 0: Does not reset battery powered domain software Bit 16 BPDRST 1: Reset battery powered domain software... -
Page 76: Additional Register 1 (Crm_Misc1)
AT32F423 Series Reference Manual Reset flag clear Cleared by writing 1 through software. Bit 24 RSTFC 0: No effect 1: Clear the reset flag Bit 23:2 Reserved 0x000000 resd Kept at its default value. LICK stable Bit 1 LICKSTBL 0: LICK is not ready... -
Page 77: Additional Register 2 (Crm_Misc2)
AT32F423 Series Reference Manual 4.3.24 Additional register 2 (CRM_MISC2) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Bit 31:22 Reserved 0x000 resd Kept at its default value. HEXT as system clock frequency division... -
Page 78: Flash Memory Controller (Flash)
AT32F423 Series Reference Manual Flash memory controller (FLASH) 5.1 FLASH introduction Flash memory is divided into three parts: main Flash memory, information block and Flash memory registers. Main Flash memory is up to 256 KB. Information block consists of 20 KB bootloader and the user system data area. The bootloader uses USART1, USART2 or USB serial interface for ISP programming. -
Page 79: Table 5-4 User System Data Area
AT32F423 Series Reference Manual Each system data occupies two bytes, where the low byte corresponds to the contents in the system data area and the high byte represents the inverse code that is used to verify the correctness of the selected bit. -
Page 80: Flash Memory Operation
AT32F423 Series Reference Manual nEPP2[7:0]: Inverse code of EPP2[7:0] [15:8] EPP3[7:0]: Flash erase/write protection byte 3 (in the FLASH_EPPS[31:24]) Bit [6:0] is used to protect sector48~sector61 of the main Flash memory (256 KB) and sector96~sector123 of the main Flash memory (128 KB). Each bit takes care of 4 KB sectors. -
Page 81: Figure 5-1 Flash Memory Sector Erase Process
AT32F423 Series Reference Manual Note: When the boot memory is configured as the Flash memory extension area, performing sector- erase operation erases the entire Flash memory extension area. Figure 5‑1 Flash memory sector erase process Start Check the OBF bit in FLASH_STS... -
Page 82: Programming Operation
AT32F423 Series Reference Manual Note: 1) When the boot memory is configured as the Flash memory extension area, performing mass-erase operation erases automatically the entire the entire Flash memory and its extension area. 2) Read access during erase operation halts the CPU and waits until the completion of erase. -
Page 83: Figure 5-3 Flash Memory Programming Process
AT32F423 Series Reference Manual Note: 1) When the address to be written is not erased in advance, the programming operation is not executed unless the data to be written is all 0. In this case, a programming error is reported by the PRGMERR bit in the FLASH_STS register. -
Page 84: Read Operation
AT32F423 Series Reference Manual 5.2.4 Read operation Flash memory can be accessed through AHB bus of the CPU. 5.3 Main Flash memory extension area Boot memory can also be programmed as the extension area of the main Flash memory to store user- application code. -
Page 85: Programming Operation
AT32F423 Series Reference Manual Figure 5‑4 System data area erase process Start Check the OBF bit in FLASH_STS OBF = 0? Set USDERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ? Read ODF bit in FLASH_STS 5.4.3... -
Page 86: Read Operation
AT32F423 Series Reference Manual Figure 5‑5 System data area programming process Start Check the OBF bit in FLASH_STS OBF = 0? Set the USDPRGM bit = 1 in FLASH_CTRL Write word/half-word (32bits/16 bits) data Check the OBF bit in FLASH_STS... -
Page 87: Access Protection
AT32F423 Series Reference Manual 5.5.1 Access protection Flash memory access protection is divided into two parts: high-level and low level. Once enabled, only the Flash program is allowed to read Flash memory data. This read operation is not permitted in debug mode or by booting from non-Flash memory. -
Page 88: Read Access
AT32F423 Series Reference Manual When the Flash access protection is enabled, the sector0~sector1 in the 256 KB main Flash memory and sector0~sector3 in the 128 KB/64 KB Flash memory will be protected against erase/program automatically; When the Flash access protection is enabled, the main Flash memory is protected against sector erase and programming operation when it is the main Flash memory and its extension area are in debug mode or when it boots from non-main Flash memory. -
Page 89: Boot Memory Used As Flash Memory Extension
AT32F423 Series Reference Manual Perform system reset, and then reload security library setting word. Read the SLIB_STS0/STS1 register to verify the security library settings. Note: The main Flash memory and its extension area cannot be set as security library at the same time. -
Page 90: Flash Performance Select Register (Flash_Psr)
AT32F423 Series Reference Manual FLASH_ADDR 0x14 0x0000 0000 FLASH_USD 0x1C 0x03FF FFFC FLASH_EPPS 0x20 0xFFFF FFFF SLIB_STS0 0x74 0x00FF 0000 SLIB_STS1 0x78 0xFFFF FFFF SLIB_PWD_CLR 0x7C 0xFFFF FFFF SLIB_MISC_STS 0x80 0x0000 0000 FLASH_CRC_ADDR 0x84 0x0000 0000 FLASH_CRC_CTRL 0x88 0x0000 0000... -
Page 91: Flash Unlock Register (Flash_Unlock)
AT32F423 Series Reference Manual 5.8.2 Flash unlock register (FLASH_UNLOCK) Abbr. Reset value Type Description Unlock key value Bit 31:0 UKVAL 0xXXXX XXXX This is used to unlock the Flash memory and its extension area. Note: All these bits are write-only, and return 0 when being read. -
Page 92: Flash Address Register (Flash_Addr)
AT32F423 Series Reference Manual User system data program Bit 4 USDPRGM It indicates the user system data program. Bank erase Bit 2 BANKERS It indicates bank erase operation. Sector erase Bit 1 SECERS It indicates sector erase operation. Flash program... -
Page 93: Flash Security Library Status Register 0 (Sl Ib_Sts0)
AT32F423 Series Reference Manual 5.8.9 Flash security library status register 0 (SLIB_STS0) For Flash security library only. Abbr. Reset value Type Description Bit 31:24 Reserved 0x00 resd Kept at its default value. Extension memory sLib instruction start sector 00000000: Sector 0... -
Page 94: Security Library Password Clear Register (Slib_Pwd_Clr)
AT32F423 Series Reference Manual … 00001111111: Sector 127 (the last sector of 256KB/128KB main Flash memory) 5.8.11 Security library password clear register (SLIB_PWD_CLR) For Flash security library only. Abbr. Reset value Type Description sLib password clear value This register is used to key in a correct sLib password in... -
Page 95: Flash Crc Check Result Register (Flash_Crc_Chkr)
AT32F423 Series Reference Manual 5.8.15 Flash CRC check result register (FLASH_CRC_CHKR) For the main Flash memory and its extension area. Abbr. Reset value Type Description Bit 31:0 CRC_CHKR 0x0000 0000 CRC check result Note: All these bits are read-only, and return no response when being written. -
Page 96: Flash Extension Memory Security Library Setting Register
AT32F423 Series Reference Manual 5.8.18 Flash extension memory security library setting register (EM_SLIB_SET) For Flash extension area only. Abbr. Reset value Type Description Bit 31:24 Reserved 0x00 resd Kept at its default value. Extension memory sLib instruction start sector setting It is used to set the security library instruction area start sector. -
Page 97: Gpios And Iomux
AT32F423 Series Reference Manual GPIOs and IOMUX Introduction AT32F423 series supports up to 86 bidirectional I/O pins, namely PA0-PA15, PB0-PB15, PC0-PC15, PD0-PD15, PE0-PE15, PF0-PF2 PF6 PF8-PF10. Each of these pins features communication, control and data collection. In addition, their main features also include: ... -
Page 98: Gpio Reset Status
AT32F423 Series Reference Manual 6.2.2 GPIO reset status After power-on or system reset, all pins are configured as floating input mode except JATG-related pins. JTAG pin configurations are as follows: PA15/JTDI, PA13/JTMS and PB4/JNTRST in multiplexed pull-up mode; ... -
Page 99: I/O Port Protection
AT32F423 Series Reference Manual When I/O port is configured as output: Schmitt-trigger input is enabled; Output through output register; In opens-drain mode, forced output 0, and use pull-up resistor to output 1; In push-pull mode, output register is used to output 0/1;... -
Page 100: Multiplexed Function Pull-Up/Down Configuration
AT32F423 Series Reference Manual 6.2.8 Multiplexed function pull-up/down configuration Mode IOMC PUPD Multiplexed function floating Multiplexed function pull-down Multiplexed function pull-up When an I/O port is configured as input: Get an I/O pin state by reading input data register;... - Page 101 AT32F423 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 USART4_TX EVENTOUT USART4_R EVENTOUT CAN2_RX XMC_D4 EVENTOUT CAN2_TX XMC_D5 EVENTOUT USART6_TX TMR14_CH1 OTGFS_OE XMC_D6 EVENTOUT USART6_R TMR13_CH1C XMC_D7 EVENTOUT USART3_R TMR13_CH1 EVENTOUT TMR14_CH1 EVENTOUT USART2_TX USART7_RX OTGFS_SOF EVENTOUT...
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Page 102: Table 5-8 Port B Multiplexed Function Configuration With Gpioa_Mux* Register
AT32F423 Series Reference Manual Table 5-8 Port B multiplexed function configuration with GPIOA_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 SPI1_MISO / SPI3_MOSI/I2S3_S TMR1_CH2C TMR3_CH3 USART2_RX I2S1_MCK SPI1_MOSI / TMR1_CH3C TMR3_CH4 SPI2_SCK/I2S2_CK USART2_CK I2S1_SD SPI3_MOSI/I2S3_S TMR2_CH4 TMR3_EXT I2C3_SMBA... - Page 103 AT32F423 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 USART3_CK EVENTOUT USART3_RTS_ TMR14_CH1 EVENTOUT TMR14_CH1C EVENTOUT USART1_RTS_ USART7_RX USART5_TX EVENTOUT I2S_SDEXT USART7_TX USART5_RX EVENTOUT USART5_RTS_D USART5_RX CAN2_RX EVENTOUT USART5_TX CAN2_TX USART4_CK EVENTOUT USART4_CTS XMC_NADV EVENTOUT USART5_RX CAN1_RX...
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Page 104: Table 5-9 Port C Multiplexed Function Configuration With Gpioa_Mux* Register
AT32F423 Series Reference Manual Table 5-9 Port C multiplexed function configuration with GPIOA_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 I2C3_SCL I2C1_SCL SPI3_MOSI/I2 SPI2_MOSI/I2S2_S I2C3_SDA I2C1_SDA S3_SD SPI2_MISO/I2 I2S_SDEXT S2_MCK SPI2_MOSI/I2 S2_SD TMR9_CH1 I2S1_MCK USART3_TX TMR9_CH2 I2C1_SMBA USART3_RX... - Page 105 AT32F423 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 USART6_T USART7_TX EVENTOUT USART6_R USART7_RX EVENTOUT USART8_T XMC_NWE EVENTOUT USART8_R XMC_A0 EVENTOUT XMC_NE4 EVENTOUT TMR13_CH1 TMR13_CH1C XMC_NOE EVENTOUT USART6_T USART7_TX XMC_D1 EVENTOUT USART6_R USART7_RX XMC_NADV EVENTOUT USART6_C EVENTOUT...
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Page 106: Table 5-10 Port D Multiplexed Function Configuration With Gpioa_Mux* Register
AT32F423 Series Reference Manual Table 5-10 Port D multiplexed function configuration with GPIOA_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 SPI3_MOSI/I2S3_S SPI2_CS/I2S 2_WS SPI2_CS/I2S SPI2_SCK/I2S2_CK 2_WS USART3_RT TMR3_EXT S_DE SPI2_SCK/I2 SPI2_MISO/I2S2_M USART2_CT S2_CK SPI2_MOSI/I2S2_S USART2_RT S_DE USART2_TX SPI3_MOSI/I2... - Page 107 AT32F423 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 USART4_R CAN1_RX XMC_D2 EVENTOUT USART4_T CAN1_TX XMC_D3 EVENTOUT USART5_R XMC_NWE EVENTOUT XMC_CLK EVENTOUT XMC_NOE EVENTOUT XMC_NWE EVENTOUT XMC_NWAIT EVENTOUT XMC_NE1 EVENTOUT TMR12_CH2C XMC_D13 EVENTOUT XMC_D14 EVENTOUT USART4_T PD10...
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Page 108: Table 5-11 Port E Multiplexed Function Configuration With Gpioa_Mux* Register
AT32F423 Series Reference Manual Table 5-11 Port E multiplexed function configuration with GPIOA_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 TMR4_EXT TMR1_CH2C TMR3_EXT TMR9_BRK TMR3_CH1 TMR9_CH2C TMR3_CH2 TMR9_CH1C TMR3_CH3 TMR9_CH1 TMR3_CH4 TMR9_CH2 TMR1_EXT TMR1_CH1C TMR1_CH1 PE10 TMR1_CH2C PE11... - Page 109 AT32F423 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 USART8_R TMR13_CH1 XMC_LB EVENTOUT USART8_T TMR14_CH1 XMC_UB EVENTOUT TMR14_CH1C XMC_A23 EVENTOUT TMR14_BRK XMC_A19 EVENTOUT XMC_A20 EVENTOUT XMC_A21 EVENTOUT XMC_A22 EVENTOUT USART5_C USART7_RX XMC_D4 EVENTOUT USART4_T USART7_TX XMC_D5 EVENTOUT...
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Page 110: Peripheral Mux Function Configuration
AT32F423 Series Reference Manual Table 5-12 Port F multiplexed function configuration with GPIOA_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 TMR1_CH1 I2C1_SDA SPI2_CS / TMR1_CH2C I2C1_SCL I2S2_WS SPI2_SCK/I2 S2_CK TMR2_CH1 I2C2_SCL TMR2_CH2 I2C2_SDA TMR4_CH1 PF10 TMR4_CH2 MUX8 MUX9... -
Page 111: External Interrupt/Wake-Up Lines
AT32F423 Series Reference Manual PB15 PWC_CTRLSTS[14] =1 Once enabled, PB15 pin acts as WKUP7 of PWC. (ERTC_CTRL[23]=1)| (ERTC_CTRL[22:21]!=00)| (ERTC_CTRL[11]=1& PC13 Once enabled, PC13 pin is used as RTC channel. ERTC_TAMP[17]=0)| (ERTC_TAMP[0]=1& ERTC_TAMP[16]=0) (ERTC_CTRL[11]=1& ERTC_TAMP[17]=1)| (ERTC_TAMP[0]=1& Once enabled, PA0 pin is used as TAMPER2_BPR. -
Page 112: Gpio Configuration Register (Gpiox_Cfgr) (X=A
AT32F423 Series Reference Manual 6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A..F) Address offset: 0x00 Reset value: 0xa8000000 for port A, for port , and 0x00000000 for other ports. 0x0000 0280 Register Reset value Type Description GPIOx mode configuration (y=~15) This field is used to configure the GPIOx mode:... -
Page 113: Gpio Output Data Register (Gpiox_Odt) (X=A
AT32F423 Series Reference Manual 6.3.6 GPIO output data register (GPIOx_ODT) (x=A..F) Register Reset value Type Description Bit 31:16 Reserved 0x0000 resd Always 0. GPIOx output data Each bit represents an I/O port. Bit 15:0 0x0000 It indicates the output status of I/O port. -
Page 114: Gpio Multiplexed Function High Register (Gpiox_Muxh) (X=A
AT32F423 Series Reference Manual 1011: MUX11 1100: MUX12 1101: MUX13 1110: MUX14 1111: MUX15 6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..F) Register Reset value Type Description Multiplexed function select for GPIOx pin y (y=8…15) This field is used to configure multiplexed function IOs. -
Page 115: System Configuration Controller (Scfg)
AT32F423 Series Reference Manual System configuration controller (SCFG) 7.1 Introduction This device contains a set of system configuration register. The system configuration controller is mainly set to: Manage the external interrupts connected to the GPIOs Control the memory mapping mode ... - Page 116 AT32F423 Series Reference Manual Bit 29:3 Reserved 0x0000 000 resd Kept at its default value. PVM lock enable 0: Disconnect the PVM interrupt with TIM1/TIM9/ TIM10/11/12/13/14 break input. The PVMSEL and Bit 2 PVM_LK PVMEN bits can be modified by software.
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Page 117: Scfg External Interrupt Configuration Register 3 (Scfg_Exintc3)
AT32F423 Series Reference Manual 7.2.4 SCFG external interrupt configuration register 2 (SCFG_EXINTC2) Register Reset value Type Description Bit 31:16 Reserved 0x0000 resd Kept at its default value. EXINT7 input source configuration These bits are used to select the input source for the EXINT7 external interrupt. - Page 118 AT32F423 Series Reference Manual Others: Reserved EXINT9 input source configuration These bits are used to select the input source for the EXINT9 external interrupt. 0000: GPIOA pin 9 0001: GPIOB pin 9 Bit 7:4 EXINT9 0010: GPIOC pin 9 0011: GPIOD pin 9...
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Page 119: Scfg Ultra High Souring/Sinking Strength (Scfg_Uhdrv)
AT32F423 Series Reference Manual 7.2.7 SCFG ultra high souring/sinking strength (SCFG_UHDRV) Register Reset value Type Description Bit 31:7 Reserved 0x0000 000 resd Kept at its default value. PD13 Ultra high sourcing/sinking strength This bit is written by software to control PD13 PAD sourcing/sinking strength. -
Page 120: External Interrupt/Event Controller (Exint)
AT32F423 Series Reference Manual External interrupt/event controller (EXINT) 8.1 EXINT introduction EXINT consists of 25 interrupt lines EXINT_LINE[28:0] (in which 19, 20, 24 and 27 bits are reserved), each of which can generate an interrupt or event by edge detection trigger or software trigger. EXINT... -
Page 121: Exint Registers
AT32F423 Series Reference Manual Interrupt initialization procedure Select an interrupt by setting the SCFG_EXINTCx register (this is required if GPIO is used as an interrupt source); Select a trigger mode by setting the EXINT_POLCFG1 and EXINT_POLCFG2 registers; ... -
Page 122: Polarity Configuration Register 2 (Exint_Polcfg2)
AT32F423 Series Reference Manual 8.3.4 Polarity configuration register 2 (EXINT_POLCFG2) Register Reset value Type Description Bit 31:29 Reserved resd Forced to 0 by hardware. Falling polarity event configuration bit of line x These bits are used to select a falling edge to trigger an interrupt and event on line x. -
Page 123: Dma Controller (Dma)
AT32F423 Series Reference Manual DMA controller (DMA) 9.1 Introduction Direct memory access (DMA) controller is designed for high speed data transmission between peripherals and memory or between memories. The data can be transmitted through DMA at a high speed without CPU interference, which saves CPU capacity. -
Page 124: Handshake Mechanism
AT32F423 Series Reference Manual Programmable data transfer size is up to 65535. This value is decremented after each data transfer. Configure the channel setting in the DMA_CHCTRLx register Including channel priority, data transfer direction/width, address incremented mode, circular mode and... -
Page 125: Errors
AT32F423 Series Reference Manual Figure 9-3 PWIDTH: byte, MWIDTH: half-word 4-word FIFO AHB Read Sequence AHB Write Sequence HW3 HW2 HW1 HW0 Half-word2 Half-word0 Half-word3 Half-word1 Figure 9-4 PWIDTH: half-word, MWIDTH: word 4-word FIFO AHB Read Sequence AHB Write Sequence... -
Page 126: Interrupts
AT32F423 Series Reference Manual 9.3.6 Interrupts An interrupt can be generated on a DMA half-transfer, transfer complete and transfer error. Each channel has its specific interrupt flag, clear and enable bits, as shown in the table below Table 9-2 DMA interrupts... -
Page 127: Table 9-3 Flexible Dma1 / Dma2 Request Mapping
AT32F423 Series Reference Manual Table 9-3 Flexible DMA1 / DMA2 request mapping CHx_ CHx_ CHx_ CHx_ Request source Request source Request source Request source DMA_MUXREQG1 33 USART5_TX TMR3_OVERFLOW 97 TMR12_TRIG DMA_MUXREQG2 34 reserved TMR3_TRIG TMR12_HALL DMA_MUXREQG3 35 reserved TMR4_CH1 reserved... -
Page 128: Dmamux Overflow Interrupts
AT32F423 Series Reference Manual Table 9-4 DMAMUX EXINT LINE for trigger input and synchronized input EXINT EXINT EXINT EXINT Source Source Source Source LINE LINE LINE LINE reserved exint_gpio[0] exint_gpio[8] DMA_MUXevt1 DMA_MUXevt2 reserved exint_gpio[1] exint_gpio[9] DMA_MUXevt3 reserved exint_gpio[2] exint_gpio[10] DMA_MUXevt4... -
Page 129: Dma Registers
AT32F423 Series Reference Manual Figure 9-8 DMAMUX event generation Selected all_req[n] chx_mux_req SYNCEN EVTGEN mux_req_cnt mux_evtx SYNCEN = 0, EVTGEN = 1, REQCNT = 2 9.5 DMA registers The table below lists DMA register map and their reset values. These peripheral registers can be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits). -
Page 130: Dma Interrupt Status Register (Dma_Sts )
AT32F423 Series Reference Manual DMA_C6PADDR 0x74 0x0000 0000 DMA_C6MADDR 0x78 0x0000 0000 DMA_C7CTRL 0x80 0x0000 0000 DMA_C7DTCNT 0x84 0x0000 0000 DMA_C7PADDR 0x88 0x0000 0000 DMA_C7MADDR 0x8c 0x0000 0000 DMA_MUXSEL 0x100 0x0000 0000 DMA_MUXC1CTRL 0x104 0x0000 0000 DMA_MUXC2CTRL 0x108 0x0000 0000... - Page 131 AT32F423 Series Reference Manual Channel 6 transfer complete event flag Bit 21 FDTF6 0: No transfer complete event occurred 1: Transfer complete event occurred Channel 6 global event flag 0: No transfer error, half transfer or transfer complete Bit 20...
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Page 132: Dma Interrupt Flag Clear Register (Dma_Clr)
AT32F423 Series Reference Manual Channel 1 half transfer event flag Bit 2 HDTF1 0: No half-transfer event occurred 1: Half-transfer event occurred Channel 1 transfer complete event flag Bit 1 FDTF1 0: No transfer complete event occurred 1: Transfer complete event occurred... - Page 133 AT32F423 Series Reference Manual Channel 4 half transfer flag clear Bit 14 HDTFC4 rw1c 0: No effect 1: Clear the HDTF4 flag in the DMA_STS register Channel 4 transfer complete flag clear Bit 13 FDTFC4 rw1c 0: No effect 1: Clear the FDTF4 flag in the DMA_STS register...
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Page 134: Dma Channel-X Configuration Register (Dma_Cxctrl) (X = 1
AT32F423 Series Reference Manual 9.5.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…7) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Bit 31:15 Reserved 0x00000 resd Kept at its default value. Memory to memory mode... -
Page 135: Dma Channel-X Peripheral Address Register (Dma_Cxpaddr)
AT32F423 Series Reference Manual 9.5.5 DMA channel-x peripheral address register (DMA_CxPADDR) (x = 1…7) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Peripheral base address Base address of peripheral data register is the source or... -
Page 136: Dmamux Generator-X Control Register (Dma_Muxgxctrl
AT32F423 Series Reference Manual Event generate enable Bit 9 EVTGEN 0: Disabled 1: Enabled Synchronization overrun interrupt enable Bit 8 SYNCOVIEN 0: Interrupt disabled 1: Interrupt enabled Bit 7 Reserved resd Kept at its default value. DMA request select flag... -
Page 137: Dmamux Channel Interrupt Clear Register (Dma_Muxsyncclr)
AT32F423 Series Reference Manual 9.5.11 DMAMUX channel interrupt clear register (DMA_MUXSYNCCLR) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Bit 31:8 Reserved 0x0000 00 resd Kept at its default value. Synchronization overrun interrupt flag clear... -
Page 138: Crc Calculation Unit (Crc)
AT32F423 Series Reference Manual 10 CRC calculation unit (CRC) 10.1 CRC introduction The Cyclic Redundancy Check (CRC) is an independent peripheral with CRC check feature. It follows CRC32/MPEG-2 standard. The CRC_CTRL register is used to select output data toggle (word, REVOD=1) or input data toggle (byte, REVID=01;... -
Page 139: Crc Registers
AT32F423 Series Reference Manual CRC-32/MPEG-2 parameters: Generating polynomial: 0x4C11DB7, �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + �� + 1 Initial value is 0xFFFF FFFF, to avoid obtaining the same calculation result for 1 byte 0x00 and ... -
Page 140: Control Register (Crc_Ctrl)
AT32F423 Series Reference Manual 10.3.3 Control register (CRC_CTRL) Register Reset value Type Description Bit 31:8 Reserved 0x000000 resd Kept at its default value. Reverse output data Set and cleared by software. This bit is used to control Bit 7 REVOD resd whether or not to reverse output data. -
Page 141: C Interface
AT32F423 Series Reference Manual 11 I C interface 11.1 I C instruction C (inter-integrated circuit) bus interface manages the communication between the microcontroller and serial I C bus. It supports master and slave modes, with up to 1 Mbit/s of communication speed (enhanced edition). -
Page 142: I 2 C Interface
AT32F423 Series Reference Manual 11.4 I C interface The figure below shows the block diagram of I C interface. Figure 11-2 I C1 interface block diagram SYSCLK I2CCLK PCLK Clock Control HICK TIMEOUT_Frozen I2C_SCL_out Master clock generation CPU_Halt_en Slave clock... - Page 143 AT32F423 Series Reference Manual Slave mode communication: Wait until the address is matched Data Tx or Rx Wait for the generation of Stop condition End of communication Digital filter capability The digital filter is available on both SCL and SDA lines. It is enabled by setting the DFLT[3: 0] bit (0~15) in the I2C_CTRL1 register to reduce noise on bus on a large scale.
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Page 144: C Timing Control
AT32F423 Series Reference Manual Data reception: the shift register receives a new data before the data in the I2C_RXDT register has been read. In this case, the SCL line is pulled low until the data of the I2C_RXDT register is read. - Page 145 AT32F423 Series Reference Manual It is possible to configure data hold time (t ) and data setup time (t ) freely by setting the DIV[7:0], HD;DAT SU;DAT SDAD[3:0] and SCLD[3:0] in the I2C_CLKCTRL register. Data hold time (t ): refers to the duration from SCL falling edge to SDA output HD;DAT...
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Page 146: Data Transfer Management
AT32F423 Series Reference Manual Table 11-1 I C timing specifications Standard mode Fast mode Fast mode plus SMBus Parameter Min. Max. Min. Max. Min. Max. Min. Max. (kHz) SCL clock frequency 1000 (us) SCL clock low (us) SCL clock high 0.26... -
Page 147: I 2 C Master Communication Flow
AT32F423 Series Reference Manual This feature is enabled by setting the SCTRL bit in the I2C_CTRL2 register so that the slave is able to control ACK/NACK signals of each byte independently. Proceed as below: ― Set SCTRL=1 to enable Byte Control Through Slave ―... - Page 148 AT32F423 Series Reference Manual Set slave address ― Set slave address value (by setting the SADDR bit in the I2C_CTRL2 register) ― Set slave address mode (by setting the ADDR10 bit in the I2C_CTRL2 register) ADDR10=0: 7-bit address mode ADDR10=1: 10-bit address mode Set transfer direction (by setting the DIR bit in the I2C_CTRL2 register) ―...
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Page 149: Figure 11-5 I 2 C Master Transmission Flow
AT32F423 Series Reference Manual Master transmitter Figure 11-5 I C master transmission flow Master initialization Set I2C_CTRL2_CNT = N , ( if N > 255 , CNT = 0xFF, N=N- 255 ,RLDEN = 1) ,Configure slave address, and GENSTART = 1. -
Page 150: Figure 11-6 Transfer Sequence Of I
AT32F423 Series Reference Manual Figure 11-6 Transfer sequence of I C master transmitter Example : I2C master transmitter N bytes . Initial setting flow : 1. I2C_CTRL2_CNT = N 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL2_GENSTART = 1... -
Page 151: Figure 11-8 Transfer Sequence Of I
AT32F423 Series Reference Manual Figure 11-8 Transfer sequence of I C master receiver Example : I2C master receiver N bytes . Initial setting flow : 1. I2C_CTRL2_CNT = N 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL2_GENSTART = 1... -
Page 152: I 2 C Slave Communication Flow
AT32F423 Series Reference Manual Figure 11-10 10-bit address read access when READH10=0 A8 r/w A4 A3 A8 r/w Slave address Slave address 2nd Byte Write Read S = Start Master to Slave RS= restart Data Data A = Acknowledge P = Stop Slave to Master 11.4.4... - Page 153 AT32F423 Series Reference Manual register. At the end of data transfer, the STOPF is cleared by writing 1 to the STOPC, transmission ends. In the case of the clock stretching being disabled (STRETCH=1), if data has not yet been written to...
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Page 154: Figure 11-11 I 2 C Slave Transmission Flow
AT32F423 Series Reference Manual Slave transmitter Figure 11-11 I C slave transmission flow Slave initialization (if STRETCH =1, write data to I2C_TXDT_DT ) I2C_STS_ADDRF=1? Read ADDR and SDIR in I2C_STS Optional : Set I2C_STS_TDBE = 1 Set I2C_CLR_ADDRC =1 I2C_STS_ACKFAIL=1? -
Page 155: Figure 11-13 I 2 C Slave Receive Flow
AT32F423 Series Reference Manual Slave receiver Figure 11-13 I C slave receive flow Slave initialization I2C_STS_ADDRF=1? Read ADDR and SDIR in I2C_STS Set I2C_CLR_ADDRC =1 I2C_STS_STOPF=1? I2C_STS_RDBF=1? Set I2C_CLR_STOPC Read I2C_RXDT_DT Figure 11-14 I C slave receive timing Example : I2C Slave receiver Nbytes from I2C master . -
Page 156: Smbus
AT32F423 Series Reference Manual 11.4.5 SMBus The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other. It is based on I C. With SMBus, the device can provide manufacturer information, tell the system its model/part number, report different types of errors and accept control parameters and so on. -
Page 157: Table 11-3 Smbus Timeout Specification
AT32F423 Series Reference Manual PEC transfer: ― Host: PEC transfer is enabled by setting PECTEN=1 in the I2C_CTRL2 register. The host sends a PEC as soon as the number of data transfer reaches N-1 (CNT=N) ― Slave: PEC transfer is enabled by setting PECTEN=1 in the I2C_CTRL2 register. When the number of data transfer reaches N-1 (CNT=N), the slave will consider the Nth data as a PEC and check it. -
Page 158: Smbus Master Communication Flow
AT32F423 Series Reference Manual Table 11-5 SMBus mode configuration Transfer mode PECEN PECTEN RLDEN ASTOPEN SCTRL Master transmit/receive +STOP Master transmit/receive +RESTART Slave receive Slave transmit How to use the interface in SMBus mode Set SMBus default address acknowledgement: HADDREN=1: Master default address acknowledged (0b0001000x) -
Page 159: Figure 11-15 Smbus Master Transmission Flow
AT32F423 Series Reference Manual register. The ADDRF flag can be cleared by setting ADDRC=1 in the I2C_CLR register, and then data transfer starts. Master transmit I2C_TXDT data register is empty, the shift register is empty, TDIS=1 in the I2C_STS register... -
Page 160: Figure 11-16 Smbus Master Transmission Timing
AT32F423 Series Reference Manual Figure 11-16 SMBus master transmission timing Example : SMBus master receiver N bytes +PEC . Initial setting flow : 1. I2C_CTRL2_CNT = N+ 1 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_PECTEN = 1 4. I2C_CTRL2_GENSTART = 1... -
Page 161: Smbus Slave Communication Flow
AT32F423 Series Reference Manual Figure 11-18 SMBus master receive timing SMBus master receiver N bytes +PEC Initial setting flow : 1. I2C_CTRL2_CNT = N+ 1 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL1_PECEN = 1 5. I2C_CTRL2_PECTEN = 1 6. - Page 162 AT32F423 Series Reference Manual ― Slave receive: by setting RLDEN=1 in the I2C_CTRL2 register The ADDRF flag can be cleared by setting ADDRC=1 in the I2C_CLR register, and then data transfer starts. Data transfer (slave transmission, clock stretching enabled, STRETCH=0)
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Page 163: Figure 11-19 Smbus Slave Transmission Flow
AT32F423 Series Reference Manual SMBus slave transmitter Figure 11-19 SMBus slave transmission flow Slave initialization I2C_STS_ADDRF=1? Set I2C_CTRL2_CNT =N+ 1 I2C_CTRL2_PECTEN = 1 I2C_CLR_ADDRC =1 I2C_STS_TDIS=1? Write I2C_TXDT_DT 2023.04.25 Page 163 Rev 2.01... -
Page 164: Figure 11-20 Smbus Slave Transmission Timing
AT32F423 Series Reference Manual Figure 11-20 SMBus slave transmission timing Example : SMBus slave transmitter N bytes + PEC Address Data1 Data2 DataN Stretch TDIS EV1.I2C_STS_ADDRF = 1 ,set I2C_CTRL2 CNT = N+1, PECTEN = 1 , Master to Slave... -
Page 165: Data Transfer Using Dma
AT32F423 Series Reference Manual Figure 11-22 SMBus slave receive timing Example : SMBus slave receiver N bytes +PEC Address Data1 Data2 DataN Stretch RDBF EV1. I2C_STS_ADDR =1, Set I2C_CTRL2 CNT = N+1 ,PECTEN = 1,and set S = Start Master to Slave... -
Page 166: Error Management
AT32F423 Series Reference Manual 11.4.9 Error management The error management feature included in the I C provides a guarantee for the reliability of communication. The manageable error events are listed below: Table 11-6 I C error event Error event Event flag... -
Page 167: Wakeup From Deepsleep Mode At Address Matching Event
AT32F423 Series Reference Manual In master receive mode, an NACK is always sent, whatever the PEC check result. SMBus alert (ALERTF) The SMBus alert feature is present when HADDREN=1 (SMBus master mode) and SMBALERT=1 (SMBus alert mode).Once an alert event is detected on the ALERT pin (ALERT pin changes from high to low), the ALERTF bit is set by hardware in the I2C_STS register. -
Page 168: I 2 C Debug Mode
AT32F423 Series Reference Manual Overrun/underrun Arbitration lost ARLOST Bus error BUSERR 11.6 I C debug mode When the microcontroller enters debug mode (Cortex -M4 halted), the SMBUS timeout either continues to work or stops, depending on the I2Cx_SMBUS_TIMEOUT configuration bit in the DEBUG module. -
Page 169: Control Register 2 (I2C_Ctrl2)
AT32F423 Series Reference Manual 0: Clock stretching mode enabled 1: Clock stretching mode disabled Note: It is valid in slave mode only. Slave receiving data control Bit 16 SCTRL 0: Slave receiving data control disabled 1: Slave receiving data control enabled... -
Page 170: Own Address Register 1 (I2C_Oaddr1)
AT32F423 Series Reference Manual 10-bit address header read enable Bit 12 READH10 0: 10-bit address header read disabled 1: 10-bit address header read enabled Host send 10-bit address mode enable Bit 11 ADDR10 0: 7-bit address mode 1: 10-bit address mode... -
Page 171: Timeout Register (I2C_Timeout)
AT32F423 Series Reference Manual 11.7.6 Timeout register (I2C_TIMEOUT) Register Reset value Type Description Cumulative clock low extend timeout enable 0: Cumulative clock low extend timeout disabled Bit 31 EXTEN 1: Cumulative clock low extend timeout enabled Corresponds to T in SMBus... -
Page 172: Status Clear Register (I2C_Clr)
AT32F423 Series Reference Manual 0: No Bus error occurred 1: Bus error occurred Transmission is complete, waiting to load data 0: Data transfer is not complete yet 1: Data transfer is complete This bit is set when data transfer is complete (CNT=1) -
Page 173: Pec Register (I2C_Pec)
AT32F423 Series Reference Manual Clear 0~7 bit address match flag Bit 3 ADDRC The 0~7 bit address match flag is cleared by writing 1. Bit 2:0 Reserved Kept at its default value. 11.7.9 PEC register (I2C_PEC) Register Reset value Type... -
Page 174: Universal Synchronous/Asynchronous Receiver/Transmitter (Usart)
AT32F423 Series Reference Manual 12 Universal synchronous/asynchronous receiver/transmitter (USART) 12.1 USART introduction The universal synchronous/asynchronous receiver/transmitter (USART) serves an interface for communication by means of various configurations and peripherals with different data formats. It supports asynchronous full-duplex and half-duplex as well as synchronous transfer. With a programmable baud rate generator, USART offers up to 7.5 Mbits/s of baud rate by setting the system... -
Page 175: Full-Duplex/Half-Duplex Selector
AT32F423 Series Reference Manual ─ RS-232 CTS/RTS (Clear To Send/Request To Send) hardware flow operation ─ RS-485 ─ Multi-processor communication with silent mode (waken up by configuring ID match and bus idle frame) ─ Synchronous mode Programmable baud rate generator ─... -
Page 176: Mode Selector
AT32F423 Series Reference Manual LINEN, CLKEN, SCMEN and IRDAEN bits must be set 0. RX pin is inactive, while TX and SW_RX are interconnected inside the USART. For the USART part, TX pins is used for data output, and SW_RX for data input. -
Page 177: Figure 12-3 Smartcard Frame Format
AT32F423 Series Reference Manual select whether to send NACK when a parity error occurs. This is to indicate to the Smartcard that the data has not been correctly received. Figure 12-3 Smartcard frame format Without Parity error： Start Guard time... -
Page 178: Figure 12-5 Hardware Flow Control
AT32F423 Series Reference Manual Figure 12-5 Hardware flow control RTS flow control: frame0 frame1 RX pin CTS flow control： frame0 frame1 frame2 TX pin 6. RS485 mode This mode is enabled by setting RS485EN=1. The enable signal is output on the RTS pin. The DEP bit is used to select the polarity of the DE signal. -
Page 179: Usart Frame Format And Configuration
AT32F423 Series Reference Manual 8. Synchronous mode Setting the CLKEN bit enables synchronous mode and clock pin output. Select CK pin high or low in idle state by setting the CLKPOL bit (1 or 0). Whether to sample data on the second or first edge of the clock depends on the CLKPHA bit (1 or 0). -
Page 180: Figure 12-8 Word Length Configuration
AT32F423 Series Reference Manual Figure 12-8 Word length configuration 9-bit word length (DBN1, DBN0 = 01)： Clock PEN = 1, Next Data frame Next Data frame Parity bit Start Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8... -
Page 181: Dma Transfer Introduction
AT32F423 Series Reference Manual Figure 12-9 Stop bit configuration Clock PEN = 1, Next STOPBN = 00 Data frame Parity bit Start Start 1 Stop bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6... -
Page 182: Reception Using Dma
AT32F423 Series Reference Manual 12.5.2 Reception using DMA 1. Select a DMA transfer channel: Select a DMA channel from DMA channel map table described in DMA chapter. 2. Configure the destination of DMA transfer: Configure the memory address as the destination of DMA transfer in the DMA control register. -
Page 183: Transmitter
AT32F423 Series Reference Manual 12.7 Transmitter 12.7.1 Transmitter introduction USART transmitter has its individual TEN control bit. The transmitter and receiver share the same baud rate that is programmable. There is a transmit data buffer (TDR) and a transmit shift register in the USART. -
Page 184: Receiver
AT32F423 Series Reference Manual 12.8 Receiver 12.8.1 Receiver introduction USART receiver has its individual REN control bit (bit 2 in the USART_CTRL1 register). The transmitter and receiver share the same baud rate that is programmable. There is a receive data buffer (RDR) and a receive shift register in the USART. -
Page 185: Start Bit And Noise Detection
AT32F423 Series Reference Manual The content in the receive shift register is overwritten. Afterwards, any data received will be lost. An interrupt is generated if the RDBFIEN is set or both ERRIEN and DMAREN are set. The ROERR bit is cleared by reading the USART_STS register and then USART_DT register in... -
Page 186: Low-Power Wakeup
AT32F423 Series Reference Manual Figure 12-11 Data sampling for noise detection one bit time RX pin Oversampling Sample bits 12.9 Low-power wakeup USART supports low-power wakeup. Before entering DEEPSLEEP mode, the software should guarantee that the USART_CLK is clocked by HICK and LEXT, confirm no transmission by checking the OCCUPY bit, verify the completion of USART receiver initialization by checking the RXON bit, and finally set SMUSEN=1 to enable USART in DEEPSLEEP mode. -
Page 187: Interrupt Requests
AT32F423 Series Reference Manual Figure 12-12 Tx/Rx swap USART_TX USART_TX USART_RX USART_RX USART USART TRPSWAP=0 TRPSWAP=1 Note: The SWAP (USART_CTRL2[15]) can be modified only when the USART is disabled (UEN=0) 12.11 Interrupt requests USART interrupt generator serves as a control center of USART interrupts. It is used to monitor the interrupt source inside the USART in real time and the generation of interrupts according to the programmed interrupt control bits. -
Page 188: I/O Pin Control
AT32F423 Series Reference Manual 12.12 I/O pin control The following five interfaces are used for USART communication. RX: Serial data input. TX: Serial data output. In single-wire half-duplex and Smartcard mode, the TX pin is used as an I/O for data transmission and reception. - Page 189 AT32F423 Series Reference Manual Bit 11 RTODF Receiver timeout detection flag This bit is set by hardware when the timeout value reaches the programmed value in RTOV register and without any communication. It is cleared by software. 0: No timeout detected...
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Page 190: Data Register (Usart_Dt)
AT32F423 Series Reference Manual USART_DT read operation) 0: No parity error occurs 1: Parity error occurs 12.13.2 Data register (USART_DT) Register Reset value Type Description Bit 31:9 Reserved 0x000000 resd Forced to 0 by hardware. Data value This register provides read and write function. When... - Page 191 AT32F423 Series Reference Manual 0: Waken up by idle line 1: Waken up by ID match Parity enable This bit is used to enable hardware parity control (generation of parity bit for transmission; detection of parity bit for reception). When this bit is enabled, the MSB Bit 10 bit of the transmitted data is replaced with the parity bit;...
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Page 192: Control Register 2 (Usart_Ctrl2)
AT32F423 Series Reference Manual 12.13.5 Control register 2 (USART_CTRL2) Register Reset value Type Description USART identification Bit 31:28 This field holds the upper four bits of USART ID. It is configurable Bit 27:20 Reserved 0x000 resd Kept at its default value. -
Page 193: Control Register 3 (Usart_Ctrl3)
AT32F423 Series Reference Manual 1: Data bit - 1 bit Note: When this bit is set, in 7, 8 or 9-bit data mode, the ID bit number is the lower 6, 7 or 8 bit, respectively. USART identification Bit 3:0 This field holds the lower four bits of USART ID. -
Page 194: Guard Time And Divider Register (Gdiv)
AT32F423 Series Reference Manual This bit is used to configure IrDA low-power mode. 0: IrDA low-power mode is disabled. 1: IrDA low-power mode is enabled. IrDA enable Bit 1 IRDAEN 0: IrDA is disabled. 1: IrDA is enabled. Error interrupt enable... -
Page 195: Serial Peripheral Interface (Spi)
AT32F423 Series Reference Manual 13 Serial peripheral interface (SPI) 13.1 SPI introduction The SPI interface supports either the SPI protocol or the I S protocol, depending on software configuration. This chapter gives an introduction of the main features and configuration procedure of SPI used as SPI or I 13.2 Functional overview... -
Page 196: Full-Duplex/Half-Duplex Selector
AT32F423 Series Reference Manual Programmable 8-bit or 16-bit frame format Programmable communication frequency and prescaler (prescaler up to f PCLK Programmable clock polarity and phase Programmable data transfer order (MSB-first or LSB-first) Programmable error interrupt flags (CS pulse error, receiver overflow error, master mode error and CRC error) ... -
Page 197: Figure 13-3 Single-Wire Unidirectional Receive Only In Spi Master Mode
AT32F423 Series Reference Manual Figure 13-3 Single-wire unidirectional receive only in SPI master mode SPI master SPI slave MISO MISO MOSI MOSI Figure 13-4 Single-wire unidirectional receive only in SPI slave mode SPI master SPI slave MISO MISO MOSI MOSI In master mode, it is required to wait until the second to last RDBF bit is set and then one SPI_CPK clock before disabling the SPI. -
Page 198: Chip Select Controller
AT32F423 Series Reference Manual In both master and slave mode, when the SPI is selected for data transmission in single-wire bidirectional half-duplex mode, the TDBE bit must be set, and the BF must be 0 before disabling the SPI. The power- saving mode (or disabling SPI system clock) cannot be entered unless the SPI is disabled. -
Page 199: Crc
AT32F423 Series Reference Manual Note that the clock output is activated after the SPI is enabled in master reception-only mode, and it remains there until when the SPI is disabled and the reception is complete. 13.2.5 CRC The SPI interface provides separate CRC calculation unit for transmission and reception. When used as SPI through software configuration, the automatic CRC calculation and check is performed while the user is reading or writing through DMA or CPU. -
Page 200: Dma Transfer
AT32F423 Series Reference Manual 13.2.6 DMA transfer The SPI supports write and read operations with DMA. Refer to the following configuration procedure. Special attention should be paid to: when the CRC calculation and check is enabled, the number of data transferred by DMA is configured as the number of the data to be transferred plus 1. The number of data read with DMA is configured as the number of the data to be received. -
Page 201: Transmitter
AT32F423 Series Reference Manual a CS pulse error is detected. At this point, the detected erroneous pulse will be ignored by the SPI. However, since there is something wrong with the CS signal, the software should disable the SPI slave and re-configure the SPI master before re-enabling the SPI slave for communication. -
Page 202: Motorola Mode
AT32F423 Series Reference Manual Receiver configuration procedure: Configure full-duplex/half-duplex selector Configure chip select controller Configure SPI_SCK controller Configure CRC (if necessary) Configure DMA transfer (if necessary) If the DMA transfer mode is not used, the software will check whether to enable receive data interrupt (RDBEIE =1) through the RDBE bit. -
Page 203: Figure 13-7 Slave Full-Duplex Communications
AT32F423 Series Reference Manual Figure 13-7 Slave full-duplex communications Sampling Drive MISO MOSI TDBE flag Transmit buffer empty and RDBF flag software can write data BF flag Software needs to read the received data Half-duplex communication – master transmit timing... -
Page 204: Ti Mode
AT32F423 Series Reference Manual CLKPOL=0, CLKPHA=0: SCK idle output low, use the first edge for sampling FBN=0: 8-bit frame Slave transmit: 0xaa, 0xcc, 0xaa Figure 13-10 Slave half-duplex transmit Drive MISO Transmit buffer empty and TDBE flag software can write data BF flag Half-duplex communication –... -
Page 205: Interrupts
AT32F423 Series Reference Manual Figure 13-13 TI mode continous transfer with dummy CLK Write the to-be-transmitted data MISO MOSI dummy In TI mode, when the to-be-transmitted data is written after the falling SCK edge corresponding to the last data of the current transmit frame, the host always issues a valid SCK clock after 1T SCK + 4T PCLK cycles. -
Page 206: I 2 S Functional Description
AT32F423 Series Reference Manual 13.3 I S functional description 13.3.1 I S introduction The I S is capable of operating in master receive, master transmit, and slave receive and slave transmit, depending on software configuration. These four operating modes support four audio protocols including Philips standard, MSB-aligned standard, LSB-aligned standard and PCM standard, respectively. -
Page 207: I S Full-Duplex
AT32F423 Series Reference Manual Main peripheral clock with a fixed frequency of 256x Fs (audio sampling frequency) 13.3.2 I S full-duplex Two SPIs can be combined to support I S full-duplex mode through the SCFG_CFG2[31:30] bit in the SCFG register. Of the three SPIs, either SPI1 or SPI2 can be configured as full-duplex master, while the SPI2 or SPI3 can be set as full-duplex slave, which is selected through the SCFG_CFG2[31:30] bit in the SCFG register. -
Page 208: Figure 13-18 I 2 S Slave Device Transmission
AT32F423 Series Reference Manual Figure 13-18 slave device transmission I2S master I2S slave Slave device reception: Set the I2SMSEL bit, and OPERSEL[1:0]=01, the I S will work in slave device reception mode. Figure 13-19 slave device reception I2S master I2S slave... -
Page 209: Audio Protocol Selector
AT32F423 Series Reference Manual Figure 13-21 I S master device reception I2S master I2S slave 13.3.4 Audio protocol selector As I S interface, the SPI supports multiple audio protocols. The user is able to select the desired audio protocol, the number of data bits and of channel bits through the audio protocol selector by software. By controlling the WS controller automatically, the audio protocol selector outputs or detects WS signals that conform to the protocol requirements. -
Page 210: I2S_Clk Controller
AT32F423 Series Reference Manual The data bits are the same as the channel bits. Each channel requires two read/write operations from/to the SPI_DT register, and the number of DMA transfer is 2. These 32-bit data are proceeded (transmit and reception) in two times, with 16-bit data each time. -
Page 211: Dma Transfer
AT32F423 Series Reference Manual Table 13-1 Audio frequency precision using system clock 16bit 32bit Target SCLK (MHz) I2S_ODD RealFs Error I2S_ODD RealFs Error (Hz) 192000 187500 2.34% 187500 2.34% 96000 97826.09 1.90% 93750 2.34% 48000 34615.38 27.88% 48913.04 1.90% 44100 44117.65... -
Page 212: Transmitter/Receiver
AT32F423 Series Reference Manual Configure the total number of bytes to be transferred in the DMA control register. Configure DMA interrupt generation after half or full transfer in the DMA control register Enable DMA transfer channel in the DMA control register. -
Page 213: Interrupts
AT32F423 Series Reference Manual 13.3.8 Interrupts Figure 13-23 I S interrupts RDBF RDBFIE TDBE TDBEIE I2S interrupt ERRIE ROERR TUERR 13.3.9 IO pin control The I S needs three pins for transfer operation, namely, the SD, WS and CK. The MCLK pin is also required if there is a need to provide main clock for peripherals. - Page 214 AT32F423 Series Reference Manual mode. 0: Receive-only mode 1: Transmit-only mode RC calculation enable Bit 13 CCEN 0: Disabled 1: Enabled Transmit CRC next When this bit is set, it indicates that the next data Bit 12 transferred is CRC value.
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Page 215: Spi Control Register2 (Spi_Ctrl2)
AT32F423 Series Reference Manual 0: Data capture starts from the first clock edge 1: Data capture starts from the second clock edge Note: The SPI_CTRL1 register must be 0 in I S mode. 13.4.2 SPI control register2 (SPI_CTRL2) Register Reset value... -
Page 216: Spi Data Register (Spi_Dt)
AT32F423 Series Reference Manual 0: SPI is not busy. 1: SPI is busy. Receiver overflow error Bit 6 ROERR 0: No overflow error 1: Overflow error occurs. Master mode error This bit is set by hardware and cleared by software... -
Page 217: Spitxcrc Register (Spi_Tcrc)
AT32F423 Series Reference Manual SPI_CTRL1 register is cleared. When the data frame format is set to 8-bit data, only the 8-bit LSB ([7: 0]) are calculated based on CRC8 standard; when 16-bit data bit is selected, follow CRC16 standard. Note: This register is only used in SPI mode. -
Page 218: Spi_I2S Prescaler Register (Spi_I2Sclkp)
AT32F423 Series Reference Manual 13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) Register Reset value Type Description Bit 15: 12 Reserved resd Forced 0 by hardware. S Master clock output enable Bit 9 I2SMCLKOE 0: Disabled 1: Enabled Odd factor for I S division... -
Page 219: Timer
AT32F423 Series Reference Manual 14 Timer AT32F423 timers include basic timers, general-purpose timers, and advanced timers. Please refer to Section 14.1 Section 14.5 for detailed function modes. All functions of different timers are shown in the following tables. Table 14-1 TMR functional comparison... -
Page 220: Basic Timer (Tmr6 And Tmr7)
AT32F423 Series Reference Manual 14.1 Basic timer (TMR6 and TMR7) 14.1.1 TMR6 and TMR7 introduction Basic timers (TMR6 and TMR7) include a 16-bit up counter and the corresponding control logic, without being connected to external I/Os. They can be used for basic timing function. -
Page 221: Debug Mode
AT32F423 Series Reference Manual overflow or underflow occurs. Setting the TMREN bit (TMREN=1) enables the timer to start counting. Base on synchronization logic, however, the actual counter enable signal TMR_EN is set 1 clock cycle after the TMREN is set. -
Page 222: Tmr6 And Tmr7 Registers
AT32F423 Series Reference Manual 14.1.4 TMR6 and TMR7 registers These peripheral registers have to be accessed by words (32 bits). In Table 14-2, all the TMR6 and TMR7 registers are mapped to a 16-bit addressable space. Table 14-2 TMR6 and TMR7 register table and reset value... -
Page 223: Tmr6 And Tmr7 Control Register2 (Tmrx_Ctrl2)
AT32F423 Series Reference Manual 14.1.4.2 TMR6 and TMR7 control register2 (TMRx_CTRL2) Register Reset value Type Description Bit 15: 7 Reserved 0x000 resd Kept at default value. Master TMR output selection This field is used to select the signals in master mode to be sent to slave timers. -
Page 224: Tmr6 And Tmr7 Period Register (Tmrx_Pr)
AT32F423 Series Reference Manual 14.1.4.8 TMR6 and TMR7 period register (TMRx_PR) Register Reset value Type Description Period value Bit 15: 0 0x0000 This indicates the period value of the TMRx counter. The timer stops working when the period value is 0. -
Page 225: General-Purpose Timer (Tmr2 To Tmr4)
AT32F423 Series Reference Manual 14.2 General-purpose timer (TMR2 to TMR4) 14.2.1 TMR2 to TMR4 introduction The general-purpose timers (TMR2 to TMR4) consist of a 16-bit counter supporting up, down, up/down (TMR2 can be extended to 32 bits) counting modes, four capture/compare registers, and four independent channels. -
Page 226: Figure 14-9 Control Circuit With Ck_Int, Tmrx_Div=0X0 And Tmrx_Pr=0X16
AT32F423 Series Reference Manual Internal clock (CK_INT) By default, the CK_INT, which is divided by a prescaler, is used to drive the counter to count. Follow the procedures below: – Select a counting mode by setting the TWCMSEL[1:0] in TMRx_CTRL1 register. If a unidirectional aligned counting mode is selected, it is necessary to select a counting direction through the OWCDIR bit in TMRx_CTRL1 register. -
Page 227: Figure 14-10 Block Diagram Of External Clock Mode A
AT32F423 Series Reference Manual – Set external signal frequency division through the ESDIV[1:0] bit in TMRx_STCTRL register – Set external signal filter through the ESF[3:0] bit in TMRx_STCTRL register – Enable external clock mode B through the ECMBEN bit in TMRx_STCTR register –... -
Page 228: Counting Mode
AT32F423 Series Reference Manual be provided by the TRGOUT signal from another timer. The internal trigger signal is selected by setting the STIS[2: 0] bit to enable counting. TMR2 to TMR4 consist of a 16-bit prescaler, which is used to generate the CK_CNT that enables the counter to count. -
Page 229: Figure 14-5 Overflow Event When Prben=1
AT32F423 Series Reference Manual mode timer controller in reset mode. Once the OVFS is set, an overflow event is generated only when overflow or underflow occurs. Setting the TMREN bit (TMREN=1) enables the timer to start counting. Base on synchronization logic, however, the actual enable signal TMR_EN is set 1 clock cycle after the TMREN is set. -
Page 230: Figure 14-19 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32
AT32F423 Series Reference Manual TMR_CLK CNT_CLK COUNTER PR[15：0] DIV[15：0] OVFIF Clear Up/down counting mode (center-aligned mode) This mode is selected by setting CMSEL[1:0]≠2’b00 in the TMRx_CTRL1 register. In up/down counting mode, the counter counts up/down alternatively. When the counter counts from the value programmed in the TMRx_PR register down to 1, an underflow event is generated, and then restarts counting from 0;... -
Page 231: Figure 14-21 Example Of Counter Behavior In Encoder Interface Mode (Encoder Mode C)
AT32F423 Series Reference Manual SMSEL=3'b001/010/011 encoder mode filter polarity select TMRx_CH2 C2IRAW C2DF C2IFP2 director C1DF C1IFP1 TMRx_CH3 polarity select filter edge C1IRAW TMRx_CH1 detector preload pos/neg edge C1INSEL TMRx_DIV encoder mode A encoder DIV counter DIV_CLK Overflow event mode B... -
Page 232: Tmr Input Function
AT32F423 Series Reference Manual DOWN C1IRAW C2IRAW COUNTER SMSEL 14.2.3.3 TMR input function Each of timers (TMR2 to TMR4) has four independent channels, with each channel being configured as input or output. As input, each channel input signal is processed as follows: −... -
Page 233: Figure 14-24 Pwm Input Mode Configuration Example
AT32F423 Series Reference Manual In input mode, the TMRx_CxDT register latches the current counter values after the selected trigger signal is detected, and the capture compare interrupt flag bit (CxIF) is set to 1. An interrupt or a DMA request will be generated if the CxIEN and CxDEN bits are enabled. If the selected trigger signal is detected when the CxIF is set to 1, a capture overflow event is generated, and the previous counter value will be overwritten by the current counter value, with setting CxRF to 1. -
Page 234: Tmr Output Function
AT32F423 Series Reference Manual reset counter and C1DT capture C2DT capture COUNTER STIS SMSEL C1DT C2DT 14.2.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. -
Page 235: Figure 14-26 Capture/Compare Channel Output Stage (Channel 1 To 4)
AT32F423 Series Reference Manual Figure 14-26 Capture/compare channel output stage (channel 1 to 4) Output mode CNT_value controller Polarity CNT_value=CxDT Output enable selection TMRx_CM1 Compare CxORAW /CM2 CNT_value>CxDT CxEN CxOUT CxDT To the master mode controller Output mode Write CxC[1: 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this... -
Page 236: Figure 14-27 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F423 Series Reference Manual Fast output mode: Enable this mode by setting CxOIEN=1. If enabled, the CxORAW signal will not change when the counter value matches the CxDT, but change at the beginning of the current counting period. In other words, the comparison result is advanced, so the comparison result between the counter value and the TMRx_CxDT register will determine the level of CxORAW in advance. -
Page 237: Figure 14-29 Up/Down Counting Mode And Pwm Mode A
AT32F423 Series Reference Manual Figure 14-29 Up/down counting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW ≥32 C1DT[15：0] C1ORAW Figure 14-30 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master mode timer event output When TMR is used as a master timer, one of the following source of signals can be selected as TRGOUT output to a slave mode timer. -
Page 238: Tmr Synchronization
AT32F423 Series Reference Manual Figure 14-31 Clearing CxORAW(PWM mode A) by EXT input COUNTER CxDT CxOSEN CxORAW 14.2.3.5 TMR synchronization The timers are linked together internally for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit; Slave timer is selected by setting the SMSEL[2: 0] bit. -
Page 239: Figure 14-34 Example Of Trigger Mode
AT32F423 Series Reference Manual Slave mode: Trigger mode The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1) Figure 14-34 Example of trigger mode TMR_CLK CI1F1 TMR_EN COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] OVFIF Master/slave timer interconnection Both Master and slave timer can be configured in different master and slave modes respectively. -
Page 240: Debug Mode
AT32F423 Series Reference Manual Figure 14-36 Using master timer to start slave timer TMR_CLK COUNTER PR[15:0] Master DIV[15:0] Overflow event TMR_CLK TMREN Slave COUNTER DIV[15:0] PR[15:0] Starting master and slave timers synchronously by an external trigger: In this example, configure the master timer as master/slave mode synchronously and enable its slave timer synchronization function. -
Page 241: Control Register 1 (Tmrx_Ctrl1)
AT32F423 Series Reference Manual Table 14-5 TMR2 to TMR4 register map and reset value Register Offset Reset value TMRx_CTRL1 0x00 0x0000 TMRx_CTRL2 0x04 0x0000 TMRx_STCTRL 0x08 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CM1 0x18 0x0000 TMRx_CM2... -
Page 242: Control Register 2 (Tmrx_Ctrl2)
AT32F423 Series Reference Manual One-way count direction Bit 4 OWCDIR 0: Up 1: Down One cycle mode enable This bit is use to select whether to stop counting at an Bit 3 OCMEN overflow event 0: The counter does not stop at an overflow event... -
Page 243: Dma/Interrupt Enable Register (Tmrx_Iden)
AT32F423 Series Reference Manual times 0000: No filter, sampling by f ������ 0001: f , N=2 ���������������� ����_������ 0010: f , N=4 ���������������� ����_������ 0011: f , N=8 ���������������� ����_������ 0100: f /2, N=6 ���������������� ������ 0101: f /2, N=8 ����������������... -
Page 244: Interrupt Status Register (Tmrx_Ists)
AT32F423 Series Reference Manual Channel 2 DMA request enable Bit 10 C2DEN 0: Disabled 1: Enabled Channel 1 DMA request enable Bit 9 C1DEN 0: Disabled 1: Enabled Overflow event DMA request enable Bit 8 OVFDEN 0: Disabled 1: Enabled... -
Page 245: Software Event Register (Tmrx_Sw Evt)
AT32F423 Series Reference Manual This bit is set by hardware on a capture event. It is cleared by software or read access to the TMRx_C1DT 0: No capture event occurred 1: Capture event is generated If the channel 1 is configured as output mode: This bit is set by hardware on a compare event. - Page 246 AT32F423 Series Reference Manual 1: Once high level is detect on EXT input, clear C1ORAW. Channel 1 output control This field defines the behavior of the original signal C1ORAW. 000: Disconnected. C1ORAW is disconnected from C1OUT; 001: C1ORAW is high when TMRx_CVAL=TMRx_C1DT...
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Page 247: Channel Mode Register2 (Tmrx_Cm2)
AT32F423 Series Reference Manual 11: Input, C2IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS. Channel 1 digital filter This field defines the digital filter of the channel 1. N stands for the number of filtering, indicating that the input edge can pass the filter only after N sampling events. -
Page 248: Channel Control Register (Tmrx_Cctrl)
AT32F423 Series Reference Manual This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: 00: Output 01: Input, C3IN is mapped on C3IFP3 10: Input, C3IN is mapped on C4IFP3 11: Input, C3IN is mapped on STCI. -
Page 249: Counter Value (Tmrx_Cval)
AT32F423 Series Reference Manual 0: C1OUT is active high 1: C1OUT is active low When the channel 1 is configured as input mode: C1CP/C1P are used to define the valid edge of input signals. 00: C1IN active edge is on its rising edge. When used as external trigger, C1IN is not inverted. - Page 250 AT32F423 Series Reference Manual depends on the C1OBEN bit, and the corresponding output is generated on C1OUT as configured. 2023.04.25 Page 250 Rev 2.01...
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Page 251: Channel 2 Data Register (Tmrx_C2Dt)
AT32F423 Series Reference Manual 14.2.4.14 Channel 2 data register (TMRx_C2DT) Register Reset value Type Description Channel 2 data register Bit 31: 16 C2DT 0x0000 When TMR2 enables plus mode (the PMEN bit in the TMR_CTRL1 register), the C2DT is expanded to 32 bits. -
Page 252: Dma Data Register (Tmrx_Dmadt)
AT32F423 Series Reference Manual ..14.2.4.18 DMA data register (TMRx_DMADT) Register Reset value Type Description DMA data register read or write operation to the DMADT register Bit 15: 0 DMADT 0x0000 accesses the TMR registers at the following address: TMRx peripheral address + ADDR*4 to TMRx peripheral address + ADDR*4 + DTB*4. -
Page 253: Figure 14-39 Counting Clock
AT32F423 Series Reference Manual Figure 14-39 Counting clock Encoder mode (SMSEL=3'b001/010/011) CK_INT(form CRM) CI1FP1/CI2FP2 STIS[1:0] External clock mode A (SMSEL=3'b111) STIS[2] Internal trigger CK_CNT DIV_counter CNT_counter STIS[1:0] TRGIN C1INC External trigger C1IFP1 C2IPF2 Internal clock (CK_INT) By default, the CK_INT, which is divided by a prescaler, is used to drive the counter to count. -
Page 254: Figure 14-41 Block Diagram Of External Clock Mode A
AT32F423 Series Reference Manual – Set counting period through the PR[15:0] in TMRx_PR register – Enable counter through the TMREN bit in TMRx_CTRL1 register Figure 14-41 Block diagram of external clock mode A STIS C1INC External clock TMRx_CH1 C1DF C1P/C1CP... -
Page 255: Counting Mode
AT32F423 Series Reference Manual Figure 14-43 Counter timing with prescaler value chang from 1 to 4 TMR_CLK CK_CNT COUNTER DIV[15：0] PR[15：0] OVFIF Clear 14.3.3.2 Counting mode The general-purpose timer (TMR9 and TMR12) consists of a 16-bit counter supporting multiple counting modes to meet different application scenarios. -
Page 256: Figure 14-45 Overflow Event When Prben=0
AT32F423 Series Reference Manual Figure 14-45 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-46 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode This mode is enabled by setting CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1 register. -
Page 257: Figure 14-48 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32
AT32F423 Series Reference Manual Up/down counting mode (center-aligned mode) This mode is selected by setting CMSEL[1:0]≠2’b00 in the TMRx_CTRL1 register. In up/down counting mode, the counter counts up/down alternatively. When the counter counts from the value programmed in the TMRx_PR register down to 1, an underflow event is generated, and then restarts counting from 0;... -
Page 258: Figure 14-49 Ovfif In Upcounting Mode And Central-Aligned Mode
AT32F423 Series Reference Manual Repetition counter mode: The TMRx_RPR register is used to enable repetition counting mode. This mode is enabled when the repetition counter value is not equal to 0. In this mode, an overflow event is generated when a counter overflow occurs (RPR[7:0]+1). -
Page 259: Figure 14-50 Encoder Mode Structure
AT32F423 Series Reference Manual Figure 14-50 Encoder mode structure SMSEL=3'b001/010/011 encoder mode filter polarity select TMRx_CH2 C2IRAW C2DF C2IFP2 director TMRx_CH1 C1DF C1IFP1 C1IRAW filter polarity select edge detector preload pos/neg edge TMRx_DIV encoder mode A encoder DIV counter DIV_CLK... -
Page 260: Tmr Input Function
AT32F423 Series Reference Manual Figure 14-51 Example of counter behavior in encoder interface mode (encoder mode C) DOWN C1IRAW C2IRAW COUNTER SMSEL 14.3.3.3 TMR input function Each timer of TMR9 and TMR12 has two independent channels that can be configured as input or output each. -
Page 261: Figure 14-53 Channel 1 Input Stage
AT32F423 Series Reference Manual Figure 14-53 Channel 1 input stage STIS STCI C1INC input divider C1IPS C1DF C1P/C1CP C1EN CNT counter Capture C1DT C1IDIV TMRx_CH1 C1IF C1IN C1IFP1 edge detector filter C1SWTR C2IFP1 C2DF C2P/C2CP TMRx_CH2 C2IF edge detector filter... -
Page 262: Figure 14-54 Pwm Input Mode Configuration Example
AT32F423 Series Reference Manual Figure 14-54 PWM input mode configuration example C1C(2'b01) edge detector STCI C1P=0 C1DF C1IF C1IRAW C1EN Capture C1DT C1IFP1(pos) C1IN Capture trigger C1CP=0 filter C2IFP1 SMSEL(3'b110) (CH1 period) STIS(3'b101) Trigger mode C1INC CNT counter Hang reset... -
Page 263: Tmr Output Function
AT32F423 Series Reference Manual 14.3.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. TMR9 and TMR12 differ in output function on different channels. -
Page 264: Figure 14-58 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F423 Series Reference Manual be the programmed level, regardless of the counter value. Despite this, the channel flag bit and DMA request still depend on the compare result. Output compare mode: Enable output compare mode by setting CxOCTRL=3’b001/010/011. In this case, when the counter value matches the value of the CxDT register, the CxORAW is forced high (CxOCTRL=3’b001), low... -
Page 265: Figure 14-60 One-Pulse Mode
AT32F423 Series Reference Manual Figure 14-60 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master mode timer event output When TMR is used as a master timer, one of the following source of signals can be selected as TRGOUT output to a slave mode timer. This is done by setting the PTOS bit in the TMRxCTRL2 register. -
Page 266: Tmr Break Function
AT32F423 Series Reference Manual Figure 14-61 Complementary output with dead-time insertion C1ORAW C1OUT Delay C1COUT Delay C1ORAW C1OUT Delay > positive pulse C1COUT C1ORAW Delay > negative pulse C1OUT C1COUT 14.3.3.5 TMR break function When the break function is enabled (BRKEN=1), the CxOUT and CxCOUT are jointly controlled by OEN, FCSODIS, FCSOEN, CxIOS and CxCIOS. -
Page 267: Tmr Synchronization
AT32F423 Series Reference Manual Figure 14-62 TMR output control Clock failure event break enable From clock control CSS(Clock Security System) overflow event break break BRKEN auto enable trigger event AOEN TMRx_BRK BRKV filter polarity selection polarity select CxEN run state... -
Page 268: Debug Mode
AT32F423 Series Reference Manual Figure 14-64 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] C1IF1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low. -
Page 269: Tmr9 And Tmr12 Registers
AT32F423 Series Reference Manual 14.3.4 TMR9 and TMR12 registers Table 14-9 TMR9 and TMR12 register map and reset value Register name Register Reset value TMRx_CTRL1 0x00 0x0000 TMRx_CTRL2 0x04 0x0000 TMRx_STCTRL 0x08 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT... -
Page 270: Tmr9 And Tmr12 Control Register 2 (Tmrx_Ctrl2)
AT32F423 Series Reference Manual 1: The counter stops at an overflow event Overflow event source This bit is used to select overflow event or DMA request sources. Bit 2 OVFS 0: Counter overflow, setting the OVFSWTR bit or overflow event generated by slave timer controller... -
Page 271: Tmr9 And Tmr12 Slave Timer Control Register (Tmr1_Stctrl)
AT32F423 Series Reference Manual 14.3.4.3 TMR9 and TMR12 slave timer control register (TMR1_STCTRL) Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at default value. Subordinate TMR synchronization If enabled, master and slave timer can be synchronized. -
Page 272: Tmr9 And Tmr12 Interrupt Status Register (Tmrx_Ists)
AT32F423 Series Reference Manual HALL interrupt enable Bit 5 HALLIEN 0: Disabled 1: Enabled Reserved 0x00 resd Kept at default value. Bit 4: 3 Channel 2 interrupt enable Bit 2 C2IEN 0: Disabled 1: Enabled Channel 1 interrupt enable Bit 1... -
Page 273: Tmr9 And Tmr12 Software Event Register (Tmrx_Swevt)
AT32F423 Series Reference Manual 1: Overflow event is generated. If OVFEN=0 and OVFS=0 in the TMRx_CTRL1 register: − An overflow event is generated when OVFG= 1 in the TMRx_SWEVE register; − An overflow event is generated when the counter CVAL is reinitialized by a trigger event. - Page 274 AT32F423 Series Reference Manual Output compare mode: Register Reset value Type Description Bit 15 Reserved resd Kept at default value. Bit 14: 12 C2OCTRL Channel 2 output control Bit 11 C2OBEN Channel 2 output buffer enable Bit 10 C2OIEN Channel 2 output enable immediately...
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Page 275: Tmr9 And Tmr12 Channel Control Register (Tmrx_Cctrl)
AT32F423 Series Reference Manual 10: Input, C1IN is mapped on C2IFP1 11: Input, C1IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS. Input capture mode: Register Reset value Type Description Bit 15: 12... -
Page 276: Tmr9 And Tmr12 Counter Value (Tmrx_Cval)
AT32F423 Series Reference Manual Please refer to C1P description. Channel 2 enable Bit 4 C2EN Please refer to C1EN description. Channel 1 complementary polarity Bit 3 C1CP 0: C1COUT is active high. 1: C1COUT is active low. Channel 1 complementary enable... -
Page 277: Tmr9 And Tmr12 Channel 2 Data Register (Tmrx_C2Dt)
AT32F423 Series Reference Manual depends on the C1OBEN bit, and the corresponding output is generated on C1OUT as configured. 14.3.4.14 TMR9 and TMR12 channel 2 data register (TMRx_C2DT) Register Reset value Type Description Channel 2 data register When the channel 2 is configured as input mode:... -
Page 278: Tmr9 And Tmr12 Dma Control Register (Tmrx_Dmactrl)
AT32F423 Series Reference Manual This bit acts on the channels that have complementary output. It is used to set the channel state when the timer is inactive and MOEN=0. 0: CxOUT/CxCOUT outputs are disabled. 1: CxOUT/CxCOUT outputs are enabled. Output idle level. -
Page 279: General-Purpose Timer (Tmr10/11/13/14)
AT32F423 Series Reference Manual 14.4 General-purpose timer (TMR10/11/13/14) 14.4.1 TMRx introduction The general-purpose timers (TMR10/11/13/14) consist of a 16-bit upcounter, one capture/compare register, and one independent channel. They can be used for dead-time insertion, input capture and programmable PWM output. -
Page 280: Counting Mode
AT32F423 Series Reference Manual Figure 14-69 Control circuit with CK_INT, TMRx_DIV=0x0 and PR=0x16 CK_INT TMREN COUNTER overflow OVFIF 14.4.3.2 Counting mode The TMR10/11/13/14 supports multiple counting modes to meet various application scenarios. Each consists of a 16-bit upcounter. The TMRx_PR register is used to define counting period of counter. The value in the TMRx_PR is immediately moved to the shadow register by default. -
Page 281: Figure 14-71 Overflow Event When Prben=0
AT32F423 Series Reference Manual Figure 14-71 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-72 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode This mode is enabled by setting CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1 register. -
Page 282: Figure 14-74 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32
AT32F423 Series Reference Manual Figure 14-74 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32 TMR_CLK COUNTER OWCDIR PR[15:0] DIV[15:0] TWCMSEL [1：0] OVFIF Clear Clear Clear Repetition counter mode: The TMRx_RPR register is used to enable repetition counting mode. This mode is enabled when the repetition counter value is not equal to 0. -
Page 283: Tmr Input Function
AT32F423 Series Reference Manual Figure 14-75 OVFIF in upcounting mode and central-aligned mode Example 1 ： up count mode,RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 2 ： two-way up count mode3, RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 3 ： two-way up count mode3, RPR=0x1... -
Page 284: Tmr Output Function
AT32F423 Series Reference Manual Figure 14-76 Input/output channel 1 main circuit filter edge detector input divider C1IRAW TMRx_CH1 C1DF C1P/C1CP C1IDIV C1EN C1IFP1 C1IN Capture trigger C1DT_shadow CNT counter Capture C1DT Compare C1DT preload C1OCTRL C1OBEN Overflow event C1ORAW polarity select... - Page 285 AT32F423 Series Reference Manual to IO after being processed by the output control circuit. The period of the output signal is configured by the TMR15_PR register, while the duty cycle by the TMRx_CxDT register. PWM mode A: Enable PWM mode A by setting CxOCTRL=3’b110. In upcounting mode, C1ORAW outputs high when TMRx_C1DT>TMRx_CVAL, otherwise, it is low;...
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Page 286: Figure 14-79 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F423 Series Reference Manual Figure 14-79 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW Figure 14-80 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0]... -
Page 287: Tmr Break Function
AT32F423 Series Reference Manual If the delay is greater than the width of the active output, C1OUT and C1COUT will not generate corresponding pulses. Therefore, the dead-time should be less than the width of the active output. Figure 14-82 gives an example of dead-time insertion when CxP=0, CxCP=0, OEN=1, CxEN=1 and CxCEN=1. -
Page 288: Debug Mode
AT32F423 Series Reference Manual If AOEN=1, the OEN bit is automatically set again at the next overflow event. Note: When the break input is active, the OEN cannot be set, nor the status flag, BRKIF can be cleared. Figure 14-83 TMR output control... -
Page 289: Tmrx Registers
AT32F423 Series Reference Manual 14.4.4 TMRx registers Table TMR10/11/13/14 register map and reset value 14-10 Register Offset Reset value TMRx_CTRL1 0x00 0x0000 TMRx_CTRL2 0x04 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CM1 0x18 0x0000 TMRx_CCTRL 0x20 0x0000... -
Page 290: Tmrx Control Register 2 (Tmrx_Ctrl2) (X=10/11/13/14)
AT32F423 Series Reference Manual 0: Counter overflow, setting the OVFSWTR bit or overflow event generated by slave timer controller 1: Only counter overflow generates an overflow event Overflow event enable 0: Enabled Bit 1 OVFEN 1: Disabled TMR enable 0: Enabled... -
Page 291: Tmrx Interrupt Status Register (Tmrx_Ists) (X=10/11/13/14)
AT32F423 Series Reference Manual 14.4.4.4 TMRx interrupt status register (TMRx_ISTS) (x=10/11/13/14) Register Reset value Type Description Bit 15: 10 Reserved 0x00 resd Kept at default value. Channel 1 recapture flag This bit indicates whether a recapture is detected when C1IF=1. This bit is set by hardware, and cleared by... -
Page 292: Tmrx Channel Mode Register1 (Tmrx_Cm1) (X=10/11/13/14)
AT32F423 Series Reference Manual 0: No effect 1: Generate a channel 1 event. Overflow event triggered by software This bit is set by software to generate an overflow event. Bit 0 OVFSWTR 0: No effect 1: Generate an overflow event. -
Page 293: Tmrx Channel Control Register (Tmrx_Cctrl) (X=10/11/13/14)
AT32F423 Series Reference Manual 10: Reserved 11: Reserved Input capture mode: Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at default value. Channel 1 digital filter This field defines the digital filter of the channel 1. N stands for the number of filtering, indicating that the input edge can pass the filter only after N sampling events. -
Page 294: Table 14-11 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function
AT32F423 Series Reference Manual 01: C1IN active edge is on its falling edge. When used as external trigger, C1IN is inverted. 10: Reserved 11: C1IN active edge is on its falling edge and rising edge. When used as external trigger, C1IN is not inverted. -
Page 295: Tmrx Counter Value (Tmrx_Cval) (X=10/11/13/14)
AT32F423 Series Reference Manual Note: If the two outputs of a channel are not used (CxEN = CxCEN = 0), CxIOS, CxCIOS, CxP and CxCP must be cleared. Note: The state of the external I/O pins connected to the complementary CxOUT and CxCOUT channels depends on the CxOUT and CxCOUT channel state and the GPIO and the IOMUX registers. - Page 296 AT32F423 Series Reference Manual 1101: f /32, N=5 SAMPLING 0110: f /4, N=6 SAMPLING 1110: f /32, N=6 SAMPLING 0111: f /4, N=8 SAMPLING 1111: f /32, N=8 SAMPLING Output enable This bit acts on the channels as output. It is used to enable Bit 15 CxOUT and CxCOUT outputs.
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Page 297: Tmrx Dma Control Register (Tmrx_Dmactrl) (X=10/11/13/14)
AT32F423 Series Reference Manual 14.4.4.14 TMRX DMA control register (TMRX_DMACTRL) (X=10/11/13/14) Register Reset value Type Description Bit 15:13 Reserved resd Kept at default value. DMA transfer bytes This field defines the number of DMA transfers: 00000: 1 byte 00001: 2 bytes... -
Page 298: Advanced-Control Timers (Tmr1)
AT32F423 Series Reference Manual 14.5 Advanced-control timers (TMR1) 14.5.1 TMR1 introduction The advanced-control timer TMR1 consists of a 16-bit counter supporting up and down counting modes, four channel registers, and four independent channels. It can be used for dead-time insertion, input capture and programmable PWM output. -
Page 299: Figure 14-86 Counting Clock
AT32F423 Series Reference Manual Figure 14-86 Counting clock Encoder mode (SMSEL=3'b001/010/011) CK_INT(form CRM) CI1FP1/CI2FP2 STIS[1:0] External clock mode A (SMSEL=3'b111) STIS[2] Internal trigger CK_CNT DIV_counter CNT_counter STIS[1:0] TRGIN C1INC C1IFP1 polarity edge External trigger External clock mode B detector C2IPF2... -
Page 300: Figure 14-88 Block Diagram Of External Clock Mode A
AT32F423 Series Reference Manual polarity (ESP in TMRx_STCTRL register), external signal frequency division (ESDIV[1:0] in TMRx_STCTRL) and external signal filter (ESF[3:0] in TMRx_STCTRL register). – Set TRGIN signal source through the STIS[1:0] bit in TMRx_STCTRL register – Enable external clock mode A by setting SMSEL=3’b111 in TMRx_STCTR register –... -
Page 301: Counting Mode
AT32F423 Series Reference Manual Figure 14-91 Counting in external clock mode B, PR=0x32 and DIV=0x0 TMR_CLK CK_CNT COUNTER ESDIV[1:0] ESF[3:0] 0000 OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer. -
Page 302: Figure 14-93 Basic Structure Of A Counter
AT32F423 Series Reference Manual every DIV[15:0]+1 clock cycle. Similar to TMRx_PR register, after enabling periodic buffer, the value of the TMRx_DIV register are transferred into the shadow register at each overflow event. Reading the TMRx_CNT register returns the current counter value. Writing the TMRx_CNT register will update the current counter value. -
Page 303: Figure 14-96 Counter Timing Diagram With Internal Clock Divided By 4
AT32F423 Series Reference Manual Figure 14-96 Counter timing diagram with internal clock divided by 4 TMR_CLK CNT_CLK COUNTER PR[15：0] DIV[15：0] OVFIF Clear Up/down counting mode (center-aligned mode) Up/down counting mode can be enabled by setting CMSEL[1:0]≠2’b00 in the TMRx_CTRL1 register. In up/down counting mode, the counter counts up/down alternatively. -
Page 304: Figure 14-98 Ovfif Behavior In Upcounting Mode And Center-Aligned Mode
AT32F423 Series Reference Manual Figure 14-98 OVFIF behavior in upcounting mode and center-aligned mode Example 1 ： up count mode,RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 2 ： two-way up count mode3, RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 3 ：... -
Page 305: Figure 14-100 Example Of Encoder Interface Mode C
AT32F423 Series Reference Manual SMSEL=3'b001/010/011 encoder mode filter polarity select TMRx_CH2 C2IRAW C2DF C2IFP2 director C1DF C1IFP1 TMRx_CH3 polarity select filter edge C1IRAW TMRx_CH1 detector preload pos/neg edge C1INSEL TMRx_DIV encoder mode A encoder DIV counter DIV_CLK mode B counter... - Page 306 AT32F423 Series Reference Manual DOWN C1IRAW C2IRAW COUNTER SMSEL 2023.04.25 Page 306 Rev 2.01...
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Page 307: Tmr Input Function
AT32F423 Series Reference Manual 14.5.3.3 TMR input function The TMR1 has four independent channels. Each channel can be configured as input or output. As input, each channel input signal is processed as follows: − TMRx_CHx outputs the pre-processed CxIRAW. The C1INSE bit is used to select TMRx_CHx, or the XOR-ed TMRx_CH1, TMRx_CH2 and TMRx_CH3 as the source of C1IRAW. -
Page 308: Figure 14-103 Pwm Input Mode Configuration Example
AT32F423 Series Reference Manual with the current counter value, and the CxRF is set to 1. To capture the rising edge of C1IN input, following the procedure below: Set C1C=01 in the TMRx_CM1 register to select the C1IN as channel 1 input ... -
Page 309: Tmr Output Function
AT32F423 Series Reference Manual Figure 14-104 PWM input mode reset counter and C1DT capture C2DT capture COUNTER STIS SMSEL C1DT C2DT 14.5.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. - Page 310 AT32F423 Series Reference Manual when TMRx_C1DT>TMRx_CVAL, otherwise, it is low; In downcounting mode, C1ORAW outputs low when TMRx_C1DT<TMRx_CVAL, otherwise, it is high. To use PWM mode A, the following procedures are recommended: − Set PWM periods through TMRx_PR register Set PWM duty cycles through TMRx_CxD −...
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Page 311: Figure 14-107 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F423 Series Reference Manual Figure 14-107 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW Figure 14-108 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0]... -
Page 312: Figure 14-110 One-Pulse Mode
AT32F423 Series Reference Manual Figure 14-110 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master mode timer event output When TMR is used as a master timer, one of the following source of signals can be selected as TRGOUT output to a slave mode timer. This is done by setting the PTOS bit in the TMRxCTRL2 register. -
Page 313: Tmr Break Function
AT32F423 Series Reference Manual If the delay is greater than the width of the active output, then theC1OUT and C1COUT will not generate corresponding pulses. Therefore the dead-time should be less than the width of the active output. Figure 14-112 gives an example of dead-time insertion when CxP=0, CxCP=0, OEN=1, CxEN=1 and CxCEN=1. -
Page 314: Tmr Synchronization
AT32F423 Series Reference Manual If AOEN=1, the OEN bit is automatically set again at the next overflow event. Note: When the break input is active, the OEN cannot be set, nor the status flag, BRKIF can be cleared. Figure 14-113 TMR output control... -
Page 315: Figure 14-115 Example Of Reset Mode
AT32F423 Series Reference Manual Figure 14-115 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] CI1F1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low. -
Page 316: Debug Mode
AT32F423 Series Reference Manual 14.5.3.7 Debug mode When the microcontroller enters debug mode (Cortex -M4F core halted), the TMR1 counter stops counting by setting the TMR1_PAUSE in the DEBUG module. 14.5.4 TMR1 registers These peripheral registers must be accessed by words (32 bits). -
Page 317: Tmr1 Control Register2 (Tmr1_Ctrl2)
AT32F423 Series Reference Manual counts up 11: Two-way counting mode 3, count up and down alternately, the CxIF bit is set when the counter counts up / down One-way count direction Bit 4 OWCDIR 0: Up 1: Down One cycle mode enable... -
Page 318: Tmr1 Slave Timer Control Register (Tmr1_Stctrl)
AT32F423 Series Reference Manual This bit only acts on channels that have complementary output. If the channel control bits are buffered: 0: Control bits are updated by setting the HALL bit 1: Control bits are updated by setting the HALL bit or a rising edge on TRGIN. -
Page 319: Tmr1 Dma/Interrupt Enable Register (Tmr1_Iden)
AT32F423 Series Reference Manual Please refer to Table 14-11 for more information on ISx for each timer. Bit 3 Reserved resd Kept at its default value. Subordinate TMR mode selection 000: Slave mode is disabled 001: Encoder mode A 010: Encoder mode B 011: Encoder mode C 100: Reset mode —Rising edge of the TRGIN input... -
Page 320: Tmr1 Interrupt Status Register (Tmr1_Ists)
AT32F423 Series Reference Manual 0: Disabled 1: Enabled Overflow interrupt enable Bit 0 OVFIEN 0: Disabled 1: Enabled 14.5.4.5 TMR1 interrupt status register (TMR1_ISTS) Register Reset value Type Description Bit 15: 13 Reserved resd Kept at default value. Channel 4 recapture flag... -
Page 321: Tmr1 Software Event Register (Tmr1_Swevt)
AT32F423 Series Reference Manual − An overflow event is generated when OVFG= 1 in the TMRx_SWEVE register; − An overflow event is generated when the counter CVAL is reinitialized by a trigger event. 14.5.4.6 TMR1 software event register (TMR1_SWEVT) Register... - Page 322 AT32F423 Series Reference Manual 1: Once a high level is detect on EXT input, clear C1ORAW. Channel 1 output control This field defines the behavior of the original signal C1ORAW. 000: Disconnected. C1ORAW is disconnected from C1OUT; 001: C1ORAW is high when TMR1_CVAL=TMR1_C1DT...
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Page 323: Tmr1 Channel Mode Register2 (Tmr1_Cm2)
AT32F423 Series Reference Manual 11: Input, C2IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS. Channel 1 digital filter This field defines the digital filter of the channel 1. N stands for the number of filtering, indicating that the input edge can pass the filter only after N sampling events. -
Page 324: Tmr1 Channel Control Register (Tmr1_Cctrl)
AT32F423 Series Reference Manual Bit 6: 4 C3OCTRL Channel 3 output control Bit 3 C3OBEN Channel 3 output buffer enable Bit 2 C3OIEN Channel 3 output enable immediately Channel 3 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=‘0’:... -
Page 325: Table 14-15 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function
AT32F423 Series Reference Manual 1: C1COUT is active low. Channel 1 complementary enable Bit 2 C1CEN 0: Output is disabled. 1: Output is enabled. Channel 1 polarity When the channel 1 is configured as output mode: 0: C1OUT is active high... -
Page 326: Tmr1 Counter Value (Tmr1_Cval)
AT32F423 Series Reference Manual (corresponding IO is not driven by the timer, IO floating) In other cases: Off-state (Output enabled with inactive level) Asynchronously: CxOUT =CxP, Cx_EN=1, CxCOUT=CxCP, CxCEN=1; If the clock is present: after a dead-time, CxOUT=CxIOS, CxCOUT=CxCIOS, assuming that CxIOS and CxCIOS do not correspond to CxOUT and CxCOUT active level. - Page 327 AT32F423 Series Reference Manual C2DT is the value to be compared with the CVAL value. Whether the written value takes effective immediately depends on the C2OBEN bit, and the corresponding output is generated on C2OUT as configured. 2023.04.25 Page 327...
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Page 328: Tmr1 Channel 3 Data Register (Tmr1_C3Dt)
AT32F423 Series Reference Manual 14.5.4.16 TMR1 channel 3 data register (TMR1_C3DT) Register Reset value Type Description Channel 3 data register When the channel 3 is configured as input mode: The C3DT is the CVAL value stored by the last channel... -
Page 329: Tmr1 Dma Control Register (Tmr1_Dmactrl)
AT32F423 Series Reference Manual 1: Break input is enabled. Frozen channel status when holistic output enable This bit acts on the channels that have complementary output. It is used to set the channel state when the timer Bit 11 FCSOEN is inactive and MOEN=1. -
Page 330: Tmr1 Dma Data Register (Tmr1_Dmadt)
AT32F423 Series Reference Manual 14.5.4.20 TMR1 DMA data register (TMR1_DMADT) Register Reset value Type Description DMA data register A write/read operation to the DMADT register accesses Bit 15: 0 DMADT 0x0000 any TMR register located at the following address: TMR1 peripheral address + ADDR*4 to TMR1 peripheral address + ADDR*4 + DTB*4 14.5.4.21... -
Page 331: Window Watchdog Timer (Wwdt)
AT32F423 Series Reference Manual 15 Window watchdog timer (WWDT) 15.1 WWDT introduction The window watchdog downcounter must be reloaded in a limited time window to prevent the watchdog circuits from generating a system reset. The window watch dog is used to detect the occurrence of system malfunctions. -
Page 332: Debug Mode
AT32F423 Series Reference Manual Table 15-1 Minimum and maximum timeout value when PCLK1=72 MHz Prescaler Min. Timeout value Max. Timeout value 56.5μs 3.64ms 113.5μs 7.28ms 227.5μs 14.56ms 455μs 29.12ms Figure 15-2 Window watchdog timing diagram CNT[6：0] 55 54 52 51 50... -
Page 333: Configuration Register (Wwdt_Cfg)
AT32F423 Series Reference Manual 15.5.2 Configuration register (WWDT_CFG) Register Reset value Type Description Bit 31: 10 Reserved 0x000000 resd Kept at default value. Reload counter interrupt Bit 9 RLDIEN 0: Disabled 1: Enabled Clock division value 00: PCLK1 divided by 4096... -
Page 334: Watchdog Timer (Wdt)
AT32F423 Series Reference Manual 16 Watchdog timer (WDT) 16.1 WDT introduction The WDT is driven by a dedicated low-speed clock (LICK). Due to the lower clock accuracy of LICK, the WDT is best suited to the applications that have lower timing accuracy and can run independently outside the main application. -
Page 335: Debug Mode
AT32F423 Series Reference Manual Figure 16-1 WDT block diagram power domain 1.2 V power domain Prescaler register 8-bit SYNC WDT_DIV prescaler Reload register 12-bit reload 12-bit SYNC WDT_RLD value downcounter Compare CNT=0 reset Windows register 12-bit windows SYNC WDT_WIN value reload at CNT>WIN... -
Page 336: Command Register (Wdt_Cmd)
AT32F423 Series Reference Manual 16.5.1 Command register (WDT_CMD) (Reset in Standby mode) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at default value. Command register 0xAAAA: Reload counter 0x5555: Unlock the write-protected WDT_DIV, WDT_RLD Bit 15: 0... -
Page 337: Window Register (Wdt_Win)
AT32F423 Series Reference Manual 16.5.5 Window register (WDT_WIN) (Not reset in Standby mode) Register Reset value Type Description Bit 31: 12 Reserved 0x000000 resd Kept at default value. Window value When the counter value is greater than the window value,... -
Page 338: Enhanced Real-Time Clock (Ertc)
AT32F423 Series Reference Manual 17 Enhanced real-time clock (ERTC) 17.1 ERTC introduction The real-time clock provides a calendar clock function. The time and date can be modified by modifying the ERTC_TIME and ERTC_DATE register. The ERTC module is in the battery powered domain, which means that it keeps running and free from the influence of system reset as long as VBAT is powered (VBAT must be supplied through VDD domain). -
Page 339: Ertc Function Overview
AT32F423 Series Reference Manual 17.3 ERTC function overview 17.3.1 ERTC clock ERTC clock source (ERTC_CLK) is selected via clock controller from a LEXT, LICK, and divided HEXT (by setting the ERTCSEL[1:0] in the CRM_BPDC register). The HEXT frequency division value is configured through the ERTC_DIV[4:0] bit in the CRM_CFG register. - Page 340 AT32F423 Series Reference Manual ERTC_WP ERTC_SBS Configurable ERTC_TADJ when TADJF=0 ERTC_TSTM ERTC_TSDT ERTC_TSSBS Configurable ERTC_SCAL when CALUPDF=0 ERTC_TAMP Configurable ERTC_ALASBS when ALAWF =1 Configurable ERTC_ALBSBS when ALBWF =1 ERTC_BPRx Clock and calendar initialization After the register write protection is unlocked, follow the procedure below for clock and calendar initialization: 1.
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Page 341: Periodic Automatic Wakeup
AT32F423 Series Reference Manual calendar, the software must read the clock and calendar registers twice, and compare the results of two read operations. If the result is not aligned, read again until that the results of two read accesses are consistent. -
Page 342: Reference Clock Detection
AT32F423 Series Reference Manual cycles. A maximum of 511 pulses can be removed. When the ADD bit is set, 512 pulses can be inserted during the 2 ERTC_CLK cycles. When DEC[8: 0] and ADD are sued together, a deviation ranging from -511 to +512 ERTC_CLK cycles can be added during the 2 ERTC_CLK cycles. -
Page 343: Tamper Detection
AT32F423 Series Reference Manual users poll TSOF bit when the TSF is set. 17.3.7 Tamper detection The ERTC has two tamper detection modes: TAMP1 and TAMP2. They can be configured as a level detection with filter or edge detection. TAMP1 uses the TSPIN bit to select either ERTC_MUX1 or ERTC_MUX2 as a tamper pin, while the TAMP2 can only select ERTC_MUX2 as a tamper pin. -
Page 344: Ertc Wakeup
AT32F423 Series Reference Manual 17.3.9 ERTC wakeup ERTC can be woken up by alarm clock, periodic auto wakeup, time stamp or tamper event. To enable an ERTC interrupt, follow the procedure below: 1. Configure the EXINT line corresponding to ERTC interrupts as an interrupt mode and enable it, and select a rising edge 2. -
Page 345: Ertc Registers
AT32F423 Series Reference Manual 17.4 ERTC registers These peripheral registers must be accessed by half words (16 bits) or words (32 bits). ERTC registers are 16-bit addressable registers. Table 17-4 ERTC register map and reset values Register name Offset Reset value... -
Page 346: Ertc Date Register (Ertc_Date)
AT32F423 Series Reference Manual 17.4.2 ERTC date register (ERTC_DATE) Register Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at default value. Bit 23: 20 Year tens Bit 19: 16 Year units Week day 0: Forbidden 1: Monday... -
Page 347: Ertc Initialization And Status Register (Ertc_Sts)
AT32F423 Series Reference Manual Alarm B interrupt enable Bit 13 ALBIEN 0: Alarm B interrupt disabled 1: Alarm B interrupt enabled Alarm A interrupt enable Bit 12 ALAIEN 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled Timestamp enable... - Page 348 AT32F423 Series Reference Manual 0: No tamper event 1: Tamper event occurred Timestamp overflow flag 0: No timestamp overflow Bit 12 TSOF rw0c 1: Timestamp overflow occurs If a new time stamp event is detected when time stamp flag (TSF) is already set, this bit will be set by hardware.
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Page 349: Ertc Divider Register (Ertc_Div)
AT32F423 Series Reference Manual 0: Alarm B register write operation not allowed 1: Alarm B register write operation allowed Alarm A register allows write flag Bit 0 ALAWF 0: Alarm A register write operation not allowed 1: Alarm A register write operation allowed 17.4.5 ERTC divider register (ERTC_DIV) -
Page 350: Ertc Write Protection Register (Ertc_Wp)
AT32F423 Series Reference Manual Bit 29: 28 Date tens Bit 27: 24 Date/week day units Hour mask Bit 23 MASK3 0: No hour mask 1: Alarm clock doesn’t care about hours AM/PM 0: AM Bit 22 AMPM 1: PM Note: This bit is applicable for 12-hour format only. It is 0 for 24-hour format. -
Page 351: Ertc Time Stamp Date Register (Ertc_Tsdt)
AT32F423 Series Reference Manual for 24-hour format. Bit 21: 20 HT Hour tens Bit 19: 16 HU Hour units Bit 15 Reserved resd Kept at default value Bit 14: 12 MT Minute tens Bit 11: 8 MU Minute units Bit 7... -
Page 352: Ertc Tamper Configuration Register (Ertc_Tamp)
AT32F423 Series Reference Manual 17.4.16 ERTC tamper configuration register (ERTC_TAMP) Register Reset value Type Description Bit 31: 19 Reserved 0x0000 resd Kept at default value Output type Bit 18 OUTTYPE 0: Open-drain output 1: Push-pull output Time stamp detection pin selection... -
Page 353: Ertc Alarm Clock A Subsecond Register (Ertc_Alasbs)
AT32F423 Series Reference Manual 1: Tamper detection interrupt enabled Tamper detection 1 valid edge If TPFLT=0: 0: Rising edge Bit 1 TP1EDG 1: Falling edge If TPFLT>0: 0: Low 1: High Tamper detection 1 enable Bit 0 TP1EN 0: Tamper detection 1 disabled 1: Tamper detection 1 enabled 17.4.17 ERTC alarm clock A subsecond register (ERTC_ALASBS) -
Page 354: Analog-To-Digital Converter (Adc)
AT32F423 Series Reference Manual 18 Analog-to-digital converter (ADC) 18.1 ADC introduction The ADC is a peripheral that converts an analog input signal into a 12-bit/10-bit/8-bit/6-bit digital signal. Its sampling rate is as high as 5.33 MSPS. It has up to 26 channels for sampling and conversion. -
Page 355: Adc Structure
AT32F423 Series Reference Manual 18.3 ADC structure Figure 18-1 shows the block diagram of ADC. Figure 18-1 ADC1 block diagram OCTESEL[4:0] ADCDIV ADC prescaler HCLK/ PLLCLK ADCCLK OCTEN [1:0] TMR1_TRGO TMR1_CC4 TMR2_TRGO ADCx_IN0 TMR3_TRGO Trigger ADCx_IN1 TMR9_TRGO detection TMR1_CC1 GPIO... -
Page 356: Adc Functional Overview
AT32F423 Series Reference Manual 18.4 ADC functional overview 18.4.1 Channel management Analog signal channel input: There are 26 analog signal channel inputs for each of the ADCs, expressed by ADC_INx (x=0 to 17, 20 to 27). ADC_IN0 to ADC_IN15 represent external analog input, ADC_IN16 represents internal temperature sensor, ADC_IN17 represents internal reference voltage, and ADC_IN20 to ADC_IN27 represent external analog input. -
Page 357: Power-On And Calibration
AT32F423 Series Reference Manual Figure 18-2 ADC basic operation process Power-on Calibration Trigger conversion Read data 18.4.2.1 Power-on and calibration Power-on Set the ADCxEN bit in the CRM_APB2EN register to enable ADC clocks: PCLK2 and ADCCLK. Program the desired ADCCLK frequency by setting the ADCDIV bit in the ADC_CCTRL register. -
Page 358: Trigger
AT32F423 Series Reference Manual Figure 18-3 ADC power-on and calibration The ADCEN The ADCAL bit is set by bit is set by software. software. ADCCLK ADCEN STAB RDY flag ADCAL Trigger OCCE flag Powering up Calibration Conversion status The RDY bit... -
Page 359: Conversion Sequence Management
AT32F423 Series Reference Manual 18.4.3 Conversion sequence management Only one channel is converted at each trigger by default, that is, OSN1-defined channel or PSN4-defined channel. The following section describes various conversion sequence modes in detail. This mode enables multiple channels to be converted in a specific sequence. -
Page 360: Repetition Mode
AT32F423 Series Reference Manual 18.4.3.3 Repetition mode The repetition mode is enabled by setting the RPEN bit in the ADC_CTRL2 register. When a trigger signal is detected, the ordinary channels will be converted repeatedly. This mode can work in conjunction with the ordinary channel conversion in sequence mode to enable the repeated conversion of the ordinary group. -
Page 361: End Of Conversion
AT32F423 Series Reference Manual 18.4.4 End of conversion The ADABRT bit in the ADC_CTRL2 register is used to stop ADC conversions. At the end of the conversion, the conversion sequence returns to the first channel. This allows the user to configure a new sequence of channels, and the ADC starts conversions from the beginning based on the new order when a trigger occurs. -
Page 362: Oversampling Of Ordinary Group Of Channels
AT32F423 Series Reference Manual 18.4.5.1 Oversampling of ordinary group of channels The OOSRSEL bit in the ADC_OVSP register can be used to resume ordinary oversampling mode. OOSRSEL=0: continuous conversion mode. Ordinary group of channels, after being interrupted by preempted group of channels during oversampling, will retain the converted data and resume from the last interrupted ordinary conversion. -
Page 363: Oversampling Of Preempted Group Of Channels
AT32F423 Series Reference Manual Ordinary oversampling trigger mode Figure 18-10 Sampling OCLEN=1, OSN1=ADC_IN0, OSN2=ADC_IN1 Conversion Non-triggered oversampling mode：OOSEN = 1, POSEN = 0, OOSRSEL = 0, OOSTREN Ordinary trigger Ordinary ADC_IN0 ADC_IN0 ADC_IN0 ADC_IN0 ADC_IN1 ADC_IN1 ADC_IN1 4 ADC_IN1 OCCE flag set Triggered oversampling mode：OOSEN = 1, POSEN = 0,... -
Page 364: Data Read
AT32F423 Series Reference Manual Figure 18-12 Data alignment Ordinary channel data 12 bits Right-alignment DT[11] DT[10] DT[9] DT[8] DT[7] DT[6] DT[5] DT[4] DT[3] DT[2] DT[1] DT[0] Left-alignment DT[11] DT[10] DT[9] DT[8] DT[7] DT[6] DT[5] DT[4] DT[3] DT[2] DT[1] DT[0] Ordinary channel data 6 bits... -
Page 365: Status Flag And Interrupts
AT32F423 Series Reference Manual 18.4.7.1 Status flag and interrupts ADC has its dedicated ADC_STS registers, namely, ready flag (RDY), overflow event flag (OCCO), ordinary channel conversion start flag (OCCS), preempted channel conversion start flag (PCCS), preempted channel conversion end flag (PCCE), ordinary channel conversion end flag (OCCE) and voltage monitor out of range (VMOR). -
Page 366: Adc Status Register (Adc_Sts)
AT32F423 Series Reference Manual 18.5.1 ADC status register (ADC_STS) Accessed by words. Register Reset value Type Description Bit 31: 7 Reserved 0x0000000 resd Kept at default value. ADC conversion ready flag This bit is read only. It is set by hardware when the ADC is powered. - Page 367 AT32F423 Series Reference Manual 00: 12-bit 01: 10-bit 10: 8-bit 11: 6-bit Voltage monitoring enable on ordinary channels Bit 23 OCVMEN 0: Voltage monitoring disabled on ordinary channels 1: Voltage monitoring enabled on ordinary channels Voltage monitoring enable on preempted channels...
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Page 368: Adc Control Register2 (Adc_Ctrl2)
AT32F423 Series Reference Manual 18.5.3 ADC control register2 (ADC_CTRL2) Accessed by words. Register Reset value Type Description Kept at default value Bit 30: 26 Reserved 0x00 resd Conversion of ordinary channels triggered by software 0: Conversion of ordinary channels not triggered... -
Page 369: Adc Sampling Time Register 1 (Adc_Spt1)
AT32F423 Series Reference Manual 0: No ADC conversion abort command 1: Abort current ADC conversion Note: This bit is cleared by hardware when the ADC conversion stops. After this bit is cleared, it is possible to retrigger conversion. Initialize A/D calibration This bit is set by software and cleared by hardware. - Page 370 AT32F423 Series Reference Manual 111: 640.5 cycles Sample time selection of channel ADC_IN15 000: Reserved 001: 6.5 cycles 010: 12.5 cycles 011: 24.5 cycles Bit 17: 15 CSPT15 100: 47.5 cycles 101: 92.5 cycles 110: 247.5 cycles 111: 640.5 cycles...
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Page 371: Adc Sampling Time Register 2 (Adc_Spt2)
AT32F423 Series Reference Manual 110: 247.5 cycles 111: 640.5 cycles 18.5.5 ADC sampling time register 2 (ADC_SPT2) Accessed by words. Register Reset value Type Description Bit 31: 30 Reserved resd Kept at default value Sample time selection of channel ADC_IN9 000: Reserved 001: 6.5 cycles... - Page 372 AT32F423 Series Reference Manual Sample time selection of channel ADC_IN4 000: Reserved 001: 6.5 cycles 010: 12.5 cycles 011: 24.5 cycles Bit 14: 12 CSPT4 100: 47.5 cycles 101: 92.5 cycles 110: 247.5 cycles 111: 640.5 cycles Sample time selection of channel ADC_IN3 000: Reserved 001: 6.5 cycles...
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Page 373: Adc Preempted Channel Data Offset Registe R X
AT32F423 Series Reference Manual 18.5.6 ADC preempted channel data offset register x (ADC_ PCDTOx) (x=1..4) Accessed by words. Register Reset value Type Description Kept at default value Bit 31: 12 Reserved 0x00000 resd Data offset for Preempted channel x Bit 11: 0... -
Page 374: Adc Ordinary Sequence Register 3 (Adc_ Osq3)
AT32F423 Series Reference Manual Number of 7th conversion in ordinary sequence Note: The number can be 0~17, 20~27. For example, if Bit 4: 0 OSN7 0x00 the number is set to 8, it means that the 7 conversion is ADC_IN8 channel. -
Page 375: Adc Sampling Time Register 3 (Adc_Spt3)
AT32F423 Series Reference Manual 18.5.15 ADC sampling time register 3 (ADC_SPT3) Accessed by words. Register Reset value Type Description Bit 31: 24 Reserved resd Kept at default value. Sample time selection of channel ADC_IN27 000: 2.5 cycles 001: 6.5 cycles 010: 12.5 cycles... -
Page 376: Adc Ordinary Sequence Register 4 (Adc_Osq4)
AT32F423 Series Reference Manual 011: 24.5 cycles 100: 47.5 cycles 101: 92.5 cycles 110: 247.5 cycles 111: 640.5 cycles Sample time selection of channel ADC_IN21 000: 2.5 cycles 001: 6.5 cycles 010: 12.5 cycles Bit 5:3 CSPT21 011: 24.5 cycles 100: 47.5 cycles... -
Page 377: Adc Ordinary Sequence Register 6 (Adc_Osq6)
AT32F423 Series Reference Manual 18.5.18 ADC ordinary sequence register 6 (ADC_OSQ6) Accessed by words. Register Reset value Type Description Kept at default value. Bit 31:20 Reserved resd Bit 19:15 OSN32 0x00 Number of 32nd conversion in ordinary sequence Bit 14:10... -
Page 378: Adc Calibration Value Register (Adc_Calval)
AT32F423 Series Reference Manual 18.5.20 ADC calibration value register (ADC_CALVAL) Accessed by words. Register Reset value Type Description Bit 31: 7 Reserved 0x0000 resd Kept at default value Bit 6: 0 CALVAL A/D Calibration value 18.5.21 ADC common control register (ADC_CCTRL) Accessed by words. -
Page 379: Digital-To-Analog Converter (Dac)
AT32F423 Series Reference Manual 19 Digital-to-analog converter (DAC) 19.1 DAC introduction The DAC uses a 12-bit digital input to generate an analog output between 0 and reference voltage. The digital part of the DAC can be configured in 8-bit or 12-bit mode and can be used in conjunction with the DMA. -
Page 380: Functional Overview
AT32F423 Series Reference Manual DMA underflow When the DAC DMA feature is enabled, an overflow occurs if a second external trigger arrives before the acknowledgement for the first external trigger is received. In this case, no new external trigger is handled, and no new DMA request is issued, and the DxDMAUDRF bit in the DAC_SR register is set, reporting the error. -
Page 381: Figure 19-2 Lfsr Register Calculation Algorithm
AT32F423 Series Reference Manual Figure 19-2 LFSR register calculation algorithm The DxNBSEL [3: 0] bit in the DAC_CTRL register is set to mark partially or totally LFSR data. The resulting LSFR value is then added up to the DHRx value without overflow and this value is loaded into the DAC_DxODT register. -
Page 382: Dac Data Alignment
AT32F423 Series Reference Manual 19.4.3 DAC data alignment The DAC supports a single DAC and dual DAC mode. The data format is dependent on the selected configuration mode. Single DAC data format: 8-bit right alignment: load data into the DAC_DxDTH8R [7:0]... - Page 383 AT32F423 Series Reference Manual 0000: Unmask LSFR bit0 /Triangle amplitude is equal to 0001: Unmask LSFR bit[1: 0] /Triangle amplitude is equal to 3 0010: Unmask LSFR bit[2: 0] /Triangle amplitude is equal to 7 0011: Unmask LSFR bit[3: 0] /Triangle amplitude is equal...
- Page 384 AT32F423 Series Reference Manual 1: DAC1 DMA transfer enabled DAC1 noise bit select These bits are used to select the mark bit in noise generation mode or amplitude in triangular-wave generation mode. 0000: Unmask LSFR bit0/Triangle amplitude is equal to 1...
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Page 385: Dac Software Trigger Register (Dac_Swtrg)
AT32F423 Series Reference Manual 19.5.2 DAC software trigger register (DAC_SWTRG) Register Reset value Type Description Bit 31: 2 Reserved 0x0000 0000 resd Kept at default value DAC2 software trigger 0: DAC2 software trigger disabled 1: DAC2 software trigger enabled Bit 1... -
Page 386: Dac2 8-Bit Right-Aligned Data Holding Register (Dac_D2Dth8R)
AT32F423 Series Reference Manual 19.5.8 DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) Register Reset value Type Description Bit 31: 8 Reserved 0x000000 resd Kept at default value Bit 7: 0 D2DT8R 0x00 DAC2 8-bit right-aligned data 19.5.9 Dual DAC 12-bit right-aligned data holding register... -
Page 387: Controller Area Network (Can)
AT32F423 Series Reference Manual 20 Controller area network (CAN) 20.1 CAN introduction CAN (Controller Area Network) is a serial communication protocol for real-time and reliable data communication among nodes. It supports the CAN protocol version 2.0A and 2.0B. 20.2 CAN main features ... - Page 388 AT32F423 Series Reference Manual Baud rate formula: ���������������� = Nomal Bit Timimg ���������� ������ ������������ = t ��������_������ ��������1 ��������2 with = 1 x t ��������_������ �� = (1 + BTS1[3: 0]) x t ��������1 �� = (1 + BTS2[2: 0]) x t ��������2...
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Page 389: Figure 20-2 Frame Type
AT32F423 Series Reference Manual Figure 20-2 Frame type Inter-frame Inter-frame space or Data frame (standard identifier) space overload frame 44 + 8* N Ack field Data field CRC field Arbitration field Control field 8* N Inter-frame Inter-frame space or Data frame ( extended identifier) -
Page 390: Interrupt Management
AT32F423 Series Reference Manual 20.4 Interrupt management The CAN controller has four interrupt vectors that can be used to enable or disable interrupts by setting the CAN_INTEN register. Figure 20-3 Transmit interrupt generation TCIEN = 1 TX_INT TM0TCF = 1... -
Page 391: Design Tips
AT32F423 Series Reference Manual 20.5 Design tips The following information can be used as reference for CAN application development: Debug control When the system enters the debug mode, the CAN controller stops or continues to work normally, depending on the CANx_PAUSE bit in the DEBUG_CTRL register or the PTD bit in the CAN_MCTRL register. -
Page 392: Operating Modes
AT32F423 Series Reference Manual 20.6.2 Operating modes The CAN controller has three operating modes: Sleep mode After a system reset, the CAN controller is in Sleep mode. In this mode, the CAN clock is stopped to reduce power consumption and an internal pull-up resistance is disabled. However, the software can still access to the mailbox registers. -
Page 393: Message Filtering
AT32F423 Series Reference Manual Loop back mode is selected by setting the LBEN bit in the CAN_BTMG register. In this mode, The CAN only receives the level signal on its CANTX pin of its own node. Meanwhile, the CAN can send data to the external bus. -
Page 394: Figure 20-10 16-Bit Identifier Mask Mode
AT32F423 Series Reference Manual Figure 20-10 16-bit identifier mask mode CAN_FiFB1[15:5] CAN_FiFB1[4:0] Mask CAN_FiFB1[31:21] CAN_FiFB1[20:16] CAN_FiFB2[15:5] CAN_FiFB2[4:0] Mask CAN_FiFB2[31:21] CAN_FiFB2[20:16] Mapping SID[10:0] EID[17:15] Figure 20-11 16-bit identifier list mode CAN_FiFB1[15:8] CAN_FiFB1[7:0] CAN_FiFB1[31:24] CAN_FiFB1[23:16] CAN_FiFB2[15:8] CAN_FiFB2[7:0] CAN_FiFB2[31:24] CAN_FiFB2[23:16] SID[10:0] EID[17:15] Mapping Filter match number 14 filter banks have different filtering effects dependent on the bit width mode. -
Page 395: Message Transmission
AT32F423 Series Reference Manual CAN_F10FB2[31:16]- CAN_F11FB2[31:0]-ID Mask CAN_F12FB1[15:0]-ID CAN_F13FB1[15:0]-ID CAN_F13FB1[31:16]- CAN_F12FB1[31:16]-ID CAN_F12FB2[15:0]-ID CAN_F13FB2[15:0]-ID CAN_F13FB2[31:16]- CAN_F12FB2[31:16]-ID Priority rules It may occur that CAN controller receives a frame of message that pass through several filters successfully. In this case, the filter match number stored in the receive mailbox is determined according to the following priority rules: ... -
Page 396: Figure 20-12 Transmit Mailbox Status
AT32F423 Series Reference Manual Figure 20-12 Transmit mailbox status EMPTY Send request(TMSR = 1) Abort sending(TMxCT = 1) PENDING Is it the highest priority Abort sending(TMxCT = 1) SCHEDULED Is the bus idle Send success or send failed with Send failed with automatic... -
Page 397: Message Reception
AT32F423 Series Reference Manual 20.6.6 Message reception Register configuration The CAN_RFIx (receive FIFO mailbox identifier register), CAN_RFCx (receive FIFO mailbox data length and time stamp register), CAN_RFDTLx (receive FIFO mailbox data register low) and CAN_RFDTHx (receive FIFO mailbox data register high) registers can be used by user applications to obtain valid messages. -
Page 398: Can Registers
AT32F423 Series Reference Manual Option 1: When AEBOEN=0 in the CAN_MCTRL register, in communication mode, the CAN will recover from bus-off state when the 128 occurrence of 11 consecutive recessive bits are detected on the CAN RX pin, and the software requests to enter Frozen mode and exit Frozen mode. - Page 399 AT32F423 Series Reference Manual FMCFG 204h 0x0000 0000 Reserved 208h FBWCFG 20Ch 0x0000 0000 Reserved 210h 214h 0x0000 0000 Reserved 218h FACFG 21Ch 0x0000 0000 Reserved 220h~23Fh F0FB1 240h 0xXXXX XXXX F0FB2 244h 0xXXXX XXXX F1FB1 248h 0xXXXX XXXX F1FB2...
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Page 400: Can Control And Status Registers
AT32F423 Series Reference Manual 20.7.1 CAN control and status registers 20.7.1.1 CAN master control register (CAN_MCTRL) Register Reset value Type Description Bit 31: 17 Reserved 0x0000 resd Kept at default value. Prohibit trans when debug 0: Transmission works during debug 1: Transmission is prohibited during debug. -
Page 401: Can Master Status Register (Can_Msts)
AT32F423 Series Reference Manual to be set by hardware, that is, the CAN will keep in sleep mode, by default. Freeze mode enable 0: Freeze mode disabled 1: Freeze mode enabled Note: The CAN leaves Freeze mode once 11 consecutive recessive bits have been detected on the RX pin. -
Page 402: Can Transmit Status Register (Can_Tsts)
AT32F423 Series Reference Manual register is enabled. When set, this bit will generate a status change interrupt. Doze mode acknowledge 0: The CAN is not in Sleep mode. 1: CAN is in Sleep mode. Note: This bit is used to decide whether the CAN is in Sleep mode or not. - Page 403 AT32F423 Series Reference Manual For example, in case of free CAN, the value of these two bit becomes 01 after a message transmit request is written. If the transmit box is full, these two bits refer to the number of the transmit mailbox with the lowest priority.
- Page 404 AT32F423 Series Reference Manual start of the next transmission Transmit mailbox 1 arbitration lost flag 0: No arbitration lost 1: Transmit mailbox 1 arbitration lost Note: Bit 10 TM1ALF rw1c This bit is set when the mailbox 1 transmission failed due to an arbitration lost.
- Page 405 AT32F423 Series Reference Manual bits of mailbox 0. 2023.04.25 Page 405 Rev 2.01...
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Page 406: Can Receive Fifo 0 Register (Can_Rf0)
AT32F423 Series Reference Manual 20.7.1.4 CAN receive FIFO 0 register (CAN_RF0) Register Reset value Type Description Bit 31: 6 Reserved 0x0000000 resd Kept at default value. Receive FIFO 0 release 0: No effect 1: Release FIFO Note: This bit is set by software to release FIFO 0. It is cleared... -
Page 407: Can Interrupt Enable Register (Can_Inten)
AT32F423 Series Reference Manual Receive FIFO 1 full flag 0: Receive FIFO 1 is not full 1: Receive FIFO 1 is full Bit 3 RF1FF rw1c Note: This bit is set by hardware when three messages are pending in the FIFO 1. - Page 408 AT32F423 Series Reference Manual 1: Receive FIFO 1 overflow interrupt enabled Note: The flag bit of this interrupt is the RF1OF bit. An interrupt is generated when this bit and RF1OF bit are set. Receive FIFO 1 full interrupt enable...
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Page 409: Can Error Status Register (Can_Ests)
AT32F423 Series Reference Manual 20.7.1.7 CAN error status register (CAN_ESTS) Register Reset value Type Description Receive error counter This counter is implemented in accordance with the Bit 31: 24 0x00 receive part of the fault confinement mechanism of the CAN protocol. -
Page 410: Can Mailbox Registers
AT32F423 Series Reference Manual Note: This field defines the number of time unit in Bit time segment 2. Bit time segment 1 tBTS1 = tCAN x (BTS1[3: 0] + 1) Bit 19: 16 BTS1 Note: This field defines the number of time unit in Bit time segment 1. -
Page 411: Transmit Mailbox Data Length And Time Stamp Register
AT32F423 Series Reference Manual 20.7.2.2 Transmit mailbox data length and time stamp register (CAN_TMCx) (x=0..2) All the bits in the register are write protected when the mailbox is not in empty state. Register Reset value Type Description Transmit mailbox time stamp... -
Page 412: Receive Fifo Mailbox Data Length And Time Stamp Register
AT32F423 Series Reference Manual 20.7.2.6 Receive FIFO mailbox data length and time stamp register (CAN_RFCx) (x=0..1) Note: All the receive mailbox registers are read only. Register Reset value Type Description Receive FIFO time stamp Bit 31: 16 RFTS 0xXXXX Note: This field contains the value of the CAN timer sampled at the start of a receive frame. -
Page 413: Can Filter Bit Width Configuration Register (Can_ Fbwcfg)
AT32F423 Series Reference Manual 20.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG) Note: This register can be written only when FCS=1 in the CAN_FCTRL register (The filter is in configuration mode) Register Reset value Type Description Bit 31: 14... -
Page 414: Universal Serial Bus Full-Seed Device Interface (Otgfs)
AT32F423 Series Reference Manual 21 Universal serial bus full-seed device interface (OTGFS) As a full-speed dual-role device, the OTGFS is fully compliant with the Universal Serial Bus Specification Revision2.0. 21.1 OTGFS structure Figure 21-1 hows the block diagram of the OTGFS structure. The OTGFS module is connected to the AHB and has a dedicated SRAM of 1280 bytes. -
Page 415: Otgfs Clock And Pin Configuration
AT32F423 Series Reference Manual pulse is output on PIN and the timer 2; an OE pulse generates when the OTGFS outputs data, the pulse is output on PIN. Suspend mode is supported. The OTGFS goes into power-saving mode after Suspend mode is entered. -
Page 416: Otgfs Interrupts
AT32F423 Series Reference Manual 21.4 OTGFS interrupts Figure 21-2 shows the OTGFS interrupt hierarchy. Refer to the OTGFS interrupt register (OTGFS_GINTSTS) and OTGFS interrupt mask register (OTGFS_GINTMSK). Figure 21-2 OTGFS interrupt hierarchy CORE Interrupt Global Interrupt Mask (Bit 0) AHB Configuration... -
Page 417: Otgfs Fifo Configuration
AT32F423 Series Reference Manual Non-periodic transmit FIFO empty level Periodic transmit FIFO empty level 2. Configure the following fields in the AHB global configuration register: OTGFS_GINTMSK.RXFLVLMSK = 0x0 3. Configure the following fields in the OTGFS_GUSBCFG register: ... -
Page 418: Host Mode
AT32F423 Series Reference Manual OTGFS_DIEPTXF0.INEPT0TXDEP = tx_fifo_size[0]; OTGFS_DIEPTXF0.INEPT0TXSTADDR = rx_fifo_size 3. Device IN endpoint transmit FIFO#1 size register (OTGFS_DIEPTXF1) OTGFS_DIEPTXF1.INEPTXFSTADDR = OTGFS_DIEPTXF0.INEPT0TXSTADDR + tx_fifo_size[0] 4. Device IN endpoint transmit FIFO#2 size register (OTGFS_DIEPTXF2) OTGFS_DIEPTXF2.INEPTXFSTADDR = OTGFS_DIEPTXF1.INEPTXFSTADDR + tx_fifo_size[1] 5. -
Page 419: Refresh Controller Transmit Fifo
AT32F423 Series Reference Manual OTGFS_GRXFSIZ.RXFDEP = rx_fifo_size 2. OTGFS Non-periodic TX FIFO size register (OTGFS_GNPTXFSIZ) OTGFS_GNPTXFSIZ.NPTXFDEP = tx_fifo_size[0] OTGFS_GNPTXFSIZ. NPTXFSTADDR = rx_fifo_size 3. OTGFS host periodic transmit FIFO size register (OTGFS_HPTXFSIZ) OTGFS_HPTXFSIZ.PTXFSIZE = tx_fifo_size[1] OTGFS_HPTXFSIZ.PTXFSTADDR = OTGFS_GNPTXFSIZ.NPTXFSTADDR + tx_fifo_size[0] 4. -
Page 420: Otgfs Channel Initialization
AT32F423 Series Reference Manual 21.5.3.2 OTGFS channel initialization To communicate with the device, the application must enable and initialize at least one channel according to the following steps: 1. Unmask the following interrupts by setting the OTGFS_GINTMSK register: Non-periodic transmit FIFO empty for OUT transfers ... -
Page 421: Figure 21-3 Writing The Transmit Fifo
AT32F423 Series Reference Manual queue before starting to write to the transmit FIFO. The application must always write to the transmit FIFO in WORDs. If the packet size is not aligned with WORD, the application must use padding. The OTGFS host determines the actual packet size according to the programmed maximum packet size and transfer size. -
Page 422: Special Cases
AT32F423 Series Reference Manual Figure 21-4 Reading the receive FIFO Start RXFLVL interrupt? Unmask RXFLVL Unmask RXFLVL Mask RXFLVL interrupt interrupt interrupt Read the received packet from the Read Receive FIFO GRXSTSP PKTSTS=0x2 ? BCNT > 0? 21.5.3.5 Special cases (1) Handling babble conditions The OTGFS controller handles two cases of babble: packet babble and port babble. -
Page 423: Figure 21-5 Hfir Behavior When Hfirrldctrl=0X0
AT32F423 Series Reference Manual Figure 21-5 shows the HFIR behavior when the HFIRRLDCTRL is set to 0x0 in the OTGFS_HFIR register. Figure 21-5 HFIR behavior when HFIRRLDCTRL=0x0 (3)SOF Lost Synchronization Due to HFIR Reload HFIR DN 0 400 399 0 400... -
Page 424: Initialize Bulk And Control In Transfers
AT32F423 Series Reference Manual Figure 21-6 HFIR behavior when HFIRRLDCTRL=0x1 (3)SOF Lost Synchronization NOT Lost Due to HFIR Reload HFIR DN 0 400 399 0 400 ******************** 1 ******************** ******************** Counter Application Load Of HFIR HFIR (6)SOF back in (2)HFIR Reloaded... - Page 425 AT32F423 Series Reference Manual receive FIFO 7. The application must read the receive packet status, and ignore it when the receive packet status is not an IN data packet 8. The controller generates the XFERC interrupt as soon as the receive packet is read 9.
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Page 426: Initialize Bulk And Control Out/Setup Transfers
AT32F423 Series Reference Manual Mask ACK else if (DATATGLERR) Reset Error Count 21.5.3.8 Initialize bulk and control OUT/SETUP transfers Figure 21-7 shows a typical bulk or control transfer OUT/SETUP transfer operation. Refer to channel 1 (ch_1) for more information. It is necessary to send two bulk transfer OUT packets. The control transfer SETUP operation is the same, just the fact that it has only one packet. -
Page 427: Figure 21-7 Example Of Common Bulk/Control Out/Setup And Bulk/Control In Transfer
AT32F423 Series Reference Manual Figure 21-7 Example of common Bulk/Control OUT/SETUP and Bulk/Control IN transfer Application Host Device init_reg(ch_1) Non-periodic Request init_reg(ch_2) Queue write_tx_fifo Assume that this queue can (ch_1) hold 4 entries. set_ch_en(ch_2) write_tx_fifo (ch_1) ch_1 set_ch_en(ch_2) ch_2 ch_1... -
Page 428: Initialize Interrupt In Transfers
AT32F423 Series Reference Manual Rewind Buffer Pointers Unmask CHHLTD Disable Channel if (XactErr) Increment Error Count Unmask ACK else Reset Error Count else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (Do ping protocol for HS) - Page 429 AT32F423 Series Reference Manual 3. The OTGFS host writes an IN request to the periodic request queue each time the CHENA is set in the OTGFS_HCCHAR2 register 4. The OTGFS host attempts to send an IN token in the next frame (odd) 5.
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Page 430: Initialize Interrupt Out Transfers
AT32F423 Series Reference Manual else if (XACTERR) Increment Error Count Unmask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) -
Page 431: Figure 21-8 Shows An Example Of Common Interrupt Out/In Transfers
AT32F423 Series Reference Manual Figure 21-8 shows an example of common interrupt OUT/IN transfers Application Host Device init_reg(ch_1) Periodic Request Queue init_reg(ch_2) Assume that this queue can hold 4 entries. write_tx_fifo (ch_1) set_ch_en(ch_2) ch_1 ch_2 Odd (micro) frame DATA0 XFERC... -
Page 432: Initialize Synchronous In Transfers
AT32F423 Series Reference Manual Reset Error Count Mask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) Reset Error Count... -
Page 433: Initialize Synchronous Out Transfers
AT32F423 Series Reference Manual not an IN packet (GRXSTSR.PKTSTS!= 0x0010) 8. The controller generates an XFERC interrupt as soon as the receive packet is read 9. To handle the XFERC interrupt, read the PKTCN bit in the OTGFS_HCTSIZ2 register. If the PKTCNT bit in the OTGFS_HCTSIZ2 is not equal to 0, disable the channel before re-initializing the channel for the next transfer. -
Page 434: Figure 21-9 Example Of Common Synchronous Out/In Transfers
AT32F423 Series Reference Manual The sequence of operations shown in Figure 21-9 (channel 2) is as follows: 1. Initialize channel 1 (according to OTGFS channel initialization requirements). The application must set the ODDFRM bit in the OTGFS_HCCHAR2 register 2. Write the first packet to the channel 1 3. -
Page 435: Otgfs Device Mode
AT32F423 Series Reference Manual Disable Channel else if (CHHLTD) Mask CHHLTD De-allocate Channel 21.5.4 OTGFS device mode 21.5.4.1 Device initialization The application must perform the following steps to initialize the controller during power-on or after switching from host mode to device mode: 1. -
Page 436: Endpoint Initialization On Enumeration Completion
AT32F423 Series Reference Manual 6. Program the following fields in the endpoint-specific registers to ensure that control OUT endpoint 0 is able to receive a SETUP packet OTGFS_DOEPTSIZ0.SUPCNT = 0x3(to receive up to 3 consecutive SETUP packets) At this point, all initialization required to receive SETUP packets is done. -
Page 437: Usb Endpoint Deactivation
AT32F423 Series Reference Manual Endpoint type Transmit FIFO number 2. Once the endpoint is activated, the controller starts decoding the tokens issued to this endpoint and sends out a valid handshake for each valid token received for the endpoint 21.5.4.7 USB endpoint deactivation... -
Page 438: Control Transfers (Setup/Status In)
AT32F423 Series Reference Manual If the last SETUP packet received before the generation of the SETUP interrupt indicates data IN stage, program the controller to perform IN transfers based on Non-periodic IN data transfer operation The application can receive up to 64-byte data for a single IN data transfer of control endpoint 0. If... -
Page 439: Out Data Transfers
AT32F423 Series Reference Manual Setup stage done mode: PKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num and DPID = Don’t Care (0x00), indicating the completion of the Setup stage for the specified endpoint, and the start of the data stage. After this request is popped from the receive FIFO, the controller triggers a Setup interrupt on the specified control OUT endpoint ... - Page 440 AT32F423 Series Reference Manual must be programmed to be a non-zero value. When the application sets the SUPCNT bit to a non- zero value, the controller receives SETUP packets and writes them to the receive FIFO, irrespective of the NAK status bit and EPENA bit in the OTGFS_DOEPCTLx register. The SUPCNT bit is decremented each time the control endpoint receives a SETUP packet.
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Page 441: In Data Transfers
AT32F423 Series Reference Manual Figure 21-11 SETUP data packet flowchart Waiting for DOEPINTn.SETUP B2BSTUP Interrupt bit set? rem_supcnt = setup_addr = rd_reg(DOEPTSIZn) rd_reg(DOEPDMAn) setup_cmd[31:0] = mem[4-2* rem_supcnt] setup_cmd[31:0] = mem[setup_addr-8] setup_cmd[63:32] = mem[5-2* rem_supcnt] setup_cmd[63:32] = mem[setup_addr-4] Find setup cmd type... -
Page 442: Non-Periodic (Bulk And Control) In Data Transfers
AT32F423 Series Reference Manual Normally, except for setting the endpoint enable bit, the application must do a read modify write on the OTGFS_DIEPCTLx register to avoid modifying the contents of the register. If the space is enough, the application can write multiple data packets for the same endpoint into the transmit FIFO. For the periodic IN endpoints, the application must write packets for only one frame. -
Page 443: Non-Synchronous Out Data Transfers
AT32F423 Series Reference Manual length packets according to the IN token, and the packet count is decremented automatically. 6. If there are no data in the FIFO on a received IN token and the packet count for the endpoint is 0, the controller generates an “IN token received when FIFO is empty”... - Page 444 AT32F423 Series Reference Manual If there is no space in the receive FIFO, synchronous or non-synchronous data packets are ignored and not written to the receive FIFO. Besides, the non-synchronous OUT tokens receive a NAK handshake response. In all the above-mentioned cases, the packet count is not decremented because no data is written to the receive FIFO.
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Page 445: Synchronous Out Data Transfers
AT32F423 Series Reference Manual Figure 21-12 BULK OUT transfer block diagram Host Device Application XFERSIZE = 512bytes int_out_ep PKTCNT = 1 wr_reg(DOEPTSIZn) EPENA = 1 CNAK = 1 wr_reg(DOEPCTLn) 512 bytes xact_1 idle until intr On new xfer or RXFIFO not... -
Page 446: Enable Synchronous Endpoints
AT32F423 Series Reference Manual 1. All the application requirements are the same as that of non-synchronous OUT data transfers. 2. For synchronous OUT data transfers, the transfer size and packet count must be set to the number of the largest-packet-size packets that can be received in a single frame and not exceed this size. - Page 447 AT32F423 Series Reference Manual Instead, synchronous support in the OTGFS controller is based on a single-transfer level. The application must re-configure the controller on every frame. The OTGFS controller enables the synchronous endpoint of the frame before the frame to be transmitted.
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Page 448: Incomplete Synchronous Out Data Transfers
AT32F423 Series Reference Manual (2) Late data write to the receive FIFO. An IN token has arrived before the completion of data write (3) IN token error The INCOMPISOIN interrupt in the OTGFS_GINTSTS register is a global interrupt. Therefore, when more than one synchronous endpoints are in active state, the application must determine which one of the synchronous IN endpoints has not yet completed data transfers. -
Page 449: Incomplete Synchronous In Data Transfers
AT32F423 Series Reference Manual ensure that the current frame number is not changed. 5. For synchronous OUT endpoints with incomplete transfers, the application must drop the data in memory, and disable the endpoint through the endpoint disable bit in the OTGFS_DOEPCTLx register. - Page 450 AT32F423 Series Reference Manual Transfer size [epnum] = n * mps[epnum] + sp (where n and i are integers ≥ 0, and 0 ≤ sp < mps[epnum]) If (sp > 0), packet count [epnum] = n + 1. Otherwise, packet count [epnum] = n, mc[epnum] = packet count [epnum] ...
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Page 451: Otgfs Control And Status Registers
AT32F423 Series Reference Manual interrupt IN endpoints. 7.The assertion of the XFERC interrupt in the OTGFS_DIEPINTx register but without the INTKNTXFEMP interrupt indicates the successful completion of a synchronous IN transfer. When reading the OTGFS_DIEPTSIZx register, only transfer size =0 and packet count =0 indicate that all data are transmitted on the USB line. -
Page 452: Otgfs Register Address Map
AT32F423 Series Reference Manual Figure 21-13 CSR memory map 0000h The overall situation of the core CSRs(1024 byte) 0400h Host mode CSRs (1024 byte) 0800h Device mode CSRs (1024 byte) 0E00h Power and clock control CSRs (512 byte) 1000h Equipment EP 0/host channel 0 FIFO (4096 byte) - Page 453 AT32F423 Series Reference Manual OTGFS_GAHBCFG 0x008 0x0000 0000 OTGFS_GUSBCFG 0x00C 0x0000 1400 OTGFS_GRSTCTL 0x010 0x2000 0000 OTGFS_GINTSTS 0x014 0x0400 0020 OTGFS_GINTMSK 0x018 0x0000 0000 OTGFS_GRXSTSR 0x01C 0x0000 0000 OTGFS_GRXSTSP 0x020 0x0000 0000 OTGFS_GRXFSIZ 0x024 0x0000 0200 OTGFS_GNPTXFSIZ 0x028 0x0000 0200...
- Page 454 AT32F423 Series Reference Manual OTGFS_HCINT1 0x528 0x0000 0000 OTGFS_HCINTMSK1 0x52C 0x0000 0000 OTGFS_HCTSIZ1 0x530 0x0000 0000 OTGFS_HCCHAR2 0x540 0x0000 0000 OTGFS_HCINT2 0x548 0x0000 0000 OTGFS_HCINTMSK2 0x54C 0x0000 0000 OTGFS_HCTSIZ2 0x550 0x0000 0000 OTGFS_HCCHAR3 0x560 0x0000 0000 OTGFS_HCINT3 0x568 0x0000 0000...
- Page 455 AT32F423 Series Reference Manual OTGFS_HCINTMSK11 0x66C 0x0000 0000 OTGFS_HCTSIZ11 0x670 0x0000 0000 OTGFS_HCCHAR12 0x680 0x0000 0000 OTGFS_HCINT12 0x688 0x0000 0000 OTGFS_HCINTMSK12 0x68C 0x0000 0000 OTGFS_HCTSIZ12 0x690 0x0000 0000 OTGFS_HCCHAR13 0x6A0 0x0000 0000 OTGFS_HCINT13 0x6A8 0x0000 0000 OTGFS_HCINTMSK13 0x6AC 0x0000 0000...
- Page 456 AT32F423 Series Reference Manual OTGFS_DTXFSTS3 0x978 0x0000 0200 OTGFS_DIEPCTL4 0x980 0x0000 0000 OTGFS_DIEPINT4 0x988 0x0000 0080 OTGFS_DIEPTSIZ4 0x990 0x0000 0000 OTGFS_DTXFSTS4 0x998 0x0000 0200 OTGFS_DIEPCTL5 0x9A0 0x0000 0000 OTGFS_DIEPINT5 0x9A8 0x0000 0080 OTGFS_DIEPTSIZ5 0x9B0 0x0000 0000 OTGFS_DTXFSTS5 0x9B8 0x0000 0200...
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Page 457: Otgfs Global Registers
AT32F423 Series Reference Manual OTGFS_PCGCCTL 0xE00 0x0000 0000 21.6.3 OTGFS global registers These registers are available in both host and device modes, and do not need to be reprogrammed when switching between two modes. 21.6.3.1 OTGFS status and control register (OTGFS_GOTGCTL) This register controls the OTG function and reflects its status. -
Page 458: Otgfs Usb Configuration Register (Otgfs_Gusbcfg)
AT32F423 Series Reference Manual Bit 6: 1 Reserved 0x00 resd Kept at default value. Accessible in both host mode and device modes Global interrupt mask The application uses this bit to mask or unmask the Bit 0 GLBINTMSK interrupts sent by the interrupt line to itself. -
Page 459: Otgfs Reset Register (Otgfs_Grstctl)
AT32F423 Series Reference Manual 21.6.3.5 OTGFS reset register (OTGFS_GRSTCTL) The application resets various hardware modules in the controller through this register. Register Reset value Type Description Accessible in both host mode and device modes AHB master Idle Bit 31 AHBIDLE This bit indicates that the AHB master state machine is in idle condition. -
Page 460: Otgfs Interrupt Register (Otgfs_Gintsts)
AT32F423 Series Reference Manual a frame number of 0. If the application writes 1 to this bit, it may not be able to read the value, because this bit is cleared after a few clock cycles by the controller Accessible in both host mode and device modes... - Page 461 AT32F423 Series Reference Manual In device mode, this interrupt is generated only when a resume signal (triggered by host) is detected on the USB bus. In host mode, this interrupt is generated only when a remote wakeup signal (triggered by device) is detected on the USB bus.
- Page 462 AT32F423 Series Reference Manual pending on one of the OUT endpoints in the controller. The application must read the Device All Endpoints Interrupt register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-n Interrupt register to determine the exact source of the interrupt.
- Page 463 AT32F423 Series Reference Manual bit in the Device Control register (set by the application) has taken effect. That is, the controller has sampled the Global IN NAK bit set by the application. This bit can be cleared by writing the Clear Global Non-periodic IN NA bit in the Device Control register.
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Page 464: Otgfs Interrupt Mask Register (Otgfs_Gintmsk)
AT32F423 Series Reference Manual Current mode of operation This bit indicates the current mode. 0: Device mode 1: Host mode 21.6.3.7 OTGFS interrupt mask register (OTGFS_GINTMSK) This register works with the Interrupt Register to interrupt the application. When an interrupt bit is masked, the interrupt related to this interrupt bit is not generated. -
Page 465: Otgfs Receive Status Debug Read/Otg Status Read And Pop Registers (Otgfs_Grxstsr / Otgfs_Grxstsp)
AT32F423 Series Reference Manual Start of Frame mask Accessible in both host and device modes Bit 2 OTGINTMSK OTG interrupt mask Accessible in both host and device modes Bit 1 MODEMISMSK Mode mismatch interrupt mask Bit 0 Reserved resd Kept at default value. -
Page 466: Otgfs Receive Fifo Size Register (Otgfs_Grxfsiz)
AT32F423 Series Reference Manual 01: DATA2 11: MDATA Byte count Bit 14: 4 BCNT 0x000 Indicates the byte count of the received data packet. Endpoint number Bit 3: 0 EPTNUM Indicates the endpoint number to which the currently received data packet belongs. -
Page 467: Otgfs General Controller Configuration Register
AT32F423 Series Reference Manual Indicates the amount of space available in the non- periodic transmit request queue. This queue supports both IN and OUT requests in host mode. 00: Non-periodic transmit request queue is full 01: 1 location available 02: 2 locations available N: n locations available (0 ≤... -
Page 468: Otgfs Device In Endpoint Tx Fifo Size Register
AT32F423 Series Reference Manual The power-on reset value of this register is the sum of the largest receive FIFO depth and the largest non-periodic transmit FIFO depth. 21.6.3.15 OTGFS device IN endpoint Tx FIFO size register (OTGFS_DIEPTXFn) (x=1…7, where n is the FIFO number) This register holds the depth and memory start address of the IN endpoint transmit FIFO in device mode. -
Page 469: Otgfs Host Frame Number/Frame Time Remaining Register (Otgfs_Hfnum)
AT32F423 Series Reference Manual 1: Reload control disable 0: Reload control enable This bit must be configured at initialization. Do not change its value at runtime. Frame interval The application uses this filed to program the interval between two consecutive SOFs (full speed) The number of PHY locks in this field indicates the frame interval. -
Page 470: Otgfs Host All Channels Interrupt Register (Otgfs_Haint)
AT32F423 Series Reference Manual N: n space available (0 ≤ n ≤ 8) Others: Reserved Periodic transmit data FIFO space available Indicates the number of free space available to be written in the periodic transmit FIFO, in terms of 32-bit words. - Page 471 AT32F423 Series Reference Manual The application uses this bit to control power supply to this port (by writing 1 or 0) 0: Power off 1: Power on Note: This bit is not associated with interfaces. The application must follow the programming manual to set this bit for various interfaces.
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Page 472: Otgfs Host Channelx Characteristics Register (Otgfs_Hccharx)
AT32F423 Series Reference Manual Port enable/disable change The controller sets this bit when the status of the port Bit 3 PRTENCHNG rw1c enable bit 2 in this register changes. This bit can only be set by the controller. The application must write 1 to clear this bit. -
Page 473: Otgfs Host Channelx Interrupt Register (Otgfs_Hcintx)
AT32F423 Series Reference Manual The application sets this bit to indicate that this channel is communicating to a low-speed device. Bit 16 Reserved resd Kept at default value. Endpoint direction Indicates whether the transfer is in IN or OUT. Bit 15... -
Page 474: Otgfs Host Channelx Interrupt Mask Register (Otgfs_Hcintmskx)
AT32F423 Series Reference Manual 21.6.4.10 OTGFS host channelx interrupt mask register (OTGFS_HCINTMSKx) (x = 0...15, where x= channel number) This register is used to mask the channels described in the previous section. Register Reset value Type Description Bit 31: 11... -
Page 475: Otgfs Device Control Register (Otgfs_Dctl)
AT32F423 Series Reference Manual 01: 85% of the frame interval 10: 90% of the frame interval 11: 95% of the frame interval Device address Bit 10: 4 DEVADDR 0x00 The application must program this field every time a SetAddress command is received. -
Page 476: Otgfs Device Status Register (Otgfs_Dsts)
AT32F423 Series Reference Manual 0: A handshake is sent based on the FIFO status, NAK and STALL bit settings. 1: No data is written to the receive FIFO, irrespective of space availability. Sends a NAK handshake on all packets (except on SETUP transfers). Drops all synchronous OUT packets. -
Page 477: Otgfs Device Otgfsin Endpoint Common Interrupt Mask Register (Otgfs_Diepmsk)
AT32F423 Series Reference Manual Indicates the speed at which the controller has determined after speed detection through a sequence. 01: Reserved 10: Reserved 11: Full speed (PHY clock is running at 48MHz) Others: Reserved Suspend status In device mode, this bit is set as long as a suspend condition is detected on the USB bus. -
Page 478: Otgfs Device All Endpoints Interrupt Mask Register (Otgfs_Daint)
AT32F423 Series Reference Manual 1: Interrupt unmasked OUT packet error mask Bit 8 OUTPERRMSK 0: Interrupt masked 1: Interrupt unmasked Bit 7 Reserved resd Kept at default value. Back-to-back SETUP packets received mask Bit 6 B2BSETUPMSK 0: Interrupt masked 1: Interrupt unmasked... -
Page 479: Otgfs Device In Endpoint Fifo Empty Interrupt Mask Register (Otgfs_Diepempmsk)
AT32F423 Series Reference Manual 21.6.5.8 OTGFS device IN endpoint FIFO empty interrupt mask register (OTGFS_DIEPEMPMSK) This register works with the TXFE_OTGFS_DIEPINTx register to generate an interrupt. Register Reset value Type Description Bit 31: 8 Reserved 0x0000 resd Kept at default value. -
Page 480: Otgfs Device In Endpoint-X Control Register (Otgfs_Diepctlx)
AT32F423 Series Reference Manual handshake, irrespective of this bit’s setting. Bit 16 Reserved resd Kept at default value. USB active endpoint This bit is always set to 1, indicating that the control Bit 15 USBACEPT endpoint 0 is always active in all configurations and interfaces. - Page 481 AT32F423 Series Reference Manual Values: 0: Do not set NAK 1: Set NAK Clear NAK A write to this bit clears the NAK bit for this endpoint. Bit 26 CNAK 0: Not clear NAK 1: Clear NAK TxFIFO number Allocate FIFO number to the corresponding endpoint. A...
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Page 482: Otgfs Device Control Out Endpoint 0 Control Register (Otgfs_Doepctl0)
AT32F423 Series Reference Manual through the SETEVNFR and SETODDFR bits in this register. 0: Even frame 1: Odd frame USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The controller clears this bit for all endpoints except for endpoint 0 after detecting a... -
Page 483: Otgfs Device Control Out Endpoint-X Control Register
AT32F423 Series Reference Manual – When this bit is set (either by the application or the controller), the controller stops receiving any data on an OUT endpoint, even if there is space in the receive FIFO. The controller always responds to SETUP data packets with an ACK handshake, regardless of whether this bit is set or not. - Page 484 AT32F423 Series Reference Manual 1: Set DATA0PID or set the EOFRNUM to even frame Set NAK A write to this bit sets the NAK bit for the endpoint. The application uses this bit to control the transmission of NAK handshakes on an endpoint. The controller sets this...
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Page 485: Otgfs Device In Endpoint-X Interrupt Register (Otgfs_Diepintx)
AT32F423 Series Reference Manual Applies to synchronous OUT endpoints only. Indicates the frame number in which the controller transmits synchronous data on this endpoint. The application must program the even/odd frame number in which it tends to transmit or receive synchronous data through the SETEVNFR and SETODDFR bits in this register. -
Page 486: Otgfs Device Out Endpoint-X Interrupt Register
AT32F423 Series Reference Manual to the application’s request. Transfer completed interrupt Bit 0 XFERC rw1c Indicates that the programmed transfers are complete on the AHB and on the USB for this endpoint. 21.6.5.14 OTGFS device OUT endpoint-x interrupt register (OTGFS_DOEPINTx) (x=0…7, where x if endpoint number) - Page 487 AT32F423 Series Reference Manual from the external memory is written to the transmit FIFO. 2023.04.25 Page 487 Rev 2.01...
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Page 488: Otgfs Device Out Endpoint 0 Transfer Size Register
AT32F423 Series Reference Manual 21.6.5.16 OTGFS device OUT endpoint 0 transfer size register (OTGFS_DOEPTSIZ0) The application must set this register before enabling endpoint 0. Once the endpoint 0 is enabled using the endpoint enable pin in the device endpoint 0 control register, the controller modifies this register. The application can only read this register as long as the controller clears the endpoint enable bit. -
Page 489: Otgfs Device In Endpoint Transmit Fifo Status Register
AT32F423 Series Reference Manual 21.6.5.18 OTGFS device IN endpoint transmit FIFO status register (OTGFS_DTXFSTSx) (x=1…7, where x is endpoint number) This is a ready-only register containing the free space information for the device IN endpoint transmit FIFO. Register Reset value... -
Page 490: Power And Clock Control Registers
AT32F423 Series Reference Manual 21.6.6 Power and clock control registers 21.6.6.1 OTGFS power and clock gating control register (OTGFS_PCGCCTL) This register is available in host and device modes. Register Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at its default value. -
Page 491: Hick Auto Clock Calibration (Acc)
AT32F423 Series Reference Manual 22 HICK auto clock calibration (ACC) 22.1 ACC introduction HICK auto clock calibration (HICK ACC), which uses the SOF signal (1 ms of period) generated as a reference signal, implements the sampling and calibration for the HICK clocks. -
Page 492: Figure 22-2 Acc Block Diagram
AT32F423 Series Reference Manual CRM_HICKTWK: the HICKTWK bit in the CRM module. This signal is used to calibrate the HICK in bypass mode. The value is defined by the HICKTWK[5: 0] in the CRM_CTRL register. CRM_HICKTRIM: the HICKTRIM bit in the CRM module. This signal is used to calibrate the HICK in bypass mode. -
Page 493: Principle
AT32F423 Series Reference Manual 22.5 Principle USB_SOF period signal: 1ms of period must be accurate, which is a prerequisite of the normal operation for an auto calibration module. cross-return algorithm: This is used to calculate a calibration value closest to the theoretic value. In theory, the actual frequency after calibration can be adjusted to be within an accuracy range of about 0.5 steps from the target frequency (8MHz). -
Page 494: Register Description
AT32F423 Series Reference Manual 22.6 Register description Refer to the list of abbreviations used in register descriptions. These peripheral registers must be accessed by words (32 bits). 22.6.1 ACC register map Table 22-2 ACC register map and reset values Register name... -
Page 495: Control Register 2 (Acc_Ctrl2)
AT32F423 Series Reference Manual relationship. Bit 7: 6 Reserved Forced by hardware to 0 CALRDY interrupt enable This bit is set or cleared by software. Bit 5 CALRDYIEN 0: Interrupt generation disabled 1: ACC interrupt is generated when CALRDY=1 in the... -
Page 496: Compare Value 2 (Acc_C2)
AT32F423 Series Reference Manual is not enabled. 22.6.6 Compare value 2 (ACC_C2) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Forced to 0 by hardware Compare 2 This value defines the number of clocks sampled for 8MHz (ideal frequency) clock in 1ms period , and its... -
Page 497: Infrared Timer (Irtmr)
AT32F423 Series Reference Manual 23 Infrared timer (IRTMR) The IRTMR (Infrared Timer) is used to generate the IR_OUT signal that drives the infrared LED to achieve infrared control. The IR_OUT signals consists of a low-frequency modulation envelope and high-frequency carrier signals. -
Page 498: External Memory Controller (Xmc)
AT32F423 Series Reference Manual 24 External memory controller (XMC) 24.1 XMC introduction XMC block is able to translate the AHB transactions into external memory signals and vice versa.It features two chip-select signals at different pins, for interfacing up to two external memories at a time. -
Page 499: Xmc Architecture
AT32F423 Series Reference Manual 24.3 XMC architecture 24.3.1 Block diagram Figure 24-1 XMC block diagram Address/Data bus XMC registers AHB XMC memory AHB interface interface Central memory XMC_A[23:16] controller XMC_D[15:0] XMC_NOE XMC_NWE XMC_NWAIT NOR/PSRAM memory interface XMC_NE[4:1] XMC_NADV XMC_LB XMC_UB XMC_CLK While interfacing to the external memory, NOR/PSRAM use different pins as shown in . -
Page 500: Address Mapping
AT32F423 Series Reference Manual 24.3.2 Address mapping XMC addresses are divided into multiple memory banks, as shown below. Figure 24-2 XMC memory banks Memory Address Memory banks chip select signals 6000 0000h NOR/PSRAM bank1 16 MB XMC_NE[1] 60FF FFFFh Reserved... -
Page 501: Operating Mode
AT32F423 Series Reference Manual 24.4.1 Operating mode Pin function: Pin signals vary from one external memory to another. Table 24-3 lists typical pin signals. Table 24-3 Pin signals for NOR and PSRAM XMC pin name NOR Flash PSRAM XMC_CLK Clock (synchronous mode) -
Page 502: Access Mode
AT32F423 Series Reference Manual Asynchronous read/write Asynchronous Split into 2 XMC accesses read/write Synchronous Use XMC_LB and XMC_UB write Synchronous read/write Synchronous Split into 2 XMC accesses read/write 24.4.2 Access mode The XMC offers various access modes. Each access mode is operated based on timing parameters as... -
Page 503: Figure 24-3 Nor/Psram Multiplexed Mode Read Access
AT32F423 Series Reference Manual Table 24-8 Multiplexed mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) configuration Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode Bit 27: 24 DTLAT: Data latency CLKPSC: Clock frequency division Bit 23: 20... -
Page 504: Synchronous Mode
AT32F423 Series Reference Manual Figure 24-4 NOR/PSRAM multiplexed mode write access Don t care ADDRST+1 ADDRHT+1 DTST+2 HCLK HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[25：16] Memory address[25:16] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Address data Data from XMC XMC_D[15：0]... -
Page 505: Figure 24-5 Nor/Psram Synchronous Multiplexed Mode Read Access
AT32F423 Series Reference Manual ADMUXEN: Address/data multiplexing Bit 1 Configure according to needs. enable Bit 0 EN: Memory bank enable Table 24-10 Synchronous mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode... -
Page 506: Xmc Registers
AT32F423 Series Reference Manual Figure 24-6 NOR/PSRAM synchronous multiplexed mode write access DTLAT+1 t care XMC_CLK Clock XMC_CLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[25：16] Memory address[25:16] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Wait signal XMC_NWAIT Address data XMC_D[15：0]... -
Page 507: Nor Flash And Psram Control Registers
AT32F423 Series Reference Manual 24.5.1 NOR Flash and PSRAM control registers These peripherals registers have to be accessed by words (32 bits). 24.5.1.1 SRAM/NOR Flash chip select control register 1 (XMC_BK1CTRL1) Accessed by words Register Reset value Type Description Bit 31: 20... -
Page 508: Sram/Nor Flash Chip Select Control Register X (X=2, 4)
AT32F423 Series Reference Manual This field defines the external memory data bus width. 00: 8 bits 01: 16 bits 10: Reserved 11: Reserved Memory device type 00: SRAM/ROM Bit 3: 2 01: PSRAM (Cellular RAM or CRAM) 10: NOR Flash... -
Page 509: Sram/Nor Flash Chip Select Timing Register X (X=1,2,4)
AT32F423 Series Reference Manual NWAIT polarity This bit defines the polarity of the NWAIT signal in Bit 9 NWPOL synchronous mode. 0: NWAIT active low 1: NWAIT active high Synchronous burst enable This bit allows synchronous access to Flash memories. -
Page 510: Sram/Nor Flash Write Timing Register X (X=1,2,4)
AT32F423 Series Reference Manual …… 1111: 16 HCLK cycles are inserted Data setup time 0000: 0 HCLK cycle is inserted Bit 15: 8 DTST 0xFF 0001: 1 additional HCLK cycle is inserted …… 1111: 15 additional HCLK cycles are inserted... - Page 511 AT32F423 Series Reference Manual operations 00000001: 2 HCLK cycles are inserted for consecutive read operations …… 00001000: 9 HCLK cycles are inserted for consecutive read operations (default value) …… 11111111: 256 HCLK cycles are inserted for consecutive read operations Bus turnaround phase for consecutive write duration This field is used to define the bus turnaround phase duration for consecutive write operations.
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Page 512: Debug (Debug)
AT32F423 Series Reference Manual 25 Debug (DEBUG) 25.1 Debug introduction Cortex™-M4F core provides powerful debugging features including halt and single step support, as well as trace function that is used for checking the details of the program execution. The debug features are implemented with a serial wire debug interface. -
Page 513: Debug Device Id (Debug_Idcode)
AT32F423 Series Reference Manual 25.4.1 DEBUG device ID (DEBUG_IDCODE) MCU integrates an ID code that is used to identify MCU’s revision code. The DEBUG_IDCODE register is mapped on the external PPB bus at address 0xE0042000. This code is accessible by the SW debug port or by the user code. -
Page 514: Debug Apb1 Pause Register (Debug_ Apb1_Pause)
AT32F423 Series Reference Manual Debug Deepsleep mode control bit 0: In Deepsleep mode, all clocks in the 1.2V domain are disabled. When exiting from Deepsleep mode, the internal RC oscillator (HICK) is enabled, and HICK is used as the system clock source, and the software must... - Page 515 AT32F423 Series Reference Manual WWDT pause control bit Bit 11 WWDT_PAUSE 0: WWDT works normally 1: WWDT stops running ERTC pause control bit Bit 10 ERTC_PAUSE 0: ERTC works normally 1: ERTC stops running Bit 9 Reserved Kept at default value.
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Page 516: Debug Apb2 Pause Register (Debug_ Apb2_Pause)
AT32F423 Series Reference Manual 25.4.4 DEBUG APB2 pause register (DEBUG_ APB2_PAUSE) This register is asynchronously reset by POR Reset (not reset by system reset). It can be written by the debugger under reset. Register Reset value Type Description Bit 31: 19... -
Page 517: Revision History
AT32F423 Series Reference Manual 26 Revision history Document Revision History Date Version Revision Note Initial release. 2023.3.28 2.00 Updated description of the first page. 2023.4.25 2.01 2023.04.25 Page 517 Rev 2.01... - Page 518 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previous representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third party’s products or services...
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