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Introduction
This document is aimed at helping users with project development based on AT32F425xx MCUs.
Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by
Artery. For other versions of BSP, please pay attention to the differences in usage.
Applicable products:
Part number
2022.10.21
Getting Started with AT32F425
Getting Started with AT32F425
AT32F425xx
1
AN0129
Application Note
Ver 2.0.3
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Related Manuals for ARTERY AT32F425 Series
Summary of Contents for ARTERY AT32F425 Series
- Page 1 This document is aimed at helping users with project development based on AT32F425xx MCUs. Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by Artery. For other versions of BSP, please pay attention to the differences in usage. Applicable products:...
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Page 2: Table Of Contents
Getting Started with AT32F425 Contents Development resources .................. 5 Set up AT32 developm ent environment ................5 1.1.1 Debug tools and evaluation board ................5 1.1.2 Programming tools and software resources ............. 5 1.1.3 AT32 development environment................6 1.1.4 How to quickly replace AT32F415 with AT32F425 ..........12 AT32F425 functionality configuration ................ - Page 3 Getting Started with AT32F425 List of tables Table 1. Document revision history ....................25 2022.10.21 Ver 2.0.3...
- Page 4 List of figures Figure 1. AT_START_F425 and AT-Link-EZ ..................5 Figure 2. AT-START-F425 evaluation board package from ARTERY official website ....... 5 Figure 3. ICP/ISP/AT-Link-Family package on ARTERY official website .......... 6 Figure 4. BSP resources on ARTERY official website ..............6 Figure 5.
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Page 5: Development Resources
Resources Evaluation Board (download and unzip, and then go to “\AT_START_F425_Vx.x\03_Documents”). Figure 2. AT-START-F425 evaluation board package from ARTERY official website 1.1.2 Programming tools and software resources AT programming tools and software: AT-Link / AT-Link+ /AT-Link-Pro / AT-Link-ISO /AT-Link- EZ, and ICP/ISP 2022.10.21... -
Page 6: At32 Development Environment
Link_User_Manual_EN_Vx.x.x) Figure 3. ICP/ISP/AT-Link-Family package on ARTERY official website 1.1.3 AT32 development environment 1.1.3.1 Template project The frequently-used IDE template projects are included in ARTERY’s firmware BSP. You can get these resources by visiting ARTERY official website→Products→Value line→AT32F425 series→ BSP. -
Page 7: Figure 5. Keil_V5 Templates Template
Note: For details on BSP, refer to Section 4 of the document “AT32F425 _firmware_BSP&Pack_user_guide”, → which is available from ARTERY official website Products→Value line→AT32F425 series→BSP (download and unzip, and then go to “\AT32F425_Firmware_Library_Vx.x.x\document”). 1.1.3.2 Pack installation The installation of Pack is required to add AT32 MCU part number in Keil/IAR. -
Page 8: Figure 6. Pack Resources On Artery Official Website
Getting Started with AT32F425 Figure 6. Pack resources on ARTERY official website For the Keil compiling system, Keil 4.74, Keil 5.23 and above versions are recommended. For Keil_v5, users need to unzip the “Keil5_AT32MCU_AddOn” and then install the “ArteryTek.AT32F425_DFP”. For Keil_v4, users directly install the “Keil4_AT32MCU_AddOn”. -
Page 9: Figure 9. Click "Pack Installer" In Keil
→ which is available from ARTERY official website Products→Value line→AT32F425 series→BSP (download and unzip, and then go to “\AT32F425_Firmware_Library_Vx.x.x\document”). 1.1.3.3 Debug and download with AT-Link tool If AT-Link is to be used in Keil environment, click “Debug”, and then choose “CMSIS-DAP Debugger”. -
Page 10: Figure 11. Keil Debug Option
“ Note: For more information on WinUSB, refer to FAQ0136_How_to_use_AT-LINK_WinUSB_EN_V2.0.0”, which is available from ARTERY official website→Support→FAQ→FAQ0136. In “Port” option, choose “SW”, and then tick “SWJ” option; Confirm that the “ARM SW-DP” is recognized. Figure 12. Settings option in Keil Debug Then, click “Utilities”→untick “Use Debug Driver”... -
Page 11: Figure 13. Keil Utilities Option
Getting Started with AT32F425 Figure 13. Keil Utilities option If AT-Link is to be used in IAR environment, click “Project”→choose “Options” →go to “Debugger” and choose “CMSIS-DAP”→tick “SWD”. Figure 14. IAR Debug option 2022.10.21 Ver 2.0.3... -
Page 12: How To Quickly Replace At32F415 With At32F425
Note: The document “AT32F425firmware_BSP&Pack_user_guide” provides details on Flash algorithms, MCU → product series replacement and J-Link. This document is available from ARTERY official website Products→Value line→AT32F425 series→BSP (download and unzip, and then go to “\AT32F425_Firmware_Library_Vx.x.x\document”). 1.1.4 How to quickly replace AT32F415 with AT32F425 ... -
Page 13: Pll Clock Configuration
Getting Started with AT32F425 Figure 16. Wait state bit in FLASH_PSR register AT32 library has made relevant settings in the “system_clock_config()” function. For BSP of other AT32 MCU series, you can also find this settings at the same location. Figure 17. system_clock_config function 1.2.2 PLL clock configuration AT32F425 embeds a PLL with a maximum of 96 MHz clock output. -
Page 14: Encryption
1.2.3 Encryption Note: The BOOT1 bit of AT32F425 series is located in the user system data area (0x1FFF F800). When ISP tool is used, it is mandatory to ensure that nBOOT1=1 is asserted (default value) so that the program is booted from system memory instead of SRAM. -
Page 15: Figure 20. Use Isp To Enable Access Protection
Getting Started with AT32F425 Unlock access protection: Tick “Protection” -- choose “Disable” and “Access protection” -- click “Start”. Figure 20. Use ISP to enable access protection Figure 21. Use ISP to disable access protection Note: Access protection, after being enabled, cannot be unlocked through erase operation . 2022.10.21 Ver 2.0.3... -
Page 16: Figure 22. Use Icp Tool To Enable Erase/Program Protection
Enable erase/program protection: Are you sure to enable erase/program protection?--Yes. Disable erase/program protection: Are you sure to disable erase/program protection?--Yes. Artery ISP Multi-Port Programmer (BOOT0=1) Enable erase/program protection: Are you sure to enable erase/program protection?--Yes. Disable erase/program protection: Are you sure to disable erase/program protection?--Yes. -
Page 17: Set System Memory As Main Memory Extension
System memory is used as a boot mode by default to store microcontroller manufacturer’ Startup Code. On top of this, in AT32F425 series, a new feature is added to the system memory by using it to store user-defined codes as an extended memory area (AP mode). -
Page 18: Figure 24. Use Icp Tool To Set Boot Memory Ap Mode
“File info”. Figure 25. Boot memory AP mode operating progress In mass production stage, users can use Artery ICP Programmer to enable system memory as memory extension area according to the following procedures: ... -
Page 19: Figure 26. Use Icp Tool To Set Offline Boot Mode Ap Mode
Getting Started with AT32F425 Go to menu bar: AT-Link setting -- AT-Link offline configuration setting; Follow the steps below to generate off-line project: Click “Create” Enter the project name Select a the desired MCU series and MCU part number Add .hex file Choose SWD as download interface Tick “Boot mode AP mode”... -
Page 20: Figure 27. Use Icp Tool To Set Offline Project Programming
For demos running user program in the system memory, please refer to the BSP, which is available from ARTERY official website → Product → Value line → AT32F425 series → BSP (download and unzip, and then go to “AT32F425_Firmware_Library_V2.x.x\utilities\at32f425_boot_memory_ap_demo”) 2022.10.21... -
Page 21: How To Distinguish At32 Mcu From Other Mcus
Getting Started with AT32F425 1.2.5 How to distinguish AT32 MCU from other MCUs Read Cortex-M series CPU ID number to determine whether it is based M0, M3 or M4 core. Figure 29. Read Cortex ID cortex_id = *(uint32_t *)0xE000ED00;// read Cortex ID if((cortex_id == 0x410FC240) || (cortex_id == 0x410FC241)) printf("This chip is Cortex-M4F.\r\n");... -
Page 22: Faqs About Download And Compiling
System clock is set out of specification. JLink unable to recognize IC in Keil project For a possible solution, please refer to the following documents: “FAQ0008_J-Link_cannot_ find_IC”, which is available from ARTERY official website →Support→FAQ→FAQ0008. “FAQ0132_How_to_add_Artery_MCU_into_JLINK”, which is available from ARTERY official ... -
Page 23: No Debug Unit Device Found
Getting Started with AT32F425 2.3.2 No Debug Unit Device found Download interface is being occupied. For example, ICP is being connected to a target device. JTAG/SWD connection error or it is not connected. 2.3.3 RDDI-DAP Error The compiler optimization level is too high. For example, Keil AC6 optimization level is the default “-Oz”, which should be changed to “-O0/-O1”. -
Page 24: Security Library (Slib)
IP-Codes (such as core algorithms) developed by software solution providers. In response to this demand, the AT32F425 series is designed with a security library (sLib) to protect important IP-Codes against being changed or read by the end user program. -
Page 25: Revision History
Getting Started with AT32F425 Revision history Table 1. Document revision history Date Version Revision note 2022.05.07 2.0.0 Initial release. 2022.07.11 2.0.1 Updated descriptions. Updated 3 party tools and added description of development environment and 2022.10.11 2.0.2 file paths. 2022.10.21 2.0.3 Updated description of UID and PID. - Page 26 Purchasers hereby agrees that Artery’s products are not authorized for use as, and purchasers shall not integrate, promote, sell or otherwise transfer any Artery’s product to any customer or end user for use as critical components in (a) any medical, life saving or life...
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