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ARTERY AT32F402 Series Reference Manual

Arm-based 32-bit cortex -m4f mcu+fpu, with 128 to 256 kb flash, slib, usbfs/hs-otg, 12 timers, 1 adc, 20 communication interfaces

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®

ARM

-based 32-bit Cortex

USBFS/HS-OTG, 12 timers, 1 ADC, 20 communication interfaces



®

Core: ARM

32-bit Cortex

− 216 MHz maximum frequency, with a Memory

Protection Unit (MPU), single-cycle multiplication

and hardware division

− Floating Point Unit (FPU)

− DSP instructions



Memories

− 128 to 256 Kbytes of Flash memory

− 20 Kbytes of boot memory used as a Bootloader or

as a general instruction/data memory (one-time

configured)

− sLib: configurable part of main Flash as a library

area with code executable but secured, non-

readable

− 70 to 102 Kbytes of SRAM



Power control (PWC)

− 2.4 V to 3.6 V power supply

− Power-on reset (POR)/low voltage reset (LVR), and

power voltage monitor (PVM)

− Low-power modes: Sleep, Deepsleep and Standby

modes

− 20 x 32-bit RTC data registers (BPR)



Clock and reset management (CRM)

− 4 to 25 MHz crystal (HEXT)

− 48 MHz internal factory-trimmed HICK (1% at

TA=25 ° C, 2% at TA=-40 ° C to +105 ° C), with

automatic clock calibration (ACC)

− PLL with configurable frequency multiplication and

division factors

− 32.768 kHz crystal (LEXT)

− Low speed internal clock (LICK)



Analog

− 1 x 12-bit 2 MSPS A/D converter, up to 16 input

channels, hardware over-sampling up to equivalent

16-bit resolution

− Temperature sensor (V

(V

)

INTR



DMA

− 2 x 7-channel DMA controllers



Up to 56 fast GPIOs

− All mappable on 16 external interrupts

− Almost 5 V-tolerant



Up to 14 timers (TMR)

− 1 x 16-bit 4-channel advanced timer, each channel

PWM output with dead-time generator and

emergency break

− Up to 1 x 32-bit and 7 x 16-bit general-purpose

timers, each with 4 IC/OC/PWM or pulse counter

and incremental encoder input; including 5 timers

supporting complementary output with dead-time

2023.08.31

AT32F402/405 Series Reference Manual

®

-M4F MCU+FPU, with 128 to 256 KB Flash, sLib,

®

-M4F CPU with FPU

), internal reference voltage

TS

generator and emergency brake

− 2 x 16-bit basic timers

− 2 x watchdog timers (WDT and WWDT)

− SysTick timer: 24-bit downcounter



ERTC: Enhanced RTC, with auto wakeup, alarm,

subsecond accuracy, hardware calendar, and

calibration feature



Up to 19 communication interfaces

− Up to 3 x I

2

C interfaces (SMBus/PMBus)

− Up to 8 x USARTs/UARTs (ISO7816 interface, LIN,

IrDA capability, modem control and RS485 drive

enable, TX/RX swap)

− 3 x SPIs, all with I

combination of two interfaces support full-duplex,

with 1 full-duplex I

− 1 x CAN interface (2.0B Active)

− USB2.0 FS/host/OTG device interface, supporting

crystal-less in device mode

− USB2.0 HS/host/OTG device interface

− 1 x QSPI

− Infrared transmitter (IRTMR)



CRC calculation unit



96-bit unique ID (UID)



Debug mode

− SWD interface



Operating temperature: -40 to +105 ° C



Packages

− LQFP64 10 x 10 mm

− LQFP64 7 x 7 mm

− LQFP48 7 x 7 mm

− QFN48 6 x 6 mm

− QFN32 4 x 4 mm



List of models

Internal Flash

Model

128 Kbytes

AT32F405RBT7 AT32F405RBT7-7

AT32F405CBT7 AT32F405CBU7

AT32F405KBU7-4

AT32F402RBT7 AT32F402RBT7-7

AT32F402CBT7 AT32F402CBU7

AT32F402KBU7-4

256 Kbytes

AT32F405RCT7 AT32F405RCT7-7

AT32F405CCT7 AT32F405CCU7

AT32F405KCU7-4

AT32F402RCT7 AT32F402RCT7-7

AT32F402CCT7 AT32F402CCU7

AT32F402KCU7-45RCT7-7

AT32F405RCT7

Page 1

2

S interface multiplexed, any

2

SF interface

Ver 2.00

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Summary of Contents for ARTERY AT32F402 Series

Page 1 AT32F402/405 Series Reference Manual ® ® -based 32-bit Cortex -M4F MCU+FPU, with 128 to 256 KB Flash, sLib, USBFS/HS-OTG, 12 timers, 1 ADC, 20 communication interfaces  ® ® Core: ARM 32-bit Cortex -M4F CPU with FPU generator and emergency brake −...
Page 2: Table Of Contents
AT32F402_405 Series Reference Manual Contents System architecture ..............33 System overview ................34 ® 1.1.1 ARM Cortex -M4F processor ............34 1.1.2 Bit band ..................34 1.1.3 Interrupt and exception vectors ............ 36 1.1.4 System Tick (SysTick) ..............40 1.1.5 Reset ..................40 List of abbreviations for registers ..........
Page 3 AT32F402_405 Series Reference Manual 4.1.1 Clock sources ................57 4.1.2 System clock ................58 4.1.3 Peripheral clock ................58 4.1.4 Clock fail detector ............... 58 4.1.5 Auto step-by-step system clock switch .......... 59 4.1.6 Internal clock output ..............59 4.1.7 Interrupts ..................59 Reset ..................
Page 4 AT32F402_405 Series Reference Manual 4.3.20 Battery powered domain control regist er (CRM_BPDC)....75 4.3.21 Control/status register (CRM_CTRLSTS) ........75 4.3.22 OTGHS control register (CRM_OTGHS) ........76 4.3.23 Additional register 1 (CRM_MISC1) ..........76 4.3.24 Additional register 2 (CRM_MISC2) ..........77 Flash memory controller (FLASH) ..........
Page 5 AT32F402_405 Series Reference Manual 5.8.7 User system data register (FLASH_USD) ........93 5.8.8 Erase/program protection status register (FLASH_EPPS) ....93 5.8.9 Flash security library status register 0 (SLIB_STS0) ...... 93 5.8.10 Flash security library status register 1 (SLIB_STS1) ...... 94 5.8.11 Security library password clear register (SLIB_PWD_CLR) ....
Page 6 AT32F402_405 Series Reference Manual 6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A..F) ....110 6.3.5 GPIO input data register (GPIOx_IDT) (x=A..F) ......110 6.3.6 GPIO output data register (GPIOx_ODT) (x=A..F) ......110 6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A..F) ......110 6.3.8 GPIO write protection register (GPIOx_WPR) (x=A..F) ....111 6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..F) ...
Page 7 AT32F402_405 Series Reference Manual Main features ................122 Function overview ..............123 9.3.1 DMA configuration ..............123 9.3.2 Handshake mechanism ............... 123 9.3.3 Arbiter ..................123 9.3.4 Programmable data transfer width ..........124 9.3.5 Errors ..................125 9.3.6 Interrupts ................... 125 DMA multiplexer (DMAMUX) ............
Page 8 AT32F402_405 Series Reference Manual 10.3.4 Initialization register (CRC_IDT) ..........141 10.3.5 Polynomial register (CRC_POLY) ..........141 C interface ................142 11.1 I C Introduction ................. 142 11.2 I C main features ............... 142 11.3 I C function overview ..............142 11.4 I C Interface ................
Page 9 AT32F402_405 Series Reference Manual 12.2 Full-duplex/half-duplex selector ..........173 12.3 Mode selector ................173 12.3.1 Introduction................173 12.3.2 Configuration procedure ............. 173 12.4 USART frame format and configuration ........176 12.5 DMA transfer introduction ............178 12.5.1 Transmission using DMA ............178 12.5.2 Reception using DMA ..............
Page 10 AT32F402_405 Series Reference Manual 13.2 Functional overview ..............193 13.2.1 SPI overview ................193 13.2.2 Full-duplex/half-duplex mode selector ......... 194 13.2.3 Chip select controller ..............196 13.2.4 SPI_SCK controller ..............196 13.2.5 CRC overview ................197 13.2.6 DMA transfer ................198 13.2.7 TI mode overview ...............
Page 11 AT32F402_405 Series Reference Manual Full-duplexed I2S (I2SF) .............. 217 14.1 I2SF introduction ............... 217 14.2 I2SF functional overview ............217 14.2.1 I2SF full duplex mode ..............217 14.2.2 I2SF master clock sources ............218 14.2.3 PCM mode ................. 219 14.2.4 Interrupts ................... 220 14.2.5 IO pin control ................
Page 12 AT32F402_405 Series Reference Manual 15.2.1 TMR2 to TMR4 introduction ............229 15.2.2 TMR2 to TMR4 main features ............229 15.2.3 TMR2 to TMR4 functional overview ..........229 15.2.3.1 Counting clock ..............229 15.2.3.2 Counting mode ..............233 15.2.3.3 TMR input function ..............236 15.2.3.4 TMR output function ..............
Page 13 AT32F402_405 Series Reference Manual 15.3.3.5 TMR break function ............... 269 15.3.3.6 TMR synchronization ............. 270 15.3.3.7 Debug mode ................. 271 15.3.4 TMR9 registers ................271 15.3.4.1 TMR9 control register1 (TMRx_CTRL1) ........272 15.3.4.2 TMR9 control register 2 (TMRx_CT RL2) ......... 273 15.3.4.3 TMR9 slave timer control register (TMRx_STCTRL) ....
Page 14 AT32F402_405 Series Reference Manual 15.4.4.6 TMRx channel mode register1 (TMRx_CM1) (x=10/11/13/14) ..296 15.4.4.7 TMRx Channel control register (TMRx_CCTRL) (x=10/11/13/14) 297 15.4.4.8 TMRx counter value (TMRx_CVAL) (x=10/11/13/14) ....300 15.4.4.9 TMRx division value (TMRx_DIV) (x=10/11/13/14) ....300 15.4.4.10 TMRx period register (TMRx_PR) (x=10/11/13/14) ....300 15.4.4.11 TMRx repetition period register (TMRx_RPR) (x=10/11/13/14) 300 15.4.4.12...
Page 15 AT32F402_405 Series Reference Manual 15.5.4.15 TMR1 channel 2 data register (TMR1_C2DT) ...... 331 15.5.4.16 TMR1 channel 3 data register (TMR1_C3DT) ...... 331 15.5.4.17 TMR1 channel 4 data register (TMRx_C4DT)....... 331 15.5.4.18 TMR1 break register (TMR1_BRK)........331 15.5.4.19 TMR1 DMA control register (TMR1_DMACTRL) ....332 15.5.4.20 TMR1 DMA data register (TMR1_DMADT) ......
Page 16 AT32F402_405 Series Reference Manual 18.3.1 ERTC clock ................342 18.3.2 ERTC initialization ..............342 18.3.3 Periodic automatic wakeup ............344 18.3.4 ERTC calibration ................ 344 18.3.5 Reference clock detection ............345 18.3.6 Time stamp function ..............345 18.3.7 Tamper detection ............... 346 18.3.8 Multiplexed function output ............
Page 17 AT32F402_405 Series Reference Manual 19.4.1 Channel management ..............359 19.4.1.1 Internal temperature sensor ........... 359 19.4.1.2 Internal reference voltage ............359 19.4.2 ADC operation process ............... 359 19.4.2.1 Power-on and calibration ............360 19.4.2.2 Trigger ................. 361 19.4.2.3 Sampling and conversion sequence ........361 19.4.3 Conversion sequence management ..........
Page 18 AT32F402_405 Series Reference Manual 19.5.15 ADC oversampling register (ADC_OVSP) ........377 19.5.16 ADC common control register (ADC_CCTRL) ......377 Controller area network (CAN) ............ 378 20.1 CAN introduction ............... 378 20.2 CAN main features ..............378 20.3 Baud rate .................. 378 20.4 Interrupt management ..............
Page 19 AT32F402_405 Series Reference Manual 20.7.2.7 Receive FIFO mailbox data low register (CAN_RFDTLx) (x=0..1) 402 20.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx) (x=0..1) 402 20.7.3 CAN filter registers ..............402 20.7.3.1 CAN filter control register (CAN_FCTRL) ........ 402 20.7.3.2 CAN filter mode configurati on register (CAN_FMCFG) ..... 402 20.7.3.3 CAN filter bit width configuration register (CAN_ FBW CFG) ..
Page 20 AT32F402_405 Series Reference Manual 21.5.4 OTGFS/HS device mode ............. 426 21.5.4.1 Device initialization ............... 426 21.5.4.2 Endpoint initialization on USB reset ........426 21.5.4.3 Endpoint initialization on enumeration completion ....427 21.5.4.4 Endpoint initialization on SetAddress command ....... 427 21.5.4.5 Endpoint initialization on SetConfiguration/SetInterface command 427 21.5.4.6 Endpoint activation ...............
Page 21 AT32F402_405 Series Reference Manual 21.6.3.11 OTGFS/HS non-periodic Tx FIFO size/request queue status register (OTGFS/HS_GNPTXSTS) ..............459 21.6.3.12 OTGFS/HS general controller configuration register (OTGFS_GCCFG) ................459 21.6.3.13 OTGFS/HS controller ID register (OTGFS/HS_GUID) ... 460 21.6.3.14 OTGFS/HS host periodic Tx FIFO size register (OTGFS/HS_HPTXFSIZ) ..............
Page 22 AT32F402_405 Series Reference Manual (OTGFS/HS_DOEPMSK) ..............472 21.6.5.6 OTGFS/HS device all endpoints interrupt mask register (OTGFS/HS_DAINT) ................473 21.6.5.7 OTGFS/HS all endpoints interrupt mask register (OTGFS/HS_DAINTMSK) ..............473 21.6.5.8 OTGFS/HS device IN endpoint FIFO empty interrupt mask register (OTGFS/HS_DIEPEMPMSK) ............... 474 21.6.5.9 OTGHS device all endpoints interrupt register (OTGHS_DEACHINT) .................
Page 23 AT32F402_405 Series Reference Manual 21.6.6 Power and clock control registers ..........487 21.6.6.1 OTGFS/HS power and clock gating control register (OTGFS/HS_PCGCCTL) ..............487 HICK auto clock calibration (ACC) ..........488 22.1 ACC introduction ............... 488 22.2 Main features ................488 22.3 Interrupt requests ..............
Page 24 AT32F402_405 Series Reference Manual 23.4.6 FIFO status register (FIFOSTS) ..........504 23.4.7 Control register 2 (CTRL2) ............505 23.4.8 Command status register (CMDSTS) ........... 505 23.4.9 Read status register (RSTS) ............505 23.4.10 Flash size register (FSIZE) (FSIZE) .......... 506 23.4.11 XIP command word 0 (XIP CMD_W 0) ........
Page 25 AT32F402_405 Series Reference Manual List of figures Figure 2-1 AT32F402/405 address mapping ....................43 Figure 3-1 Block diagram of each power supply ..................48 Figure 3-2 Power-on/Low voltage reset waveform ..................49 Figure 3-3 PVM threshold and output ......................49 Figure 4-1 AT32F405 clock tree ........................
Page 26 AT32F402_405 Series Reference Manual Figure 12-1 USART block diagram ......................171 Figure 12-2 BFF and FERR detection in LIN mode .................. 173 Figure 12-3 Smartcard frame format ......................174 Figure 12-4 IrDA DATA(3/16) – normal mode ................... 174 Figure 12-5 Hardware flow control ......................175 Figure 12-6 Mute mode using Idle line or Address mark detection ............
Page 27 AT32F402_405 Series Reference Manual Figure 15-1 Basic timer block diagram ...................... 225 Figure 15-2 Control circuit with CK_INT divided by 1 ................225 Figure 15-3 Basic structure of a counter ....................226 Figure 15-4 Overflow event when PRBEN=0 .................... 226 Figure 15-5 Overflow event when PRBEN=1 ....................
Page 28 AT32F402_405 Series Reference Manual Figure 15-46 Overflow event when PRBEN=1 ..................260 Figure 15-47 Counter timing diagram with internal clock divided by 4 ............. 260 Figure 15-48 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32....261 Figure 15-49 OVFIF in upcounting mode and central-aligned mode ............261 Figure 15-50 Encoder mode structure .......................
Page 29 AT32F402_405 Series Reference Manual Figure 15-91 Counting in external clock mode B, PR=0x32 and DIV=0x0 ..........306 Figure 15-92 Counter timing with prescaler value changing from 1 to 4 ..........306 Figure 15-93 Basic structure of a counter ....................307 Figure 15-94 Overflow event when PRBEN=0 ..................
Page 30 AT32F402_405 Series Reference Manual Figure 20-4 Receive interrupt 0 generation ....................381 Figure 20-5 Receive interrupt 1 generation ....................381 Figure 20-6 Status error interrupt generation .................... 381 Figure 20-7 CAN block diagram ........................ 382 Figure 20-8 32-bit identifier mask mode ....................384 Figure 20-9 32-bit identifier list mode ......................
Page 31 AT32F402_405 Series Reference Manual List of tables Table 1-1 Bit-band address mapping in SRAM ................... 35 Table 1-2 Bit-band address mapping in the peripheral area ............... 36 Table 1-3 AT32F402/405 series vector table ....................36 Table 1-4 List of abbreviations for registers ....................41 Table 1-5 Base address and reset value of registers ..................
Page 32 AT32F402_405 Series Reference Manual Table 12-6 USART register map and reset value ..................184 Table 13-1 Audio frequency precision using system clock ................ 209 Table 13-2 SPI register map and reset value .................... 212 Table 14-1 I2SF5 register map and reset value ..................221 Table 15-1 TMR functional comparison .....................
Page 33: System Architecture
AT32F402_405 Series Reference Manual System architecture AT32F402/405 series microcontrollers consists of 32-bit ARM ® Cortex ® -M4F processor, multiple 16-bit and 32-bit timers, infrared transmitter (IRTMR), DMA controller, ERTC, communication interfaces such as SPI, I C and USART/UART, CAN bus controller, USB2.0 OTG full-speed interface, HICK with automatic clock calibration (ACC), 12-bit ADC, programmable voltage monitor (PVM) and other peripherals.
Page 34: System Overview
AT32F402_405 Series Reference Manual 1.1 System overview ® 1.1.1 ARM Cortex -M4F processor Cortex ® -M4F processor is a low-power consumption processor featuring with low gate count, low interrupt latency and low-cost debug. It supports DSP instruction set and FPU, and it is applicable to ®...
Page 35: Table 1-1 Bit-Band Address Mapping In Sram
AT32F402_405 Series Reference Manual Figure 1-4 Comparison between bit-band region and its alias region: image B bitband alias region (total 32M bytes) 0x23FF_FFFC 0x23FF_FFF8 0x23FF_FFF4 0x23FF_FFF0 0x23FF_FFEC 0x23FF_FFE8 0x23FF_FFE4 0x23FF_FFE0 0x2200_001C 0x2200_0018 0x2200_0014 0x2200_0010 0x2200_000C 0x2200_0008 0x2200_0004 0x2200_0000 bitband region (total 1M bytes) 0x200F_FFFF 0x200F_FFFE...
Page 36: Interrupt And Exception Vectors
AT32F402_405 Series Reference Manual 0x2000_0004.2 0x2200_0088.0 … … 0x200F_FFFC.31 0x23FF_FFFC.0 Table 1-2 shows the mapping between bit-band region and alias region in the peripheral area. Table 1-2 Bit-band address mapping in the peripheral area Bit-band region Equivalent alias address 0x4000_0000.0 0x4200_0000.0 0x4000_0000.1 0x4200_0004.0...
Page 37 AT32F402_405 Series Reference Manual Configurable UsageFault Undefined instruction or illegal state 0x0000_0018 0x0000_001C Reserved ~0x0000_002B Configurable SVCall System service call via SWI instruction 0x0000_002C Configurable DebugMonitor Debug monitor 0x0000_0030 Reserved 0x0000_0034 Configurable PendSV Pendable request for system service 0x0000_0038 Configurable SysTick System tick timer 0x0000_003C Configurable WWDT...
Page 38 AT32F402_405 Series Reference Manual Configurable TMR1_CH TMR1 channel interrupt 0x0000_00AC Configurable TMR2 TMR2 global interrupt 0x0000_00B0 Configurable TMR3 TMR3 global interrupt 0x0000_00B4 Configurable TMR4 TMR4 global interrupt 0x0000_00B8 Configurable I2C1_EVT 0x0000_00BC C1 event interrupt Configurable I2C1_ERR 0x0000_00C0 C1 error interrupt Configurable I2C2_EVT 0x0000_00C4 C2 event interrupt...
Page 39 AT32F402_405 Series Reference Manual 0x0000_0138 0x0000_013C 0x0000_0140 0x0000_0144 0x0000_0148 Configurable OTGFS1 0x0000_014C OTGFS1 global interrupt Configurable DMA2 channel6 0x0000_0150 DMA2 channel6 global interrupt Configurable DMA2 channel7 0x0000_0154 DMA2 channel7 global interrupt 0x0000_0158 Configurable USART6 0x0000_015C USART6 global interrupt Configurable I2C3_EVT 0x0000_0160 I2C2 event interrupt Configurable I2C3_ERR...
Page 40: System Tick (Systick)
AT32F402_405 Series Reference Manual 0x0000_01C4 0x0000_01C8 0x0000_01CC 0x0000_01D0 0x0000_01D4 0x0000_01D8 Configurable ACC 0x0000_01DC ACC global interrupt 1.1.4 System Tick (SysTick) The System Tick is a 24-bit downcounter. It will be reloaded with the initial value automatically when it is decremented to zero. It can generate periodic interrupts, so it is often used as multi-task scheduling counter for embedded operating system, and also to call the periodic tasks for non-embedded system.
Page 41: List Of Abbreviations For Registers
AT32F402_405 Series Reference Manual Example of MSP and PC initialization Figure 1-6 Other Memory Initial SP Value 0x2000_8000 0x2000_8000 1st push data 0x2000_7FFC Stack grows 0x2000_7FF8 2nd push data downward Stack Memory 0x2000_7C00 Other Memory Code Boot Code 0x0000_0100 Other Exception Vectors 0x0000_0101 0x0000_0004...
Page 42: Device Characteristics Information
AT32F402_405 Series Reference Manual Software can read this bit and toggle it by writing 1. Writing 0 has no effect on this bit. Software can read this bit. Writing any value will trigger an event. resd Reserved 1.3 Device characteristics information Table 1-5 Base address and reset value of registers Register abbr.
Page 43: Memory Resources
AT32F402_405 Series Reference Manual Memory resources 2.1 Internal memory address map Internal memory contains program memory (Flash), data memory (SRAM), peripheral registers and core registers. Their respective address mapping are shown in Figure 2-1. Figure 2-1 AT32F402/405 address mapping 0xFFFF_FFFF Reserved 0xE010_0000 0xE00F_FFFF...
Page 44: Flash Memory
AT32F402_405 Series Reference Manual 2.2 Flash memory AT32F402/405 series provide up to 256 KB of on-chip Flash memory, supporting a single-cycle 32-bit read operation. Refer to Chapter for more details about Flash memory controller and register configuration. Flash memory organization (256 KB) The main memory contains bank 1 (256 Kbytes), including 128 sectors, 2 Kbytes per sector.
Page 45: Sram Memory
AT32F402_405 Series Reference Manual 2.3 SRAM memory The AT32F402/405 series contain a 102-KB on-chip SRAM that starts at the address of 0x2000_0000. It can be accessed by bytes, half-words (16-bit) or words (32-bit). 2.4 Peripheral address map Table 2-3 Peripheral boundary address Boundary address Peripherals 0xC000 0000 - 0xFFFF FFFF...
Page 46 AT32F402_405 Series Reference Manual 0x4001 6400 - 0x4001 67FF Reserved 0x4001 6000 - 0x4001 63FF 0x4001 5C00 - 0x4001 5FFF Reserved 0x4001 5800 - 0x4001 5BFF Reserved 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TMR11 timer...
Page 47 AT32F402_405 Series Reference Manual 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF SPI3/I2S3 0x4000 3800 - 0x4000 3BFF SPI2/I2S2 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF Watchdog timer (WDT) 0x4000 2C00 - 0x4000 2FFF Window watchdog timer (WWDT) 0x4000 2800 - 0x4000 2BFF...
Page 48: Power Control (Pwc)
AT32F402_405 Series Reference Manual Power control (PWC) 3.1 Introduction For AT32F402/405 series, the operating voltage supply is 2.4 V ~ 3.6 V, with an operating temperature range of -40~+105 °C. To reduce power consumption, this series provides three types of power saving modes, including Sleep, Deepsleep and Standby modes so as to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 49: Por/Lvr
AT32F402_405 Series Reference Manual 3.3 POR/LVR A POR analog module embedded in the VDD/VDDA domain is used to generate a power reset. The power reset signal is released at V when the VDD is increased from 0 V to the operating voltage, or it is triggered at V when the VDD drops from the operating voltage to 0 V.
Page 50: Power Domain
AT32F402_405 Series Reference Manual 3.5 Power domain 1.2 V domain The 1.2 V core domain includes a CPU core, SRAM, embedded digital peripherals and Phase Locked Loop (PLL). Such power domain is supplied by LDO (voltage regulator). VDD/VDDA domain VDD/VDDA domain includes VDD domain and VDDA domain. The VDD domain contains I/O circuit, power-saving mode wakeup circuit, watchdog timer (WDT), power-on reset/low voltage reset (POR/LVR), LDO, ERTC circuit, LEXT and all PAD circuits.
Page 51 AT32F402_405 Series Reference Manual  Enabling a peripheral interrupt (it is not enabled in the NVIC) and enabling the SEVONPEND bit. When the MCU resumes, the peripheral interrupt pending bit and NVIC channel pending bit must be cleared.  Configuring an internal EXINT line as an event mode to generate a wakeup event. ...
Page 52: Pwc Registers
AT32F402_405 Series Reference Manual In Standby mode, all I/O pins remain in a high-impedance state except reset pins, TAMPER pins that set as anti-tamper or calibration output, and the wakeup pins enabled. The MCU exits the Standby mode when a rising edge on the WKUP pin, a rising edge of an ERTC alarm event, an ERTC tamper event, ERTC timestamp, ERTC periodic automatic wakeup, an external reset (NRST pin) or a WDT reset occurs.
Page 53: Power Control/Status Register (Pwc_Ctrlsts)
AT32F402_405 Series Reference Manual This bit is cleared by hardware after clearing the SWEF flag. Reading this bit at any time will return all zero. Low-power mode select when Cortex ® -M4F is in Deepsleep mode Bit 1 LPSEL 0: Enter Deepsleep mode 1: Enter Standby mode LDO state select in Deepsleep mode Bit 0...
Page 54 AT32F402_405 Series Reference Manual − When the ERTC alarm event occurs; − If the Standby wakeup pin is enabled when the Standby wakeup pin level is high. 2023.08.31 Page 54 Rev 2.00...
Page 55: Ldo Output Voltage Select Register (Pwc_Ldoov)
AT32F402_405 Series Reference Manual 3.7.3 LDO output voltage select register (PWC_LDOOV) Abbr. Reset value Type Description Bit 31:5 Reserved 0x0000000 resd Kept at its default value. Voltage regulator extra low power mode enable This bit works together with the LPSEL and VRSEL bits in the PWC_CTRL register, and it is valid when VRSEL = 1 and the chip enters Deepsleep mode.
Page 56: Clock And Reset Manage (Crm)
AT32F402_405 Series Reference Manual Clock and reset manage (CRM) 4.1 Clock AT32F402/405 series provide different clock sources, including HEXT oscillator clock, HICK oscillator clock, PLL clock, LEXT oscillator clock and LICK oscillator clock. Figure 4-1 AT32F405 clock tree Peripheral HEXT_IN 12S1/2/3 CLK HEXT clock enable...
Page 57: Clock Sources
HICK clock is 48 MHz. Although it is less accurate, its startup time is shorter than the HEXT crystal oscillator. The HICK clock frequency of each device is calibrated by ARTERY to 1% accuracy (TA=25°C) in factory. The factory-trimmed value is loaded into the HICKCAL[7:0] bit of the clock control register.
Page 58: System Clock
AT32F402_405 Series Reference Manual the configuration parameters cannot be changed once the PLL is enabled. The PLL clock signal is not released until it becomes stable. PLL formula: PLL output clock = PLL input clock x PLL frequency multiplication factor / (PLL pre-divider factor x PLL post-divider factor) 500 MHz <= PLL input clock x PLL frequency multiplication factor / PLL pre-divider factor <= 1000 MHz 2 MHz <= PLL input clock / PLL pre-divider factor <= 16 MHz...
Page 59: Auto Step-By-Step System Clock Switch
AT32F402_405 Series Reference Manual directly linked to CPU NMI so that the software can perform rescue operations. The NMI interrupt keeps executing until the CFD interrupt pending bit is cleared. This is way the CFD interrupt has to be cleared in the NMI service routine.
Page 60: Battery Powered Domain Reset
AT32F402_405 Series Reference Manual 4.2.2 Battery powered domain reset Battery powered domain has two specific reset sources:  Software reset: triggered by setting the BPDRST bit in the battery powered domain control register (CRM_BPDC)  VDD power on, if it has been powered off Software reset affects only the battery powered domain.
Page 61 AT32F402_405 Series Reference Manual PLL clock stable This bit is set by hardware after PLL is ready. Bit 25 PLLSTBL 0: PLL is not ready 1: PLL is ready PLL enable This bit is set and cleared by software. It can also be cleared by hardware when entering Standby or Deepsleep Bit 24 PLLEN...
Page 62: Pll Clock Configuration Register (Crm_Pllcfg)
AT32F402_405 Series Reference Manual 4.3.2 PLL clock configuration register (CRM_PLLCFG) Access: 0 wait state, accessible by words, half-words and bytes Abbr. Reset value Type Description Bit 31 Reserved resd Kept at its reset value. PLL reference clock select The PLL reference clock source is selected by setting “1” or clearing this bit by software.
Page 63: Clock Configuration Register (Crm_Cfg)
AT32F402_405 Series Reference Manual PLL multiplication factor PLL_NS range (31~500) This bit cannot be set when PLLEN is enabled. 000000000 ~ 000011110: Forbidden 000011111: 31 Bit 14:6 PLL_NS 0x01F 000100000: 32 000100001: 33 …… 111110011: 499 111110100: 500 111110101~111111111: Forbidden Bit 5:4 Reserved resd...
Page 64: Clock Interrupt Register (Crm_Clkint)
AT32F402_405 Series Reference Manual 10: HICK 11: External input clock Bit 21 Reserved resd Kept at its default value. HEXT division for ERTC clock This field is set and cleared by software to divide the HEXT for ERTC clock. These bits must be configured before selecting the ERTC clock source.
Page 65: Ahb Peripheral Reset Register 1 (Crm_Ahbrst1)
AT32F402_405 Series Reference Manual HEXT stable flag clear Writing “1” by software to clear HEXTSTBLF. Bit 19 HEXTSTBLFC 0: No effect 1: Clear HICK stable flag clear Writing “1” by software to clear HICKSTBLF. Bit 18 HICKSTBLFC 0: No effect 1: Clear LEXT stable flag clear Writing “1”...
Page 66 AT32F402_405 Series Reference Manual 1: Reset OTGHS Bit 28:25 Reserved resd Kept at its default value. DMA2 reset Bit 24 DMA2RST 0: Does not reset DMA2 1: Reset DMA2 Bit 23 Reserved resd Kept at its default value. DMA1 reset Bit 22 DMA1RST 0: Does not reset DMA1...
Page 67: Ahb Peripheral Reset Register 2 (Crm_Ahbrst2)
AT32F402_405 Series Reference Manual 4.3.6 AHB peripheral reset register 2 (CRM_AHBRST2) Access: 0 wait state, accessible by words, half-words and bytes Abbr. Reset value Type Description Bit 31:8 Reserved 0x000000 resd Kept at its default value. OTGFS1 reset Bit 7 OTGFS1RST 0: Does not reset OTGFS1 1: Reset OTGFS1...
Page 68: Apb2 Peripheral Reset Register (Crm_Apb2Rst)
AT32F402_405 Series Reference Manual 1: Reset SPI2 Bit 13:12 Reserved resd Kept at its default value. Window watchdog reset Bit 11 WWDTRST 0: Does not reset window watchdog 1: Reset window watchdog Bit 10:9 Reserved resd Kept at its default value. Timer14 reset Bit 8 TMR14RST...
Page 69: Ahb Peripheral Clock Enable Register 1 (Crm_Ahben1)
AT32F402_405 Series Reference Manual 0: Does not reset USART6 1: Reset USART6 USART1 reset Bit 4 USART1RST 0: Does not reset USART1 1: Reset USART1 Bit 3:1 Reserved resd Kept at its default value. TMR1 reset Bit 0 TMR1RST 0: Does not reset TMR1 1: Reset TMR1 4.3.10 AHB peripheral clock enable register 1 (CRM_AHBEN1)
Page 70: Ahb Peripheral Clock Enable Register 3 (Crm_Ahben3)
AT32F402_405 Series Reference Manual 4.3.12 AHB peripheral clock enable register 3 (CRM_AHBEN3) Access: 0 wait state, accessible by words, half-words and bytes Abbr. Reset value Type Description Bit 31:2 Reserved 0x00000000 resd Kept at its default value. QSPI1 clock enable Bit 1 QSPI1EN 0: Disabled...
Page 71: Apb2 Peripheral Clock Enable Register (Crm_Apb2En)
AT32F402_405 Series Reference Manual Timer13 clock enable Bit 7 TMR13EN 0: Disabled 1: Enabled Bit 6 Reserved resd Kept at its default value. Timer 7 clock enable Bit 5 TMR7EN 0: Disabled 1: Enabled Timer 6 clock enable Bit 4 TMR6EN 0: Disabled 1: Enabled...
Page 72: Ahb Peripheral Clock Enable In Low-Power Mode Register 1 (Crm_Ahblpen1)
AT32F402_405 Series Reference Manual 4.3.15 AHB peripheral clock enable in low-power mode register 1 (CRM_AHBLPEN1) Access: 0 wait state, accessible by words, half-words and bytes Abbr. Reset value Type Description Bit 31:30 Reserved resd Kept at its default value. OTGHS clock enable in Sleep mode Bit 29 OTGHSLPEN 0: Disabled...
Page 73: Crm_Ahblpen3)
AT32F402_405 Series Reference Manual 4.3.17 AHB peripheral clock enable in low -power mode register 3 (CRM_AHBLPEN3) Access: 0 wait state, accessible by words, half-words and bytes Abbr. Reset value Type Description Bit 31:2 Reserved 0x00000000 resd Kept at its default value. QSPI1 clock enable in Sleep mode Bit 1 QSPI1LPEN...
Page 74: Apb2 Peripheral Clock Enable In Low-Power Mode Register
AT32F402_405 Series Reference Manual 1: Enabled Timer13 clock enable in Sleep mode Bit 7 TMR13LPEN 0: Disabled 1: Enabled Bit 6 Reserved resd Kept at its default value. Timer 7 clock enable in Sleep mode Bit 5 TMR7LPEN 0: Disabled 1: Enabled Timer 6 clock enable in Sleep mode Bit 4...
Page 75: Battery Powered Domain Control Register (Crm_Bpdc)
AT32F402_405 Series Reference Manual TMR1 timer clock enable in Sleep mode Bit 0 TMR1LPEN 0: Disabled 1: Enabled 4.3.20 Battery powered domain control register (CRM_BPDC) This register is reset only by the battery powered domain reset. Access: 0 to 3 wait states, accessible by words, half-words and bytes. Wait states are inserted in the case of consecutive accesses to this register.
Page 76: Otghs Control Register (Crm_Otghs)
AT32F402_405 Series Reference Manual WDT reset flag This bit is set by hardware and cleared by writing to the Bit 29 WDTRSTF RSTFC bit with software. 0: No WDT reset occurs 1: WDT reset occurs Software reset flag This bit is set by hardware and cleared by writing to the Bit 28 SWRSTF RSTFC bit with software.
Page 77: Additional Register 2 (Crm_Misc2)
AT32F402_405 Series Reference Manual 0101: USBHS 48M clock output 0110~1111: Reserved Bit 15 Reserved resd Kept at its default value. HICK as system clock frequency select When the HICK is selected as system clock by setting the Bit 14 HICK_TO_SCLK SCLKSEL bit, the frequency of SCLK is: 0: Fixed 8 MHz, that is, HICK/6 1: 48 MHz or 8 MHz, depending on the HICKDIV...
Page 78 AT32F402_405 Series Reference Manual Bit 3:0 Reserved resd It is fixed to 0xD. Do not change. 2023.08.31 Page 78 Rev 2.00...
Page 79: Flash Memory Controller (Flash)
AT32F402_405 Series Reference Manual Flash memory controller (FLASH) 5.1 FLASH introduction Flash memory is divided into three parts: main Flash memory, information block and Flash memory registers.  Main Flash memory is up to 256 KB.  Information block consists of 20 KB bootloader and the user system data area. The bootloader uses USART1, USART2, I2C, SPI, CAN or USB for ISP programming.
Page 80: Table 5-3 User System Data Area
AT32F402_405 Series Reference Manual Table 5-3 User system data area Address Description FAP[7:0]: Flash memory access protection (Access protection enable/disable result is stored in the FLASH_USD [1] and [26]) [7:0] 0xA5: Flash access protection disabled 0xCC: High-level Flash access protection enabled Others: Low-level Flash access protection enabled nFAP[7:0]: Inverse code of FAP[7:0] [15:8]...
Page 81: Flash Memory Operation
AT32F402_405 Series Reference Manual also used for the main Flash memory (256 KB/128 KB) extension area. 0: Erase/write protection is enabled 1: Erase/write protection is disabled [31:24] nEPP3[7:0]: Inverse code of EPP3[7:0] 0x1FFF_F810 [31:0] Reserved 0x1FFF_F830 QSPIKEY0[7:0]: Quad SPI (QSPI) ciphertext access area encryption key byte The situations for non-encryption includes: QSPIKEYx and nQSPIKEYx are 0xFF (default erase status) [7:0]...
Page 82: Figure 5-1 Flash Memory Sector Erase Process
AT32F402_405 Series Reference Manual  Check the OBF bit in the FLASH_STS register to confirm that there is no other programming operation in progress;  Write the sector to be erased in the FLASH_ADDR register;  Set the SECERS and ERSTR bits in the FLASH_CTRL register to enable sector erase; ...
Page 83: Programming Operation
AT32F402_405 Series Reference Manual  Check the OBF bit in the FLASH_STS register to confirm that there is no other programming operation in progress;  Set the BANKERS and ERSTR bits in the FLASH_CTRL register to enable mass erase;  Wait until the OBF bit in the FLASH_STS register becomes “0”.
Page 84: Figure 5-3 Flash Memory Programming Process
AT32F402_405 Series Reference Manual  Write the data (word/half-word/byte) to be programmed to the designated address;  Wait until the OBF bit in the FLASH_STS register becomes “0”. Read the EPPERR, PRGMERR and ODF bits in the FLASH_STS register to verify the programming result. Note: 1) When the address to be written is not erased in advance, the programming operation is not executed unless the data to be written is all 0.
Page 85: Read Operation
AT32F402_405 Series Reference Manual 5.2.4 Read operation Flash memory can be accessed through AHB bus of the CPU. 5.3 Main Flash memory extension area Boot memory can also be programmed as the extension area of the main Flash memory to store user- application code.
Page 86: Programming Operation
AT32F402_405 Series Reference Manual Figure 5‑4 System data area erase proc ess Start Check the OBF bit in FLASH_STS OBF = 0? Set USDERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ? Read ODF bit in FLASH_STS 5.4.3 Programming operation...
Page 87: Read Operation
AT32F402_405 Series Reference Manual Figure 5‑5 System data area programming process Start Check the OBF bit in FLASH_STS OBF = 0? Set the USDPRGM bit = 1 in FLASH_CTRL Write word/half-word (32bits/16 bits) data Check the OBF bit in FLASH_STS OBF = 0? Read PRGMERR bit and ODF bit in FLASH_STS...
Page 88: Erase/Program Protection
AT32F402_405 Series Reference Manual system reset. Subsequently, the system data loader will be reloaded with system data and updated with Flash memory access protection disable state (FAP byte). High-level access protection When the content in the nFAP is different from 0x33, and the content in the FAP byte is equal to 0xCC, the high-level Flash memory access protection is enabled after a system reset.
Page 89: Read Access
AT32F402_405 Series Reference Manual Read access To increase system clock frequency, program the number of wait states to access the Flash memory through the WTCYC bit in the FLASH_PSR register. The Flash read times can be decreased through the PFT_EN, PFT_EN2 and PFT_LAT_DIS bits in the FLASH_PSR register.
Page 90: Boot Memory Used As Flash Memory Extension
AT32F402_405 Series Reference Manual  Wait until the OBF bit becomes “0”;  Perform a system reset, and then reload security library setting word;  Read the SLIB_STS0 register to verify that if the security library is unlocked successfully. Note: Disabling the security library will automatically perform mass erase for the main Flash memory and its extension, as well as the security library setting block.
Page 91: Flash Performance Select Register (Flash_Psr)
AT32F402_405 Series Reference Manual SLIB_PWD_CLR 0x7C 0xFFFF FFFF SLIB_MISC_STS 0x80 0x0000 0000 FLASH_CRC_ADDR 0x84 0x0000 0000 FLASH_CRC_CTRL 0x88 0x0000 0000 FLASH_CRC_CHKR 0x8C 0x0000 0000 SLIB_SET_PWD 0x160 0x0000 0000 SLIB_SET_RANGE 0x164 0x0000 0000 EM_SLIB_SET 0x168 0x0000 0000 BTM_MODE_SET 0x16C 0x0000 0000 SLIB_UNLOCK 0x170 0x0000 0000...
Page 92: Flash User System Data Unlock Register (Flash_Usd_Unlock)
AT32F402_405 Series Reference Manual 5.8.3 Flash user system data unlock register (FLASH_USD_UNLOCK) Abbr. Reset value Type Description Bit 31:0 USD_UKVAL 0xXXXX XXXX wo User system data unlock key value Note: All these bits are write-only, and return 0 when being read. 5.8.4 Flash status register (FLASH_STS) Abbr.
Page 93: Flash Address Register (Flash_Addr)
AT32F402_405 Series Reference Manual 5.8.6 Flash address register (FLASH_ADDR) Abbr. Reset value Type Description Flash address Bit 31:0 0x0000 0000 Select the address of the sectors to be erased. 5.8.7 User system data register (FLASH_USD) Abbr. Reset value Type Description Bit 31:27 Reserved 0x00...
Page 94: Flash Security Library Status Register 1 (Slib_Sts1)
AT32F402_405 Series Reference Manual When this bit is set, it indicates that the boot memory is used as the Flash extension area (BTM_AP_ENF is set) and stores security library code. Bit 1 Reserved resd Kept at its default value. Boot memory store application code enabled flag When this bit is set, it indicates that the boot memory can Bit 0 BTM_AP_ENF...
Page 95: Security Library Additional Status Register (Slib_Misc_Sts)
AT32F402_405 Series Reference Manual 5.8.12 Security library additional status register (SLIB_MISC_STS) For Flash security library only. Abbr. Reset value Type Description Bit 31:3 Reserved 0x0000000 resd Kept at its default value. sLib unlock flag Bit 2 SLIB_ULKF When this bit is set, it indicates that sLib-related setting registers can be configured.
Page 96: Security Library Password Setting Register (Slib_Set_Pwd)
AT32F402_405 Series Reference Manual 5.8.16 Security library password setting register (SLIB_SET_PWD) For Flash security library password setting only. Abbr. Reset value Type Description sLib password setting value Note: This register can be written only after sLib is Bit 31:0 SLIB_PSET_VAL 0x0000 0000 unlocked.
Page 97: Flash Extension Memory Security Library Setting Register
AT32F402_405 Series Reference Manual 5.8.18 Flash extension memory security library setting register (EM_SLIB_SET) For Flash extension area only. Abbr. Reset value Type Description Bit 31:24 Reserved 0x00 resd Kept at its default value. Extension memory sLib instruction start sector setting These bits are used to set the security library instruction area start sector.
Page 98: Gpios And Iomux
AT32F402_405 Series Reference Manual GPIOs and IOMUX 6.1 Introduction AT32F402/405 series supports up to 56 bidirectional I/O pins, namely PA0-PA15, PB0-PB15, PC0-PC15, PD2, PF0-PF1, PF4-PF7, PF11. Each of these pins features communication, control and data collection. In addition, their main features also include: ...
Page 99: Gpio Reset Status
AT32F402_405 Series Reference Manual 6.2.2 GPIO reset status After power-on or system reset, all pins are configured as floating input mode. 6.2.3 General-purpose input configuration Mode IOMC PUPD Floating input Pull-down input Pull-up input When I/O port is configured as input: ...
Page 100: I/O Port Protection
AT32F402_405 Series Reference Manual  GPIO set/clear register is used to set/clear the corresponding GPIO output data registers. Note: If both IOCB and IOSB bits are set in the GPIO set/clear register, the IOSB takes priority. 6.2.6 I/O port protection Locking mechanism can freeze the I/O configuration for the purpose of protection.
Page 101: Iomux Input/Output
AT32F402_405 Series Reference Manual  Get an I/O pin state by reading input data register.  Floating input, pull-up/pull-down input are configurable.  Schmitt-trigger input is activated.  GPIO pin output is disabled. 6.2.9 IOMUX input/output The multiplexed function of each I/O port line is configured through the GPIOx_MUXL (from pin0 to pin7) or GPIOx_MUXH (from pin8 to pin15) register.
Page 102 AT32F402_405 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 name USART4_TX EVENTOUT USART4_RX QSPI1_IO3 EVENTOUT QSPI1_CS EVENTOUT EVENTOUT USART6_TX TMR14_CH1 OTGHS1_SOF EVENTOUT TMR13_CH1 USART6_RX EVENTOUT QSPI1_MOSI_I TMR13_CH1 QSPI1_IO2 EVENTOUT USART3_RX QSPI1_MISO_I TMR14_CH1 EVENTOUT USART2_TX UART7_TX OTGFS1_SOF EVENTOUT TMR14_BR I2C1_SCL OTGFS1_VBUS...
Page 103: Table 6-2 Port B Multiplexed Function Configuration With Gpiob_Mux* Register
AT32F402_405 Series Reference Manual Table 6-2 Port B multiplexed function configuration with GPIOB_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 name SPI1_MISO / SPI3_MOSI/I2S3_S TMR1_CH2C TMR3_CH3 USART2_RX I2S1_MCK SPI1_MOSI / TMR1_CH3C TMR3_CH4 SPI2_SCK/I2S2_CK USART2_CK I2S1_SD SPI3_MOSI/I2S3_S TMR2_CH4 TMR3_EXT I2C3_SMBA SPI1_SCK/I2 TMR2_CH2...
Page 104 AT32F402_405 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 name QSPI1_MOSI_I USART3_CK I2SF5_CK EVENTOUT USART3_RT TMR14_CH1 QSPI1_SCK I2SF5_WS EVENTOUT S_DE TMR14_CH1C QSPI1_SCK EVENTOUT USART1_RT UART7_RX USART5_TX QSPI1_IO3 EVENTOUT S_DE UART7_TX USART5_RX QSPI1_SCK I2S_SDEXT EVENTOUT USART5_CK_ QSPI1_MOSI_I USART5_RX EVENTOUT RTS_DE USART5_TX...
Page 105: Table 6-3 Port C Multiplexed Function Configuration With Gpioc_Mux* Register
AT32F402_405 Series Reference Manual Table 6-3 Port C multiplexed function configuration with GPIOC_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 name I2C3_SCL I2C1_SCL SPI3_MOSI/I2 SPI2_MOSI/I2S2_S I2C3_SDA I2C1_SDA S3_SD SPI2_MISO/I2 I2S_SDEXT S2_MCK SPI2_MOSI/I2 S2_SD TMR9_CH1 I2S1_MCK USART3_TX TMR9_CH2 I2C1_SMBA USART3_RX TMR1_CH1 TMR3_CH1...
Page 106 AT32F402_405 Series Reference Manual MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 name USART6_T UART7_TX EVENTOUT USART6_R UART7_RX EVENTOUT UART8_TX EVENTOUT UART8_RX EVENTOUT QSPI1_IO2 EVENTOUT TMR13_CH1 TMR13_CH1C QSPI1_IO3 EVENTOUT USART6_T UART7_TX EVENTOUT USART6_R UART7_RX EVENTOUT USART6_C QSPI1_IO2 EVENTOUT K_RTS_DE QSPI1_MOSI_IO I2C1_SDA OTGHS1_OE EVENTOUT...
Page 107: Table 6-4 Port D Multiplexed Function Configuration With Gpiod_Mux* Register
AT32F402_405 Series Reference Manual Table 6-4 Port D multiplexed function configuration with GPIOD_MUX* register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 name USART3_RT TMR3_EXT S_DE MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 name USART5_R EVENTOUT Table 6-5 Port F multiplexed function configuration with GPIOF_MUX* register MUX0 MUX1 MUX2...
Page 108: Peripheral Mux Function Configuration
AT32F402_405 Series Reference Manual 6.2.10 Peripheral MUX function configuration IOMUX function configuration is as follows:  To use a peripheral pin in MUX output, it is configured as multiplexed push-pull/open-drain output.  To use a peripheral pin in MUX input, it is configured as floating input/pull-up/pull-down input. ...
Page 109: Gpio Registers
AT32F402_405 Series Reference Manual 6.3 GPIO registers The table below lists GPIO register map and their reset values. These peripheral registers can be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits). Table 6-7 GPIO register map and reset values Register abbr.
Page 110: Gpio Drive Capability Register (Gpiox_Odrvr) (X=A..f
AT32F402_405 Series Reference Manual 6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..F) Address offset: 0x08 Reset value: 0x0000_00C0 for port B, and 0x0000_0000 for other ports. Abbr. Reset value Type Description GPIOx drive capability (y=0…15) This field is used to configure the I/O port drive capability Bit 2y+1:2y ODRVy 0x0000 0000 x0: Normal sourcing/sinking strength...
Page 111: Gpio Write Protection Register (Gpiox_Wpr) (X=A..f
AT32F402_405 Series Reference Manual If both IOCB and IOSB bits are set to 1, the IOSB takes the priority. 0: No action to the corresponding ODT bits 1: Set the corresponding ODT bits 6.3.8 GPIO write protection register (GPIOx_WPR) (x=A..F) Abbr.
Page 112: Gpio Multiplexed Function High Register (Gpiox_Muxh) (X=A
AT32F402_405 Series Reference Manual 6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..F) Abbr. Reset value Type Description Multiplexed function select for GPIOx pin y (y=8…15) This field is used to configure multiplexed function I/Os. 0000: MUX0 0001: MUX1 0010: MUX2 0011: MUX3 0100: MUX4 0101: MUX5...
Page 113: Gpio Port Bit Toggle Register (Gpiox_Togr) (X=A..f
AT32F402_405 Series Reference Manual 6.3.12 GPIO port bit toggle register (GPIOx_TOGR) (x=A..F) Abbr. Reset value Type Description Bit 31:16 Reserved 0x0000 resd Kept at its default value. GPIOx toggle bit The corresponding ODT register bit value is toggled by writing “1” to this bit, and remains unchanged when Bit 15:0 IOTB 0x0000...
Page 114: System Configuration Controller (Syscfg)
AT32F402_405 Series Reference Manual System configuration controller (SYSCFG) 7.1 Introduction This device contains a set of system configuration registers. The system configuration controller is mainly set to: Manage the external interrupts connected to GPIOs   Control the memory mapping mode ...
Page 115: Scfg External Interrupt Configuration Register 1 (Scfg_Exintc1)
AT32F402_405 Series Reference Manual 0: No SRAM odd parity error 1: SRAM odd parity error Bit 7:3 Reserved 0x0000 000 resd Kept at its default value. PVM lock enable 0: Disconnect the PVM interrupt with TIM1/TIM9 /TIM10/11/12/13/14 break input. The PVMSEL and PVMEN Bit 2 PVM_LK bits can be modified by software.
Page 116 AT32F402_405 Series Reference Manual 7.2.4 SCFG external interrupt configuration register 2 (SCFG_EXINTC2) Abbr. Reset value Type Description Bit 31:16 Reserved 0x0000 resd Kept at its default value. EXINT7 input source configuration These bits are used to select the input source for the EXINT7 external interrupt.
Page 117 AT32F402_405 Series Reference Manual These bits are used to select the input source for the EXINT8 external interrupt. 0000: GPIOA pin 8 0001: GPIOB pin 8 0010: GPIOC pin 8 Others: Reserved 7.2.6 SCFG external interrupt configuration register 4 (SCFG_EXINTC4) Abbr.
Page 118 AT32F402_405 Series Reference Manual 7.2.7 SCFG ultra high sourcing/sinking strength register (SCFG_UHDRV) Abbr. Reset value Type Description Bit 31:3 Reserved 0x0000 0000 resd Kept at its default value. PB10 Ultra high sourcing/sinking strength This bit is written by software to control PB10 PAD sourcing/sinking strength.
Page 119: External Interrupt/Event Controller (Exint)
AT32F402_405 Series Reference Manual External interrupt/event controller (EXINT) 8.1 EXINT introduction EXINT consists of 22 interrupt lines EXINT_LINE[22:0] (in which bit [19] is reserved), each of which can generate an interrupt or event by edge detection trigger or software trigger. EXINT can enable or disable an interrupt or event independently through software configuration, and utilizes different edge detection modes (rising edge, falling edge or both edges) as well as trigger modes (edge detection, software trigger or both triggers) to respond to trigger source in order to generate an interrupt or event.
Page 120: Exint Registers
AT32F402_405 Series Reference Manual Note: To modify the interrupt source configuration, disable the EXINT_INTEN and EXINT_EVTEN registers and then restart interrupt initialization. Interrupt clear procedure  Writing “1” to the EXINT_INTSTS register to clear the interrupts generated, and the corresponding bits in the EXINT_SWTRG register will be cleared at the same time.
Page 121: Software Trigger Register (Exint_Swtrg)
AT32F402_405 Series Reference Manual 8.3.5 Software trigger register (EXINT_SWTRG) Abbr. Reset value Type Description Bit 31:23 Reserved 0x000 resd Forced to 0 by hardware Software trigger on line x If the corresponding bit in the EXINT_INTEN register is 1, the software writes this bit, and the hardware sets the corresponding EXINT_INTSTS register...
Page 122: Dma Controller (Dma)
AT32F402_405 Series Reference Manual DMA controller (DMA) 9.1 Introduction Direct memory access (DMA) controller is designed for high-speed data transmission between peripherals and memory or between memories. The data can be transmitted through DMA at a high speed without CPU interference, which saves CPU capacity. There are two DMA controllers in the microcontroller.
Page 123: Function Overview
AT32F402_405 Series Reference Manual 9.3 Function overview 9.3.1 DMA configuration Set the peripheral address in the DMA_CPBAx register The initial peripheral address for data transfer remains unchanged during transmission. Set the memory address in the DMA_CMBAx register The initial memory address for data transfer remains unchanged during transmission. Configure the amount of the data to be transferred in the DMA_DTCNTx register Programmable data transfer size is up to 65535.
Page 124: Programmable Data Transfer Width
AT32F402_405 Series Reference Manual 9.3.4 Programmable data transfer width Transfer width of the source data and destination data is programmable through the PWIDTH and MWIDTH bits in the DMA_CHCTRLx register. When PWIDTH is not equal to MWIDTH, it can be aligned according to the settings of PWIDTH/ MWIDTH.
Page 125: Errors
AT32F402_405 Series Reference Manual 9.3.5 Errors Table 9-1 DMA error event Error event Description Transfer error AHB response error occurred during DMA read/write access 9.3.6 Interrupts An interrupt can be generated on a DMA half-transfer, transfer complete and transfer error. Each channel has its specific interrupt flag, clear and enable bits, as shown in the table below.
Page 126: Table 9-3 Flexible Dma1 / Dma2 Request Mapping
AT32F402_405 Series Reference Manual Table 9-3 Flexible DMA1 / DMA2 request mapping CHx_ CHx_ CHx_ CHx_ Request source Request source Request source Request source DMA_MUXREQG1 33 USART5_TX TMR3_OVERFLOW 97 reserved DMA_MUXREQG2 34 reserved TMR3_TRIG reserved DMA_MUXREQG3 35 reserved TMR4_CH1 reserved reserved DMA_MUXREQG4 36 TMR4_CH2...
Page 127: Dmamux Overflow Interrupts
AT32F402_405 Series Reference Manual Table 9-4 DMAMUX EXINT LINE for trigger input and synchronized input EXINT EXINT EXINT EXINT Source Source Source Source LINE LINE LINE LINE reserved exint_gpio[0] exint_gpio[8] DMA_MUXevt1 DMA_MUXevt2 reserved exint_gpio[1] exint_gpio[9] DMA_MUXevt3 reserved exint_gpio[2] exint_gpio[10] DMA_MUXevt4 reserved exint_gpio[3] exint_gpio[11]...
Page 128: Dma Registers
AT32F402_405 Series Reference Manual Figure 9-8 DMAMUX event generation Selected all_req[n] chx_mux_req SYNCEN EVTGEN mux_req_cnt mux_evtx SYNCEN = 0, EVTGEN = 1, REQCNT = 2 9.5 DMA registers The table below lists DMA register map and their reset values. These peripheral registers can be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 129 AT32F402_405 Series Reference Manual DMA_C6PADDR 0x74 0x0000 0000 DMA_C6MADDR 0x78 0x0000 0000 DMA_C7CTRL 0x80 0x0000 0000 DMA_C7DTCNT 0x84 0x0000 0000 DMA_C7PADDR 0x88 0x0000 0000 DMA_C7MADDR 0x8c 0x0000 0000 DMA_MUXSEL 0x100 0x0000 0000 DMA_MUXC1CTRL 0x104 0x0000 0000 DMA_MUXC2CTRL 0x108 0x0000 0000 DMA_MUXC3CTRL 0x10c 0x0000 0000...
Page 130: Dma Interrupt Status Register (Dma_Sts)
AT32F402_405 Series Reference Manual 9.5.1 DMA interrupt status register (DMA_STS) Access: 0 wait state, accessible by bytes, half-words or words. Abbr. Reset value Type Description Bit 31:28 Reserved resd Kept at its default value. Channel 7 data transfer error event flag Bit 27 DTERRF7 0: No transfer error occurred...
Page 131 AT32F402_405 Series Reference Manual Channel 4 half transfer event flag Bit 14 HDTF4 0: No half-transfer event occurred 1: Half-transfer event occurred Channel 4 transfer complete event flag Bit 13 FDTF4 0:No transfer complete event occurred 1:Transfer complete event occurred Channel 4 global event flag Bit 12 0: No transfer error, half-transfer or transfer complete...
Page 132: Dma Interrupt Flag Clear Register (Dma_Clr)
AT32F402_405 Series Reference Manual Channel 1 global event flag Bit 0 0: No transfer error, half-transfer or transfer complete 1: Transfer error, half-transfer or transfer complete 9.5.2 DMA interrupt flag clear register (DMA_CLR) Access: 0 wait state, accessible by bytes, half-words or words. Abbr.
Page 133 AT32F402_405 Series Reference Manual Channel 4 data transfer error flag clear Bit 15 DTERRFC4 rw1c 0: No effect 1: Clear the DTERRF4 flag in the DMA_STS register Channel 4 half transfer flag clear Bit 14 HDTFC4 rw1c 0: No effect 1: Clear the HDTF4 flag in the DMA_STS register Channel 4 transfer complete flag clear Bit 13...
Page 134: Dma Channel-X Configuration Register (Dma_Cxctrl) (X=1
AT32F402_405 Series Reference Manual Channel 1 transfer complete flag clear Bit 1 FDTFC1 rw1c 0: No effect 1: Clear the FDTF1 flag in the DMA_STS register Channel 1 global flag clear 0: No effect Bit 0 GFC1 rw1c 1: Clear DTERRF1, HDTF1, FDTF1 and GF1 flags in the DMA_ISTS register 9.5.3 DMA channel-x configuration register (DMA_CxCTRL) (x=1…7)
Page 135: Dma Channel-X Number Of Data Register (Dma_Cxdtcnt) (X=1
AT32F402_405 Series Reference Manual 9.5.4 DMA channel-x number of data register (DMA_CxDTCNT) (x=1…7) Access: 0 wait state, accessible by bytes, half-words or words. Abbr. Reset value Type Description Bit 31:16 Reserved 0x0000 resd Kept at its default value. Number of data to transfer The number of data to transfer is from 0x0 to 0xFFFF.
Page 136: Dmamux Channel-X Control Register (Dma_Muxcxctrl
AT32F402_405 Series Reference Manual 9.5.8 DMAMUX channel-x control register (DMA_MUXCxCTRL) (x=1…7) Access: 0 wait state, accessible by bytes, half-words or words. Abbr. Reset value Type Description Bit 31:25 Reserved 0x00 resd Kept at its default value. Bit 28:24 SYNCSEL 0x00 Synchronization select DMA request count These bits indicate the number of DMA requests sent to...
Page 137: Dmamux Channel Synchronization Status Register
AT32F402_405 Series Reference Manual 9.5.9 DMAMUX generator-x control register (DMA_MUXGxCTRL) (x=1…4) Access: 0 wait state, accessible by bytes, half-words or words. Abbr. Reset value Type Description Bit 31:24 Reserved 0x00 resd Kept at its default value. DMA request generation count It is used to define the number of DMA request (GNBREQ Bit 23:19 GREQCNT...
Page 138: Dmamux Generator Interrupt Status Register (Dma_Muxgsts)
AT32F402_405 Series Reference Manual 9.5.12 DMAMUX generator interrupt status register (DMA_MUXGSTS) Access: 0 wait state, accessible by bytes, half-words or words. Abbr. Reset value Type Description Bit 31:4 Reserved 0x0000 000 resd Kept at its default value. Trigger overrun interrupt flag Bit 3:0 TRGOVF 0x00...
Page 139: Crc Calculation Unit (Crc)
AT32F402_405 Series Reference Manual 10 CRC calculation unit (CRC) 10.1 CRC introduction The Cyclic Redundancy Check (CRC) is an independent peripheral with CRC check feature. It follows CRC-32/MPEG-2 standard. The CRC_CTRL register is used to select output data toggle (word, REVOD=1) or input data toggle (byte, REVID=01;...
Page 140: Crc Registers
AT32F402_405 Series Reference Manual  Toggle output: determine whether to perform toggle (word) according to the REVOD value in the CRC_CTRL register before output.  Perform XOR calculation for the result, and the XOR-ed value is fixed to 0x0000 0000. CRC-32/MPEG-2 parameters ...
Page 141: Control Register (Crc_Ctrl)
AT32F402_405 Series Reference Manual 10.3.3 Control register (CRC_CTRL) Abbr. Reset value Type Description Bit 31:8 Reserved 0x000000 resd Kept at its default value. Reverse output data It is set and cleared by software. This bit is used to control Bit 7 REVOD resd whether or not to reverse output data.
Page 142: C Interface
AT32F402_405 Series Reference Manual 11 I C interface 11.1 I C Introduction C (inter-integrated circuit) bus interface manages the communication between the microcontroller and serial I C bus. It supports master and slave modes, with up to 1 Mbit/s of communication speed (enhanced edition).
Page 143: I 2 C Interface
AT32F402_405 Series Reference Manual 11.4 I C Interface The figure below shows the block diagram of I C interface. Figure 11-2 I C interface block diagram I2CCLK Clock Control TIMEOUT_Frozen I2C_SCL_out Master clock generation CPU_Halt_en GPIO I2C_SCL Slave clock Digital I2C_SCL_in stretching noise filter...
Page 144 AT32F402_405 Series Reference Manual ― 2: Address bit [7:3] ― 3: Address bit [7:4] ― 4: Address bit [7:5] ― 5: Address bit [7:6] ― 6: Address bit [7] ― 7: All addresses, excluding those reserved by I Support special slave address: ...
Page 145: C Timing Control
AT32F402_405 Series Reference Manual When the OUF bit is set, if the ERRIE=1 in the I2C_CTRL1 register, an interrupt will occur. 11.4.1 C timing control C core is clocked by I2C_CLK, whereas the I2C_CLK is clocked by PCLK1. The PCLK1 should be set to be less than 4/3 SCL cycles.
Page 146: Data Transfer Management
AT32F402_405 Series Reference Manual counter value reaches the SCLH value, the SCL line is pulled low. In the process of SCL remaining high, if it is pulled low by external bus, the internal SCLH counter will stop counting and start counting in SCL low mode, laying the foundation for clock synchronization.
Page 147: I 2 C Master Communication Flow
AT32F402_405 Series Reference Manual  Stop data transfer by software (ASTOPEN=0 in the I2C_CTRL2 register) ― When the number of data programmed in the CNT[7:0] has been fully transferred, the TDC=1 in the I2C_STS register, the SCL will be pulled low at this point, and an interrupt is generated if the TDCIEN is generated.
Page 148 AT32F402_405 Series Reference Manual ― ASTOPEN=0: stop data transfer by software. After the completion of data transfer, the TDC is set in the I2C_STS register, and GENSTOP=1 or GENSTART=1 is written by software to send a STOP or START condition. ―...
Page 149: Figure 11-4 I 2 C Master Transmission Flow
AT32F402_405 Series Reference Manual Master transmitter Figure 11-4 I C master transmission flow Master initialization Set I2C_CTRL2_CNT = N , ( if N > 255 , CNT = 0xFF, N=N- 255 ,RLDEN = 1) ,Configure slave address, and GENSTART = 1. I2C_STS_ACKFAIL=1? I2C_STS_TDIS=1? Write I2C_TXDT_DT...
Page 150: Figure 11-5 Transfer Sequence Of I
AT32F402_405 Series Reference Manual Figure 11-5 Transfer sequence of I C master transmitter Example : I2C master transmitter N bytes . Initial setting flow : 1. I2C_CTRL2_CNT = N 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL2_GENSTART = 1 Initial setting Address Data2...
Page 151: Figure 11-7 Transfer Sequence Of I
AT32F402_405 Series Reference Manual Figure 11-7 Transfer sequence of I C master receiver Example : I2C master receiver N bytes . Initial setting flow : 1. I2C_CTRL2_CNT = N 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_ASTOPEN = 1 4. I2C_CTRL2_GENSTART = 1 Initial setting Address Data1...
Page 152: I 2 C Slave Communication Flow
AT32F402_405 Series Reference Manual 11.4.4 C slave communication flow Set local address 1 ― Set address mode: 7-bit address: by setting ADDR1MODE=0 in the I2C_OADDR1 register 10-bit address: by setting ADDR1MODE=1 in the I2C_OADDR1 register ― Set address 1: by setting the ADDR1 bit in the I2C_OADDR1 register ―...
Page 153: Figure 11-10 I 2 C Slave Transmission Flow
AT32F402_405 Series Reference Manual After the reception of data, RDBF=1; read the RXDT register will clear the RDBF automatically; Repeat step 2 until the completion of all data transfer; Wait for the generation of a STOP condition. Once received, the STOPF bit in the I2C_STS register is set.
Page 154: Figure 11-11 I 2 C Slave Transmission Timing
AT32F402_405 Series Reference Manual Figure 11-11 I C slave transmission timing Example : I2C Slave transfer N bytes to I2C Master , I2C_CTRL2_STRETCH = 0 . Address Data1 Data2 DataN NA P Stretch TDIS EV1. I2C_STS1_ADDRF = 1, set I2C_CLR_ADDRC = 1. Master to Slave S = Start EV2.
Page 155: Smbus
AT32F402_405 Series Reference Manual Figure 11-13 I C slave receive timing Example : I2C Slave receiver Nbytes from I2C master . Address Data1 Data2 DataN Stretch RDBF EV1. I2C_STS_ADDRF = 1, set I2C_CLR_ADDRC S = Start Master to Slave EV2. I2C_STS_RDBF = 1 , read Data1 A = Acknowledge P = Stop EV3.
Page 156: Table 11-3 Smbus Timeout Specification
AT32F402_405 Series Reference Manual The host then processes the interrupt and accesses to all devices through ARA (Alert Response Address 0001100x) so as to get the slave addresses. Only the devices with pulled-down SMBALERT can acknowledge ARA. The host then continues to operate based on the slave addresses available. SMBus slave When an alert event occurs and the ALERT pin changes from high to low (SMBALERT=1), the slave responses to ARA (Alert Response Address, 0001100x);...
Page 157: Smbus Master Communication Flow
AT32F402_405 Series Reference Manual Table 11-4 SMBus timeout detection configuration Type of timeout Other configuration Enable bit Timeout calculation TOMODE=0 TOEN=1 (TOTIME + 1) x 2048 x TI2C_CLK TIMEOUT EXTEN=1 (EXTTIME + 1) x 2048 x TI2C_CLK LOW:SEXT EXTEN=1 (EXTTIME + 1) x 2048 x TI2C_CLK LOW:MEXT Slave receive byte control In slave receive mode, the slave receive byte control mode (SCTRL=1) can be used to control...
Page 158: Figure 11-14 Smbus Master Transmission Timing
AT32F402_405 Series Reference Manual a STOP or START condition ― ASTOPEN=1: data transfer is stopped automatically. A STOP condition is sent at the end of data transfer Set slave address ― Set slave address value (by setting the SADDR bit in the I2C_CTRL2 register) ―...
Page 159: Smbus Slave Communication Flow
AT32F402_405 Series Reference Manual Figure 11-15 SMBus master receive timing Example : SMBus master receiver N bytes +PEC . Initial setting flow : 1. I2C_CTRL2_CNT = N+ 1 2. I2C_CTRL2_SADDR = slave address 3. I2C_CTRL2_PECTEN = 1 4. I2C_CTRL2_GENSTART = 1 Initial setting Address Data1...
Page 160 AT32F402_405 Series Reference Manual Repeat step 3 and 4 until data (N-1) is sent; The slave will automatically transmit the Nth data, that is, PEC Wait for the generation of a NACK signal. Once received, the ACKFAILF is set in the I2C_STS register.
Page 161: Figure 11-16 Smbus Slave Transmission Flow
AT32F402_405 Series Reference Manual SMBus slave transmitter Figure 11-16 SMBus slave transmission flow Slave initialization I2C_STS_ADDRF=1? Set I2C_CTRL2_CNT =N+ 1 I2C_CTRL2_PECTEN = 1 I2C_CLR_ADDRC =1 I2C_STS_TDIS=1? Write I2C_TXDT_DT Figure 11-17 SMBus slave transmission timing Example : SMBus slave transmitter N bytes + PEC Address Data1 Data2...
Page 162: Figure 11-18 Smbus Slave Receive Flow
AT32F402_405 Series Reference Manual SMBus slave receive Figure 11-18 SMBus slave receive flow Slave initialization Read I2C_RXDT_DT Set I2C_CTRL2_RLDEN =0, NACKIEN = 0 and CNT = 1 I2C_STS_ADDRF=1? Set I2C_CTRL2, CNT = 1, RLDEN=1 , PECTEN = 1 I2C_STS_RDBF = 1? Set I2C_CLR_ADDRC =1 Read I2C_RXDT_DT I2C_STS_RDBF=1?
Page 163: Data Transfer Using Dma
AT32F402_405 Series Reference Manual Figure 11-19 SMBus slave receive timing Example : SMBus slave receiver N bytes +PEC Address Data1 Data2 DataN Stretch RDBF EV1. I2C_STS_ADDR =1, Set I2C_CTRL2 CNT = N+1 ,PECTEN = 1,and set S = Start Master to Slave I2C_CLR_ADDRC =1 A = Acknowledge P = Stop...
Page 164: Error Management
AT32F402_405 Series Reference Manual 11.4.9 Error management The error management feature included in the I C provides a guarantee for the reliability of communication. The manageable error events are listed below: Table 11-6 I C error events Error event Event flag Enable control bit Clear bit SMBus Alert...
Page 165: C Interrupt Requests
AT32F402_405 Series Reference Manual SMBus defines a timeout mechanism for the improvement of the system stability, preventing the bus from being pulled down in the case of a master or slave failure. Once a timeout event (defined in SMBus chapter) is detected, the TMOUT is set by hardware in the I2C_STS register. If a timeout error occurs in slave mode, the SCL and SDA buses are immediately released;...
Page 166: Control Register 1 (I2C_Ctrl1)
AT32F402_405 Series Reference Manual I2C_RXDT 0x24 0x00000000 I2C_TXDT 0x28 0x00000000 11.7.1 Control register 1 (I2C_CTRL1) Abbr. Reset value Type Description Bit 31:24 Reserved 0x00 Kept at its default value. PEC calculation enable Bit 23 PECEN 0: Disabled 1: Enabled SMBus alert enable / pin set To enable SMBus master alert feature: 0: SMBus alert disabled Bit 22...
Page 167: Control Register 2 (I2C_Ctrl2)
AT32F402_405 Series Reference Manual 11.7.2 Control register 2 (I2C_CTRL2) Abbr. Reset value Type Description Bit 31:27 Reserved 0x00 Kept at its default value. Request PEC transmission enable Bit 26 PECTEN 0: Transmission disabled 1: Transmission enabled Automatically send stop condition enable Bit 25 ASTOPEN 0: Disabled (Software sends STOP condition)
Page 168: Timing Register (I2C_Clkctrl)
AT32F402_405 Series Reference Manual 7-bit address mode Bit 0 Reserved Kept at its default value. 11.7.5 Timing register (I2C_CLKCTRL) Abbr. Reset value Type Description Bit 31:28 DIVL[3:0] Low 4 bits of clock divider value High 4 bits of clock divider value Bit 27:24 DIVH[7:4] DIV = (DIVH <<...
Page 169 AT32F402_405 Series Reference Manual SMBus timeout flag Bit 12 TMOUT 0: No timeout 1: Timeout PEC receive error flag Bit 11 PECERR 0: No PEC error 1: PEC error Overflow or underflow flag In transmission mode: 0: No overflow or underflow Bit 10 1: Underrun In reception mode:...
Page 170: Status Clear Flag (I2C_Clr)
AT32F402_405 Series Reference Manual 11.7.8 Status clear flag (I2C_CLR) Abbr. Reset value Type Description Bit 31:14 Reserved 0x00000 Kept at its default value. Clear SMBus alert flag Bit 13 ALERTC SMBus alert flag is cleared by writing 1. Clear SMBus timeout flag Bit 12 TMOUTC SMBus timeout flag is cleared by writing 1.
Page 171: Universal Synchronous/Asynchronous Receiver/Transmitter (Usart)
AT32F402_405 Series Reference Manual 12 Universal synchronous/asynchronous receiver/transmitter (USART) 12.1 USART introduction The universal synchronous/asynchronous receiver/transmitter (USART) serves an interface for communication by means of various configurations and peripherals with different data formats. It supports asynchronous full-duplex and half-duplex as well as synchronous transfer. With a programmable baud rate generator, USART offers up to 13.5 Mbits/s of baud rate by setting the system frequency and frequency divider, which is also convenient for users to configure the required communication frequency.
Page 172 AT32F402_405 Series Reference Manual  Programmable communication modes ─ NRZ standard format (Mark/Space) ─ LIN (Local Interconnection Network) ─ IrDA SIR (SIR Serial Infrared) ─ Asynchronous SmartCard protocol defined in ISO7816-3 standard: support 0.5 or 1.5 stop bits in Smartcard mode ─...
Page 173: Full-Duplex/Half-Duplex Selector
AT32F402_405 Series Reference Manual 12.2 Full-duplex/half-duplex selector The full-duplex and half-duplex selector enables USART to perform data exchanges with peripherals in full-duplex or half-duplex mode, which is achieved by setting the corresponding registers. In two-wire unidirectional full-duplex mode (by default), TX pin is used for data output, while the RX pin is used for data input.
Page 174: Figure 12-3 Smartcard Frame Format
AT32F402_405 Series Reference Manual 2. Smartcard mode Set SCMEN=1, LINEN=0, SLHDEN=0, IRDAEN=0, CLKEN=1, DBN[1:0]=01, PEN=1 and STOPBN[1:0]=11. The polarity, phase and pulse number of the clock can be configured by setting the CLKPOL, CLKPHA and LBCP bits (Refer to Synchronous mode for details). The assertion of the TDC flag can be delayed by setting the SCGT[7:0] bit (guard time bit).
Page 175: Figure 12-5 Hardware Flow Control
AT32F402_405 Series Reference Manual 5. Hardware flow control mode Setting RTSEN=1 and CTSEN=1 will enable RTS and CTS flow control, respectively. RTS flow control: When the USART receiver is ready to receive new data, the RTS becomes effective (pull down low). When the data is received in the receiver (at the beginning of each stop bit), the RTS bit is set, indicating that the data transmission is to be stopped at the end of the current frame.
Page 176: Usart Frame Format And Configuration
AT32F402_405 Series Reference Manual Figure 12-6 Mute mode using Idle line or Address mark d etection Idle line detection(WUM = 0)： frame2 3 4 frame0 frame1 frame5 RX pin Idle RDBF Normal mode Mute mode Address mark detection(WUM = 1)： frame1 2 3 4 frame0 ADDR=1...
Page 177: Figure 12-8 Word Length Configuration
AT32F402_405 Series Reference Manual Figure 12-8 W ord length configuration 9-bit word length (DBN1, DBN0 = 01)： Clock PEN = 1, Next Data frame Next Data frame Parity bit Start Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Stop Start Idle frame...
Page 178: Dma Transfer Introduction
AT32F402_405 Series Reference Manual Figure 12-9 Stop bit configuration Clock PEN = 1, Next STOPBN = 00 Data frame Parity bit Start Start 1 Stop bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 1 Stop bit PEN = 1,...
Page 179: Reception Using Dma
AT32F402_405 Series Reference Manual 12.5.2 Reception using DMA 1. Select a DMA transfer channel: Select a DMA channel from DMA channel map table described in DMA chapter. 2. Configure the destination of DMA transfer: Configure the memory address as the destination of DMA transfer in the DMA control register.
Page 180: Transmitter
AT32F402_405 Series Reference Manual 12.7 Transmitter 12.7.1 Introduction USART transmitter has its individual TEN control bit. The transmitter and receiver share the same baud rate that is programmable. There is a transmit data buffer (TDR) and a transmit shift register in the USART.
Page 181: Receiver
AT32F402_405 Series Reference Manual 12.8 Receiver 12.8.1 Introduction USART receiver has its individual REN control bit (bit [2] in the USART_CTRL1 register). The transmitter and receiver share the same baud rate that is programmable. There is a receive data buffer (RDR) and a receive shift register in the USART.
Page 182: Start Bit And Noise Detection
AT32F402_405 Series Reference Manual  The ROERR bit is set.  The data in the receive data buffer is not lost. The previous data is still available when the USART_DT register is read.  The content in the receive shift register is overwritten. Afterwards, any data received will be lost. ...
Page 183: Tx/Rx Swap
AT32F402_405 Series Reference Manual Table 12-4 Maximum allowable deviation DBN[1:0] DIV[3:0] = 0 DIV[3:0] != 0 3.75% 3.33% 3.41% 3.03% 4.16% 3.7% When noise is detected in a data frame:  The NERR bit is set at the same time as the RDBF bit. ...
Page 184: Interrupts
AT32F402_405 Series Reference Manual 12.10 Interrupts USART interrupt generator serves as a control center of USART interrupts. It is used to monitor the interrupt source inside the USART in real time and the generation of interrupts according to the programmed interrupt control bits. The table below shows the USART interrupt source and interrupt enable control bit.
Page 185: Status Register (Usart_Sts)
AT32F402_405 Series Reference Manual USART_CTRL1 0x0C 0x0000 USART_CTRL2 0x10 0x0000 USART_CTRL3 0x14 0x0000 USART_GDIV 0x18 0x0000 USART_RTOV 0x1C 0x0000 USART_IFC 0x20 0x0000 12.12.1 Status register (USART_STS) Abbr. Reset value Type Description Bit 31:18 Bit 16:12 Reserved 0x000000 resd Forced to 0 by hardware Bit 10 Bit 17 CMDF...
Page 186: Data Register (Usart_Dt)
AT32F402_405 Series Reference Manual 1: Data is received Idle flag This bit is set by hardware when an idle line is detected. It is cleared by software (read access to the USART_STS Bit 4 IDLEF register and then read access to the USART_DT register). 0: No idle line is detected 1: Idle line is detected Receiver overflow error...
Page 187: Control Register 1 (Usart_Ctrl1)
AT32F402_405 Series Reference Manual 12.12.4 Control register 1 (USART_CTRL1) Abbr. Reset value Type Description Bit 31:29 Reserved 0x00000 resd Forced to 0 by hardware Data bit number This bit, along with the DBN0 bit, is used to program the number of data bits. 10: 7 data bits Bit 28 DBN1...
Page 188 AT32F402_405 Series Reference Manual 0: Disabled 1: Enabled Parity selection This bit selects the odd or even parity after the parity control is enabled. Bit 9 PSEL 0: Even parity 1: Odd parity PERR interrupt enable Bit 8 PERRIEN 0: Disabled 1: Enabled TDBE interrupt enable Bit 7...
Page 189: Control Register 2 (Usart_Ctrl2)
AT32F402_405 Series Reference Manual 12.12.5 Control register 2 (USART_CTRL2) Abbr. Reset value Type Description USART identification Bit 31:28 This field holds the upper four bits of USART ID. It is configurable. Bit 27:20 Reserved 0x000 resd Kept at its default value. MSB transmit first This bit is used to select MSB transmit first or LSB transmit first.
Page 190: Control Register 3 (Usart_Ctrl3)
AT32F402_405 Series Reference Manual synchronous mode. 0: The clock pulse of the last data bit is not output on the clock pin 1: The clock pulse of the last data bit is output on the clock Bit 7 Reserved resd Kept at its default value.
Page 191 AT32F402_405 Series Reference Manual DMA receiver enable Bit 6 DMAREN 0: Disabled 1: Enabled Smartcard mode enable Bit 5 SCMEN 0: Disabled 1: Enabled Smartcard NACK enable This bit is used to send NACK when parity error occurs. Bit 4 SCNACKEN 0: NACK is disabled when parity error occurs 1: NACK is enabled when parity error occurs...
Page 192: Guard Time And Divider Register (Gdiv)
AT32F402_405 Series Reference Manual 12.12.7 Guard time and divider register (GDIV) Abbr. Reset value Type Description Bit 31:16 Reserved 0x0000 resd Forced to 0 by hardware Smartcard guard time This field specifies the guard time value. The transmission Bit 15:8 SCGT 0x00 complete flag is set after this guard time in Smartcard...
Page 193: Serial Peripheral Interface (Spi)
AT32F402_405 Series Reference Manual 13 Serial peripheral interface (SPI) 13.1 SPI introduction The SPI interface supports either the SPI protocol or the I S protocol, depending on software configuration. This chapter gives a full description of the main features and configuration procedures of SPI used as SPI or I 13.2 Functional overview 13.2.1 SPI overview...
Page 194: Full-Duplex/Half-Duplex Mode Selector
AT32F402_405 Series Reference Manual  Programmable communication frequency and division factors (can be up to f PCLK Programmable clock polarity and phase Programmable data transfer order (MSB-first or LSB-first)  Programmable error interrupt flags (CS pulse error, receiver overflow error, master mode error and CRC error) Programmable transmit data buffer empty interrupt and receive data buffer full interrupt ...
Page 195: Figure 13-3 Single-Wire Unidirectional Receive Only In Spi Master Mode
AT32F402_405 Series Reference Manual Figure 13-3 Single-wire unidirectional receive only in SPI master mode SPI master SPI slave MISO MISO MOSI MOSI Figure 13-4 Single-wire unidirectional receive only in SPI slave mode SPI master SPI slave MISO MISO MOSI MOSI In this scenario, for SPI in master mode, it is required to wait until the second to last RDBF bit is set and then one SPI_CPK clock before disabling the SPI.
Page 196: Chip Select Controller
AT32F402_405 Series Reference Manual In both master and slave mode, when the SPI is selected for data transmission in single-wire bidirectional half-duplex mode, the TDBE bit must be set, and the BF must be 0 before disabling the SPI. The power- saving mode (or disabling SPI system clock) cannot be entered unless the SPI is disabled.
Page 197: Crc Overview
AT32F402_405 Series Reference Manual Note that the clock output is activated after the SPI is enabled in master reception-only mode, and it remains present until when the SPI is disabled and the reception is complete. 13.2.5 CRC overview The SPI interface provides separate CRC calculation unit for transmission and reception. When used as SPI through software configuration, the automatic CRC calculation and check is performed while the user is reading or writing data through either DMA or CPU.
Page 198: Dma Transfer
AT32F402_405 Series Reference Manual 13.2.6 DMA transfer The SPI interface supports the use of DMA for data write and read. Refer to the following configuration procedures for details in this regard. Special attention should be paid to here: When the CRC calculation and check is enabled, the number of data transferred by DMA is configured to be the number of the to-be-sent data, while the number of data read with DMA is configured as the number of the data to receive.
Page 199: Transmitter
AT32F402_405 Series Reference Manual After the TI mode is enabled, when in slave mode, the SPI interface is capable of detecting CS pulse errors during data transmission, and setting the CSPAS bit (It is cleared by reading the SPI_STS) as soon as a CS pulse error is detected.
Page 200: Motorola Mode
AT32F402_405 Series Reference Manual if the ERRIE is set. Reading SPI_DT register and then the SPI_STS register can clear the ROERR bit. The recommended configuration procedures are as follows. Receiver configuration procedures: Configure full-duplex/half-duplex selector   Configure chip select controller Configure SPI_SCK controller ...
Page 201: Figure 13-7 Slave Full-Duplex Communications
AT32F402_405 Series Reference Manual Figure 13-7 Slave full-duplex communications Sampling Drive MISO MOSI TDBE flag Transmit buffer empty and RDBF flag software can write data BF flag Software needs to read the received data Half-duplex communication – master transmit timing Configured as follows: MSTEN=1: Master enable SLBEN=1: Single line bidirectional mode...
Page 202: Ti Mode Communication Timings
AT32F402_405 Series Reference Manual CLKPOL=0, CLKPHA=0: SCK idle output low, use the first edge for sampling FBN=0: 8-bit data frame Slave sends data: 0xaa, 0xcc, 0xaa Figure 13-10 Slave half-duplex transmit Drive MISO Transmit buffer empty and TDBE flag software can write data BF flag Half-duplex communication –...
Page 203: Interrupts
AT32F402_405 Series Reference Manual Figure 13-13 TI mode continous transfer with dummy CLK Write the to-be-transmitted data MISO MOSI dummy In TI mode, when the to-be-sent data is written after the falling SCK edge corresponding to the last data of the current transmit frame, the host always issues a valid SCK clock after 1T SCK + 4T PCLK cycles.
Page 204: I 2 S Functional Description
AT32F402_405 Series Reference Manual 13.3 I S functional description 13.3.1 I S introduction The I S is capable of operating in master receive, master transmit, and slave receive and slave transmit, depending on software configuration. These four operating modes support four audio protocols including Philips standard, MSB-aligned standard, LSB-aligned standard and PCM standard, respectively.
Page 205: S Full-Duplex Mode
AT32F402_405 Series Reference Manual 13.3.2 I S full-duplex mode Two SPIs can be combined to support I S full-duplex mode through the SCFG_CFG2[31:30] bit in the SCFG register. Of the three SPIs, either SPI1 or SPI2 can be configured as full-duplex master, while the SPI2 or SPI3 can be set as full-duplex slave, which is selected through the SCFG_CFG2[31:30] bit in the SCFG register.
Page 206: Figure 13-18 I 2 S Slave Device Transmission
AT32F402_405 Series Reference Manual Figure 13-18 slave device transmission I2S master I2S slave Slave device reception: Set the I2SMSEL bit, and OPERSEL[1:0]=01, the I S will work in slave device reception mode. Figure 13-19 slave device reception I2S master I2S slave Master device transmission: Set the I2SMSEL bit, and OPERSEL[1:0]=10, the I S will work in master device transmission mode.
Page 207: Audio Protocol Selector
AT32F402_405 Series Reference Manual Figure 13-21 I S master device reception I2S master I2S slave 13.3.4 Audio protocol selector As I S interface, the SPI supports multiple audio protocols. The user can select the desired audio protocol, the number of data bits and of channel bits through the audio protocol selector by software. By controlling the WS controller automatically, the audio protocol selector outputs or detects WS signals that conform to the protocol requirements.
Page 208: I2S_Clk Controller
AT32F402_405 Series Reference Manual The data bits are the same as the channel bits. Each channel requires two read/write operations from/to the SPI_DT register, and the number of DMA transfer is 2. These 32-bit data are proceeded (transmit and reception) in two times, with 16-bit data each time. ...
Page 209: Dma Transfer
AT32F402_405 Series Reference Manual Table 13-1 Audio frequency precision using system clock 16bit 32bit Target SCLK (MHz) I2S_ODD RealFs Error I2S_ODD RealFs Error (Hz) 192000 187500 2.34% 187500 2.34% 96000 97826.09 1.90% 93750 2.34% 48000 34615.38 27.88% 48913.04 1.90% 44100 44117.65 0.04% 43269.23...
Page 210: Transmitter/Receiver
AT32F402_405 Series Reference Manual  Configure DMA interrupt generation after half or full transfer in the DMA control register Enable DMA transfer channel in the DMA control register.  13.3.7 Transmitter/Receiver Whether used as SPI or I2S, there is no difference for CPU. The SPI (in whatever mode) shares the same base address, the same SPI_DT register, the same transmitter and receiver.
Page 211: I2S Communication Timings
AT32F402_405 Series Reference Manual 13.3.8 I2S communication timings S can address four different audio standards: Philips standard, the MSB-aligned (left-aligned) and the LSB-aligned (right-aligned) standards, and t PCM standard. Figure 13-23 shows their respective timings. Figure 13-23 Audio standard timings 16CK Left Right...
Page 212: Spi Registers
AT32F402_405 Series Reference Manual 13.4 SPI registers These peripheral registers must be accessed by or words (32 bits). Table 13-2 SPI register map and reset value Register Offset Reset value SPI_CTRL1 0x00 0x0000 SPI_CTRL2 0x04 0x0000 SPI_STS 0x08 0x0002 SPI_DT 0x0C 0x0000 SPI_CPOLY...
Page 213: Spi Control Register2 (Spi_Ctrl2)
AT32F402_405 Series Reference Manual 1: High level LSB transmit first This bit is used to select for MST transfer first or LSB Bit 7 transfer first. 0: MSB 1: LSB SPI enable Bit 6 SPIEN 0: Disabled 1: Enabled Master clock frequency division In master mode, the peripheral clock divided by the prescaler is used as SPI clock.
Page 214: Spi Status Register (Spi_Sts)
AT32F402_405 Series Reference Manual 1: TI mode enabled (TI mode) Note: This mode is not used in I2S mode. It must be 0 in I2S mode. Bit 3 Reserved resd Kept at default value Hardware CS output enable This bit is valid only in master mode. When this bit is set, the I/O output on the CS pin is low;...
Page 215: Spi Data Register (Spi_Dt)
AT32F402_405 Series Reference Manual 0: Transmit data buffer is not empty. 1: Transmit data buffer is not empty. Receive data buffer full Bit 0 RDBF 0: Transmit data buffer is not full. 1: Transmit data buffer is full. 13.4.4 SPI data register (SPI_DT) Abbr.
Page 216: Spi_I2S Prescaler Register (Spi_I2Sclkp)
AT32F402_405 Series Reference Manual 00: Slave transmission 01: Slave reception 10: Master transmission 11: Master reception PCM frame synchronization This bit is valid only when the PCM standard is used. Bit 7 PCMFSSEL 0: Short frame synchronization 1: Long frame synchronization Bit 6 Reserved resd...
Page 217: Full-Duplexed I2S (I2Sf)
AT32F402_405 Series Reference Manual 14 Full-duplexed I2S (I2SF) 14.1 I2SF introduction I2SF audio interface is an extended version of I2S which supports full duplex mode. Its master clock sources can be from system clock, PLL input clock, HICK output clock or external input clock. A more accurate audio frequency can be achieved by configuring the master clock of I2SF.
Page 218: I2Sf Master Clock Sources
AT32F402_405 Series Reference Manual Figure 14-3 I2SF full-duplex host receive/slave transmit I2SF5 host I2SF5 slave (host receive) (slave transmit) OPERSEL=2'b00 OPERSEL=2'b11 SDEXT SDEXT Figure 14-4 I2SF full-duplex host receive/slave receive I2SF5 host I2SF5 slave (host receive) (slave receive OPERSEL=2'b01 OPE RS EL=2'b11 SDEXT SDEXT Full-duplex transfer in master mode (I2SFDUPEN=1 and OPERSEL[9]=1)
Page 219: Pcm Mode
AT32F402_405 Series Reference Manual Figure 14-5 I2SF master clock sources I2S5CLKSEL(CRM_CFG[23:22]) I2S5EN(CRM_APB2EN[20]) System Clock I2S5_CLK HICK External input clock 14.2.3 PCM mode The I2SF has an additional I2SFPCMCKSEL register used to select rising edge or falling edge of the clock for sampling data in PCM long-frame or PCM short-frame format.
Page 220: Interrupts
AT32F402_405 Series Reference Manual 14.2.4 Interrupts Figure 14-8 I2SF interrupts RDBF RDBFIE TDBE TDBEIE interrupt ERRIE ROERR TUERR CSPAS 14.2.5 IO pin control When full-duplex feature is enabled, the I2SF needs three pins to implement I S communication. They are SD (data pin), WS (synchronization pin) and CK (communication clock pin). If there is a need to provide main clock for peripherals, a MCLK is required.
Page 221: I2Sf Registers
AT32F402_405 Series Reference Manual 14.3 I2SF registers These peripheral registers must be accessed by or words (32 bits). Table 14-1 register map and reset value I2SF5 Register Offset Reset value I2SF_CTRL2 0x04 0x0000 I2SF_STS 0x08 0x0002 I2SF_DT 0x0C 0x0000 I2SF_I2SCTRL 0x1C 0x0000 I2SF_I2SCLKP...
Page 222: I2Sf Data Register (I2Sf_Dt)
AT32F402_405 Series Reference Manual Transmitter underload error Set by hardware, and cleared by software (read the SPI_STS register). Bit 3 TUERR 0: No underload error 1: Underload error occurs. Note: This bit is only used in I S mode. Audio channel state This bit indicates the status of the current audio channel.
Page 223: I2Sf Prescaler Register (I2Sf_I2Sclkp)
AT32F402_405 Series Reference Manual 01: 24-bit data length 10: 32-bit data length 11: Not allowed. S channel bit num This bit can be configured only when the I S is set to 16- Bit 0 I2SCBN bit data; otherwise, it is fixed to 32-bit by hardware. 0: 16-bit wide 1: 32-bit wide 14.3.5 I2SF prescaler register (I2SF_I2SCLKP)
Page 224: Timer
AT32F402_405 Series Reference Manual 15 Timer AT32F402/405 timers include basic timers, general-purpose timers, and advanced timers. Please refer to Section 15.1 Section 15.5 for detailed function modes. All functions of different timers are shown in the following tables. Table 15-1 TMR functional comparison Counter Count Capture/compare...
Page 225: Basic Timer (Tmr6 And Tmr7)
AT32F402_405 Series Reference Manual 15.1 Basic timer (TMR6 and TMR7) 15.1.1 TMR6 and TMR7 introduction Basic timers (TMR6 and TMR7) include a 16-bit up counter with corresponding control logic, without being connected to external I/Os. They can be used for basic timing function. 15.1.2 TMR6 and TMR7 main features ...
Page 226: Figure 15-3 Basic Structure Of A Counter
AT32F402_405 Series Reference Manual mode timer controller in reset mode. Once the OVFS is set, an overflow event is generated only when overflow or underflow occurs. Setting the TMREN bit (TMREN=1) enables the timer to start counting. Base on synchronization logic, however, the actual counter enable signal TMR_EN is set 1 clock cycle after the TMREN is set.
Page 227: Debug Mode
AT32F402_405 Series Reference Manual 15.1.3.3 Debug mode ® When the microcontroller enters debug mode (Cortex -M4F core halted), the TMRx counter stops counting when the TMRx_PAUSE bit is set to 1 in the DEBUG module. 15.1.4 TMR6 and TMR7 registers These peripheral registers have to be accessed by words (32 bits).
Page 228: Tmr6 And Tmr7 Control Register2 (Tmrx_Ctrl2)
AT32F402_405 Series Reference Manual 15.1.4.2 TMR6 and TMR7 control register2 (TMRx_CTRL2) Abbr. Reset value Type Description Bit 15: 7 Reserved 0x000 resd Kept at default value. Master TMR output selection This field is used to select the signals in master mode to be sent to slave timers.
Page 229: Tmr6 And Tmr7 Period Register (Tmrx_Pr)
AT32F402_405 Series Reference Manual 15.1.4.8 TMR6 and TMR7 period register (TMRx_PR) Abbr. Reset value Type Description Period value Bit 15: 0 0x0000 This indicates the period value of the TMRx counter. The timer stops working when the period value is 0. 15.2 General-purpose timer (TMR2 to TMR4) 15.2.1 TMR2 to TMR4 introduction The general-purpose timers (TMR2 to TMR4) consist of a 16-bit counter supporting up, down, up/down...
Page 230: Figure 15-8 Counting Clock
AT32F402_405 Series Reference Manual Figure 15-8 Counting clock Encoder mode (SMSEL=3'b001/010/011) CK_INT(form CRM) CI1FP1/CI2FP2 STIS[1:0] External clock mode A (SMSEL=3'b111) STIS[2] Internal trigger CK_CNT DIV_counter CNT_counter STIS[1:0] TRGIN C1INC C1IFP1 polarity edge External trigger External clock mode B detector C2IPF2 (ECMBEN=1) TMRx_EXT ESDIV...
Page 231: Figure 15-10 Block Diagram Of External Clock Mode A
AT32F402_405 Series Reference Manual (C2DF[3:0] in TMRx_CM1 register) and channel 2 input polarity (C2P/C2CP in TMRx_CCTR register); If the TMRx_EXT is used as a source of TRGIN, it is necessary to configure the external signal polarity (ESP in TMRx_STCTRL register), external signal frequency division (ESDIV[1:0] in TMRx_STCTRL) and external signal filter (ESF[3:0] in TMRx_STCTRL register).
Page 232: Figure 15-13 Counting In External Clock Mode B, Pr=0X32 And Div=0X0
AT32F402_405 Series Reference Manual Figure 15-13 Counting in external clock mode B, PR=0x32 and DIV=0x0 TMR_CLK CK_CNT COUNTER ESDIV[1:0] ESF[3:0] 0000 OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal from another timer.
Page 233: Counting Mode
AT32F402_405 Series Reference Manual 15.2.3.2 Counting mode The timers (TMR2 to TMR4) support several counting modes to meet different application scenarios. They have an internal 16-bit up, down, up/down counter. TMR2/5 can be extended to 32 bits by setting the PMEN bit to 1. The TMRx_PR register is used to set counting period of the counter.
Page 234: Figure 15-17 Overflow Event When Prben=1
AT32F402_405 Series Reference Manual Figure 15-17 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode This mode is enabled by setting CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1 register. In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed, and generates a counter underflow event.
Page 235: Figure 15-20 Encoder Mode Structure
AT32F402_405 Series Reference Manual Encoder interface mode In this mode, the two input (TMRx_CH1 and TMRx_CH2) signals are required. Depending on the level on one input signal, the counter counts up or down on the edge of the other input signal. The OWCDIR bit indicates the direction of the counter, as shown in the table below: Figure 15-20 Encoder mode structure SMSEL=3'b001/010/011...
Page 236: Tmr Input Function
AT32F402_405 Series Reference Manual Table 15-4 Counting direction versus encoder signals C1IFP1 signal C2IFP2 signal Level on opposite signal Active edge (C1IFP1 to C2IFP2, C2IFP2 to C1IFP1) Rising Falling Rising Falling High Down No count No count Count on C1IFP1 only Down No count No count...
Page 237: Figure 15-22 Input/Output Channel 1 Main Circuit
AT32F402_405 Series Reference Manual Figure 15-22 Input/output channel 1 main circuit C1INSEL TMRx_CH3 edge detector input divider STCI TMRx_CH2 C1IRAW C1DF C1P/C1CP C1IFP1 C1IDIV C1EN C1IN TMRx_CH1 C2IFP1 filter Capture trigger C1DT_shadow Compare CNT counter Capture C1DT C1DT preload C1OCTRL C1OBEN Overflow event C1ORAW...
Page 238: Tmr Output Function
AT32F402_405 Series Reference Manual  Set C2P=1’b1, select C1IFP2 falling edge active  Set STIS=3’b101, select the slave mode timer trigger signal as C1IFP1  Set SMSEL=3‘b100: configure the slave mode controller in reset mode  Set C1EN=1’b1 and C2EN=1’b1. Enable channel 1 and input capture After above configuration, the rising edge of channel 1 input signal will trigger the capture and stores the capture value into C1DT register, and it will reset the counter at the same time.
Page 239 AT32F402_405 Series Reference Manual Output mode Write CxC[2: 0]≠2’b00 to configure the channel as output to support multiple output modes. In this case, the counter value is compared with the value in the TMRx_CxDT register, and the intermediate signal CxORAW is generated according to the output mode selected by CxOCTRL[2: 0], which is sent to IO after being processed by the output control circuit.
Page 240: Figure 15-27 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F402_405 Series Reference Manual B. The counter only counts only one cycle, and the output signal sends only one pulse. Figure 15-27 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW Figure 15-28 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0]...
Page 241: Figure 15-29 Up/Down Counting Mode And Pwm Mode A
AT32F402_405 Series Reference Manual Figure 15-29 Up/down counting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW ≥32 C1DT[15：0] C1ORAW Figure 15-30 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master mode timer event output When TMR is used as a master timer, one of the following source of signals can be selected as TRGOUT output to a slave mode timer.
Page 242: Tmr Synchronization
AT32F402_405 Series Reference Manual Figure 15-31 Clearing CxORAW(PWM mode B) by EXT input COUNTER CxDT CxOSEN CxORAW 15.2.3.5 TMR synchronization The timers are linked together internally for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit; Slave timer is selected by setting the SMSEL[2: 0] bit. Slave modes include: Slave mode: Reset mode The counter and its prescaler can be reset by a selected trigger signal.
Page 243: Figure 15-34 Example Of Trigger Mode
AT32F402_405 Series Reference Manual Slave mode: Trigger mode The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1) Figure 15-34 Example of trigger mode TMR_CLK CI1F1 TMR_EN COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] OVFIF Master/slave timer interconnection Both Master and slave timer can be configured in different master and slave mode scenarios respectively.
Page 244: Debug Mode
AT32F402_405 Series Reference Manual Figure 15-36 Using master timer to start slave timer TMR_CLK COUNTER PR[15:0] Master DIV[15:0] Overflow event TMR_CLK TMREN Slave COUNTER DIV[15:0] PR[15:0] Starting master and slave timers synchronously by an external trigger: In this example, configure the master timer as master and slave mode synchronously and enable its slave timer synchronization function.
Page 245: Control Register 1 (Tmrx_Ctrl1)
AT32F402_405 Series Reference Manual Table 15-5 TMR2 to TMR4 register map and reset value Register Offset Reset value TMRx_CTRL1 0x00 0x0000 TMRx_CTRL2 0x04 0x0000 TMRx_STCTRL 0x08 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CM1 0x18 0x0000 TMRx_CM2 0x1C 0x0000 TMRx_CCTRL...
Page 246: Control Register 2 (Tmrx_Ctrl2)
AT32F402_405 Series Reference Manual is counting down 10: Two-way counting mode 2. The counter counts up and down alternately, the CxIF bit is set only when the counter is counting up 11: Two-way counting mode 3. The counter counts up and down alternately, the CxIF bit is set when the counter counting up or down One-way count direction...
Page 247: Dma/Interrupt Enable Register (Tmrx_Iden)
AT32F402_405 Series Reference Manual 00: Normal 01: Divided by 2 10: Divided by 4 11: Divided by 8 External signal filter This field is used to filter an external signal. The external signal can be sampled only after it has been generated N times 0000: No filter, sampling by f ��...
Page 248: Interrupt Status Register (Tmrx_Ists)
AT32F402_405 Series Reference Manual Kept at default value Bit 13 Reserved resd Channel 4 DMA request enable Bit 12 C4DEN 0: Disabled 1: Enabled Channel 3 DMA request enable Bit 11 C3DEN 0: Disabled 1: Enabled Channel 2 DMA request enable Bit 10 C2DEN 0: Disabled...
Page 249: Software Event Register (Tmrx_Swevt)
AT32F402_405 Series Reference Manual Please refer to C1IF description. Channel 3 interrupt flag Bit 3 C3IF rw0c Please refer to C1IF description. Channel 2 interrupt flag Bit 2 C2IF rw0c Please refer to C1IF description. Channel 1 interrupt flag If the channel 1 is configured as input mode: This bit is set by hardware on a capture event.
Page 250 AT32F402_405 Series Reference Manual 01: Input, C2IN is mapped on C2IFP2 10: Input, C2IN is mapped on C1IFP2 11: Input, C2IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS register. Channel 1 output switch enable 0: C1ORAW is not affected by EXT Bit 7 C1OSEN...
Page 251: Channel Mode Register2 (Tmrx_Cm2)
AT32F402_405 Series Reference Manual This field is used to define the direction of the channel 2 (input or output), and the selection of input pin when C2EN=’0’: 00: Output 01: Input, C2IN is mapped on C2IFP2 10: Input, C2IN is mapped on C1IFP2 11: Input, C2IN is mapped on STCI.
Page 252: Channel Control Register (Tmrx_Cctrl)
AT32F402_405 Series Reference Manual Bit 6: 4 C3OCTRL Channel 3 output control Bit 3 C3OBEN Channel 3 output buffer enable Bit 2 C3OIEN Channel 3 output enable immediately Channel 3 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: Bit 1: 0...
Page 253: Counter Value (Tmrx_Cval)
AT32F402_405 Series Reference Manual This bit defines the valid edge of input signals. Refer to C1P bit for details. Kept at default value. Bit 2 Reserved resd Channel 1 polarity When the channel 1 is configured as output mode: 0: C1OUT is active high 1: C1OUT is active low When the channel 1 is configured as input mode: C1CP/C1P are used to define the valid edge of input...
Page 254: Channel 2 Data Register (Tmrx_C2Dt)
AT32F402_405 Series Reference Manual The C1DT is the CVAL value stored by the last channel 1 input event (C1IN) When the channel 1 is configured as output mode: C1DT is the value to be compared with the CVAL value. Whether the written value takes effective immediately depends on the C1OBEN bit, and the corresponding output is generated on C1OUT as configured.
Page 255: Dma Data Register (Tmrx_Dmadt)
AT32F402_405 Series Reference Manual Bit 7: 5 Reserved resd Kept at default value. DMA transfer address offset ADDR is defined as an offset starting from the address of the TMRx_CTRL1 register. Bit 4: 0 ADDR 0x00 00000: TMRx_CTRL1 00001: TMRx_CTRL2 00010: TMRx_STCTRL ..
Page 256: Tmr9 Functional Overview
AT32F402_405 Series Reference Manual Figure 15-38 Block diagram of general-purpose TMR9 Clock failure event From clock control CSS(Clock Security System) Polarity TMRx_BRK BRK filter selection Capture CNT counter Compare Dead time TMRx_CH2 C2IRAW CH2 filter OUT MODE IN MODE STCI C2OUT TMRx_CH2 Output2...
Page 257: Figure 15-40 Control Circuit With Ck_Int, Tmrx_Div=0X0 And Tmrx_Pr=0X16
AT32F402_405 Series Reference Manual Figure 15-40 Control circuit with DIV=0x0 and TMRx_PR=0x16 CK_INT, TMRx_ CK_INT TMREN COUNTER overflow OVFIF External clock (TRGIN/EXT) The counter clock can be provided by the external clock source TRGIN. SMSEL=3’b111: External clock mode A is selected. Select an external clock source TRGIN signal by setting the STIS[2: 0] bit to drive the counter to start counting.
Page 258: Figure 15-42 Counting In External Clock Mode A, Pr=0X32 And Div=0X0
AT32F402_405 Series Reference Manual Figure 15-42 Counting in external clock mode A, PR=0x32 and DIV=0x0 TMR_CLK C2IRAW CK_CNT COUNTER STIS[2:0] C2IF[2:0] OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal from another timer.
Page 259: Counting Mode
AT32F402_405 Series Reference Manual Figure 15-43 Counter timing with prescaler value chang from 1 to 4 TMR_CLK CK_CNT COUNTER DIV[15：0] PR[15：0] OVFIF Clear 15.3.3.2 Counting mode The general-purpose timer (TMR9) consists of a 16-bit counter supporting multiple counting modes to meet different application scenarios.
Page 260: Figure 15-45 Overflow Event When Prben=0
AT32F402_405 Series Reference Manual Figure 15-45 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 15-46 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode This mode is enabled by setting CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1 register. In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed, and generates a counter underflow event.
Page 261: Figure 15-48 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32
AT32F402_405 Series Reference Manual Figure 15-48 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32 TMR_CLK COUNTER OWCDIR PR[15:0] DIV[15:0] TWCMSEL [1：0] OVFIF Clear Clear Clear Repetition counter mode: The TMRx_RPR register is used to enable repetition counting mode. This mode is enabled when the repetition counter value is not equal to 0.
Page 262: Figure 15-50 Encoder Mode Structure
AT32F402_405 Series Reference Manual Encoder interface mode In this mode, the two input (TMRx_CH1 and TMRx_CH2) signals are required. Depending on the level on one input, the counter counts up or down on the edge of the other input signal. The OWCDIR bit indicates the direction of the counter, as shown in the table below: Figure 15-50 Encoder mode structure SMSEL=3'b001/010/011...
Page 263: Tmr Input Function
AT32F402_405 Series Reference Manual Table 15-8 Counting direction versus encoder signals C1IFP1 signal C2IFP2 signal Level on opposite signal Active edge (C1IFP1 to C2IFP2, C2IFP2 to C1IFP1) Rising Falling Rising Falling High Down No count No count Count on C1IFP1 only Down No count No count...
Page 264: Figure 15-52 Input/Output Channel 1 Main Circuit
AT32F402_405 Series Reference Manual Figure 15-52 Input/output channel 1 main circuit filter edge detector input divider STCI C1IRAW TMRx_CH1 C1DF C1P/C1CP C1IDIV C1EN C1IFP1 C1IN C2IFP1 Capture trigger C1DT_shadow CNT counter Capture C1DT Compare C1DT preload C1OCTRL C1OBEN Overflow event C1ORAW polarity select polarity select...
Page 265: Figure 15-54 Pwm Input Mode Configuration Example
AT32F402_405 Series Reference Manual  Set SMSEL=3‘b100: configure the slave mode controller in reset mode  Set C1EN=1’b1 and C2EN=1’b1. Enable channel 1 and input capture After above configuration, the rising edge of channel 1 input signal will trigger the capture and stores the capture value into C1DT register, and it will reset the counter at the same time.
Page 266: Tmr Output Function
AT32F402_405 Series Reference Manual 15.3.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. Figure 15-56 Channel 1 output stage Polarity selection Output enable Dead time...
Page 267: Figure 15-58 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F402_405 Series Reference Manual Forced output mode: Enable forced output mode by setting CxOCTRL=2’b100/101. In this case, the CxORAW is forced to be the programmed level, regardless of the counter value. Despite this, the channel flag bit and DMA request still depend on the compare result. Output compare mode: Enable output compare mode by setting CxOCTRL=3’b001/010/011.
Page 268: Figure 15-60 One-Pulse Mode
AT32F402_405 Series Reference Manual Figure 15-60 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master mode timer event output When TMR is used as a master timer, one of the following source of signals can be selected as TRGOUT output to a slave mode timer. This is done by setting the PTOS bit in the TMRxCTRL2 register. −...
Page 269: Tmr Break Function
AT32F402_405 Series Reference Manual 15.3.3.5 TMR break function When the break function is enabled (BRKEN=1), the CxOUT and CxCOUT are jointly controlled by OEN, FCSODIS, FCSOEN, CxIOS and CxCIOS. But, CxOUT and CxCOUT cannot be set both to active level at the same time.
Page 270: Tmr Synchronization
AT32F402_405 Series Reference Manual Figure 15-63 Example of TMR break function AOEN CxORAW CxEN CxCEN CxIOS CxCIOS CxOUT Delay CxCOUT Delay Delay 15.3.3.6 TMR synchronization The master and slave timers are linked together internally for timer synchronization. Master mode timer is selected by setting the PTOS[2: 0] bit;...
Page 271: Debug Mode
AT32F402_405 Series Reference Manual Figure 15-65 Example of suspend mode TMR_CLK CI1F1 TMR_EN CNT_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] Slave mode: Trigger mode The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1) Figure 15-66 Example of trigger mode TMR_CLK CI1F1 TMR_EN...
Page 272: Tmr9 Control Register1 (Tmrx_Ctrl1)
AT32F402_405 Series Reference Manual TMRx_PR 0x2C 0x0000 TMRx_RPR 0x30 0x0000 TMRx_C1DT 0x34 0x0000 TMRx_C2DT 0x38 0x0000 TMRx_BRK 0x44 0x0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000 15.3.4.1 TMR9 control register1 (TMRx_CTRL1) Abbr. Reset value Type Description Bit 15: 10 Reserved 0x00 resd Kept at default value Clock divider...
Page 273: Tmr9 Control Register 2 (Tmrx_Ctrl2)
AT32F402_405 Series Reference Manual 15.3.4.2 TMR9 control register 2 (TMRx_CTRL2) Abbr. Reset value Type Description Bit 15: 2 Reserved resd Kept at default value. 0x00 Bit 11 C2CIOS Channel 2 complementary idle output state Bit 10 C2IOS Channel 2 idle output state Channel 1 complementary idle output state Output disabled (OEN= 0) after dead-time: Bit 9...
Page 274: Tmr9 Dma/Interrupt Enable Register (Tmrx_Iden)
AT32F402_405 Series Reference Manual Bit 3 Reserved resd Kept at default value. Subordinate TMR mode selection 000: Slave mode is disabled 001: Encoder mode A 010: Encoder mode B 011: Encoder mode C 100: Reset mode —Rising edge of the TRGIN input reinitializes the counter Bit 2: 0 SMSEL...
Page 275: Tmr9 Software Event Register (Tmrx_Swevt)
AT32F402_405 Series Reference Manual This bit indicates whether a recapture is detected when C1IF=1. This bit is set by hardware, and cleared by writing “0”. 0: No capture is detected 1: Capture is detected. Bit 8 Reserved resd Default value Break interrupt flag This bit indicates whether the break input is active or not.
Page 276: Tmr9 Channel Mode Register 1 (Tmrx_Cm1)
AT32F402_405 Series Reference Manual 1: Generate a HALL event. Note: This bit acts only on channels that have complementary output. Bit 4: 3 Reserved resd Kept at its default value. Channel 2 event triggered by software Bit 2 C2SWTR Please refer to C1M description Channel 1 event triggered by software This bit is set by software to generate a channel 1 event.
Page 277 AT32F402_405 Series Reference Manual only subject to the changes of C1ORAW, but also the output polarity set by CCTRL. Channel 1 output buffer enable 0: Buffer function of TMRx_C1DT is disabled. The new value written to the TMRx_C1DT takes effect immediately.
Page 278: Tmr9 Channel Control Register (Tmrx_Cctrl)
AT32F402_405 Series Reference Manual 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’ Channel 1 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when...
Page 279: Table 15-10 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function
AT32F402_405 Series Reference Manual Table 15-10 Complementary output channel CxOUT and CxCOUT control bits with break function Control bit Output state FCSOEN CxEN CxCEN OEN bit FCSODIS bit CxOUT output state CxCOUT output state Output disabled Output disabled (no driven by the timer) (no driven by the timer) CxOUT=0, Cx_EN=0 CxCOUT=0, CxCEN=0...
Page 280: Tmr9 Counter Value (Tmrx_Cval)
AT32F402_405 Series Reference Manual 15.3.4.9 TMR9 counter value (TMRx_CVAL) Abbr. Reset value Type Description Bit 15: 0 CVAL 0x0000 Counter value 15.3.4.10 TMR9 division value (TMRx_DIV) Abbr. Reset value Type Description Divider value The counter clock frequency f / (DIV[15: CK_CNT TMR_CLK Bit 15: 0...
Page 281 AT32F402_405 Series Reference Manual 0010: f , N=4 SAMPLING CK_INT 1010: f /16, N=5 SAMPLING 0011: f , N=8 SAMPLING CK_INT 1011: f /16, N=6 SAMPLING 0100: f /2, N=6 SAMPLING 1100: f /16, N=8 SAMPLING 0101: f /2, N=8 SAMPLING 1101: f /32, N=5...
Page 282: Tmr9 Dma Control Register (Tmrx_Dmactrl)
AT32F402_405 Series Reference Manual 110: DT = (32+ DTC [4: 0]) * TDTS * 8 111: DT = (32+ DTC [4: 0]) * TDTS * 16 15.3.4.16 TMR9 DMA control register (TMRx_DMACTRL) Abbr. Reset value Type Description Bit 15:13 Reserved resd Kept at default value.
Page 283: General-Purpose Timer (Tmr10/11/13/14)
AT32F402_405 Series Reference Manual 15.4 General-purpose timer (TMR10/11/13/14) 15.4.1 TMRx introduction The general-purpose timers (TMR10/11/13/14) consist of a 16-bit upcounter, one capture/compare register, and one independent channel. They can be used for dead-time insertion, input capture and programmable PWM output. 15.4.2 TMRx main features ...
Page 284: Counting Mode
AT32F402_405 Series Reference Manual Figure 15-69 Control circuit with CK_INT, TMRx_DIV=0x0 and PR=0x16 CK_INT TMREN COUNTER overflow OVFIF 15.4.3.2 Counting mode The TMR10/11/13/14 supports multiple counting modes to meet various application scenarios. Each consists of a 16-bit upcounter. The TMRx_PR register is used to define counting period of counter. The value in the TMRx_PR is immediately moved to the shadow register by default.
Page 285: Figure 15-71 Overflow Event When Prben=0
AT32F402_405 Series Reference Manual Figure 15-71 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 15-72 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode This mode is enabled by setting CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1 register. In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed, and generates a counter underflow event.
Page 286: Figure 15-74 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32
AT32F402_405 Series Reference Manual Figure 15-74 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32 TMR_CLK COUNTER OWCDIR PR[15:0] DIV[15:0] TWCMSEL [1：0] OVFIF Clear Clear Clear Repetition counter mode: The TMRx_RPR register is used to enable repetition counting mode. This mode is enabled when the repetition counter value is not equal to 0.
Page 287: Tmr Input Function
AT32F402_405 Series Reference Manual Figure 15-75 OVFIF in upcounting mode and central-aligned mode Example 1 ： up count mode,RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 2 ： two-way up count mode3, RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 3 ： two-way up count mode3, RPR=0x1 COUNTER RPR[7:0] RPR_CNT...
Page 288: Tmr Output Function
AT32F402_405 Series Reference Manual Figure 15-76 Input/output channel 1 main circuit filter edge detector input divider C1IRAW TMRx_CH1 C1DF C1P/C1CP C1IDIV C1EN C1IFP1 C1IN Capture trigger C1DT_shadow CNT counter Capture C1DT Compare C1DT preload C1OCTRL C1OBEN Overflow event C1ORAW polarity select polarity select C1CP Dead time...
Page 289 AT32F402_405 Series Reference Manual to IO after being processed by the output control circuit. The period of the output signal is configured by the TMR15_PR register, while the duty cycle by the TMRx_CxDT register. PWM mode A: Enable PWM mode A by setting CxOCTRL=3’b110. In upcounting mode, C1ORAW outputs high when TMRx_C1DT>TMRx_CVAL, otherwise, it is low;...
Page 290: Figure 15-79 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F402_405 Series Reference Manual Figure 15-79 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW Figure 15-80 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0] C1ORAW >32...
Page 291: Tmr Break Function
AT32F402_405 Series Reference Manual If the delay is greater than the width of the active output, C1OUT and C1COUT will not generate corresponding pulses. Therefore, the dead-time should be less than the width of the active output. Figure 15-82 gives an example of dead-time insertion when CxP=0, CxCP=0, OEN=1, CxEN=1 and CxCEN=1.
Page 292: Debug Mode
AT32F402_405 Series Reference Manual  If AOEN=1, the OEN bit is automatically set again at the next overflow event. Note: When the break input is active, the OEN cannot be set, nor the status flag, BRKIF can be cleared. Figure 15-83 TMR output control Clock failure event brake enable From clock control CSS(Clock Security System)
Page 293: Tmrx Registers
AT32F402_405 Series Reference Manual 15.4.4 TMRx registers Table TMR10/11/13/14 register map and reset value 15-11 Register Offset Reset value TMRx_CTRL1 0x00 0x0000 TMRx_CTRL2 0x04 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CM1 0x18 0x0000 TMRx_CCTRL 0x20 0x0000 TMRx_CVAL 0x24 0x0000...
Page 294: Tmrx Control Register 2 (Tmrx_Ctrl2) (X=10/11/13/14)
AT32F402_405 Series Reference Manual This bit is use to select whether to stop counting at an update event 0: The counter does not stop at an update event 1: The counter stops at an update event Overflow event source This bit is used to select overflow event or DMA request sources.
Page 295: Tmrx Interrupt Status Register (Tmrx_Ists) (X=10/11/13/14)
AT32F402_405 Series Reference Manual Reserved resd Kept at default value. Bit 4: 2 Channel 1 interrupt enable Bit 1 C1IEN 0: Disabled 1: Enabled Overflow interrupt enable Bit 0 OVFIEN 0: Disabled 1: Enabled 15.4.4.4 TMRx interrupt status register (TMRx_ISTS) (x=10/11/13/14) Abbr.
Page 296: Tmrx Channel Mode Register1 (Tmrx_Cm1) (X=10/11/13/14)
AT32F402_405 Series Reference Manual 0: No effect 1: Generate a HALL event. Note: This bit acts only on channels with complementary output. Bit 4: 2 Reserved resd Kept at default value. Channel 1 event triggered by software This bit is set by software to generate a channel 1 event. Bit 1 C1SWTR 0: No effect...
Page 297: Tmrx Channel Control Register (Tmrx_Cctrl) (X=10/11/13/14)
AT32F402_405 Series Reference Manual 1: No need to compare the CVAL and C1DT. An output is generated immediately when a trigger event occurs. Channel 1 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C1EN=’0’: Bit 1: 0 00: Output...
Page 298 AT32F402_405 Series Reference Manual 1: C1OUT is active low When the channel 1 is configured in input mode: The active edge of the input signal is defined by C1CP/C1P. 00: C1IN active edge is on its rising edge. When used as external trigger, C1IN is not inverted.
Page 299: Table 15-12 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function
AT32F402_405 Series Reference Manual Table Complementary output channel CxOUT and CxCOUT control bits with break function 15-12 Control bit Output state FCSOEN CxEN CxCEN OEN bit FCSODIS bit CxOUT output state CxCOUT output state Output disabled Output disabled (no driven by the timer) (no driven by the timer) CxOUT=0, Cx_EN=0 CxCOUT=0, CxCEN=0...
Page 300: Tmrx Counter Value (Tmrx_Cval) (X=10/11/13/14)
AT32F402_405 Series Reference Manual 15.4.4.8 TMRx counter value (TMRx_CVAL) (x=10/11/13/14) Abbr. Reset value Type Description Bit 15: 0 CVAL 0x0000 Counter value 15.4.4.9 TMRx division value (TMRx_DIV) (x=10/11/13/14) Abbr. Reset value Type Description Divider value The counter clock frequency f / (DIV[15: CK_CNT TMR_CLK...
Page 301 AT32F402_405 Series Reference Manual Output enable This bit acts on the channels as output. It is used to enable Bit 15 CxOUT and CxCOUT outputs. 0: Disabled 1: Enabled Automatic output enable OEN is set automatically at an overflow event. Bit 14 AOEN 0: Disabled...
Page 302: Tmrx Dma Control Register (Tmrx_Dmactrl) (X=10/11/13/14)
AT32F402_405 Series Reference Manual 15.4.4.14 TMRX DMA control register (TMRX_DMACTRL) (X=10/11/13/14) Abbr. Reset value Type Description Bit 15:13 Reserved resd Kept at default value. DMA transfer bytes This field defines the number of DMA transfers: 00000: 1 byte 00001: 2 bytes Bit 12:8 0x00 00010: 3 bytes...
Page 303: Advanced-Control Timers (Tmr1)
AT32F402_405 Series Reference Manual 15.5 Advanced-control timers (TMR1) 15.5.1 TMR1 introduction The advanced-control timer TMR1 consists of a 16-bit counter supporting up and down counting modes, four channel registers, and four independent channels. It can be used for dead-time insertion, input capture and programmable PWM output.
Page 304: Figure 15-86 Counting Clock
AT32F402_405 Series Reference Manual Figure 15-86 Counting clock Encoder mode (SMSEL=3'b001/010/011) CK_INT(form CRM) CI1FP1/CI2FP2 STIS[1:0] External clock mode A (SMSEL=3'b111) STIS[2] Internal trigger CK_CNT DIV_counter CNT_counter STIS[1:0] TRGIN C1INC C1IFP1 polarity edge External trigger External clock mode B detector C2IPF2 (ECMBEN=1) TMRx_EXT ESDIV...
Page 305: Figure 15-88 Block Diagram Of External Clock Mode A
AT32F402_405 Series Reference Manual (C2DF[3:0] in TMRx_CM1 register) and channel 2 input polarity (C2P/C2CP in TMRx_CCTR register); If the TMRx_EXT is used as a source of TRGIN, it is necessary to configure the external signal polarity (ESP in TMRx_STCTRL register), external signal frequency division (ESDIV[1:0] in TMRx_STCTRL) and external signal filter (ESF[3:0] in TMRx_STCTRL register).
Page 306: Counting Mode
AT32F402_405 Series Reference Manual Figure 15-91 Counting in external clock mode B, PR=0x32 and DIV=0x0 TMR_CLK CK_CNT COUNTER ESDIV[1:0] ESF[3:0] 0000 OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer.
Page 307: Figure 15-93 Basic Structure Of A Counter
AT32F402_405 Series Reference Manual every DIV[15:0]+1 clock cycle. Similar to TMRx_PR register, after enabling periodic buffer, the value of the TMRx_DIV register are transferred into the shadow register at each overflow event. Reading the TMRx_CNT register returns the current counter value. Writing the TMRx_CNT register will update the current counter value.
Page 308: Figure 15-96 Counter Timing Diagram With Internal Clock Divided By 4
AT32F402_405 Series Reference Manual Figure 15-96 Counter timing diagram with internal clock divided by 4 TMR_CLK CNT_CLK COUNTER PR[15：0] DIV[15：0] OVFIF Clear Up/down counting mode (center-aligned mode) Up/down counting mode can be enabled by setting CMSEL[1:0]≠2’b00 in the TMRx_CTRL1 register. In up/down counting mode, the counter counts up/down alternatively.
Page 309: Figure 15-98 Ovfif Behavior In Upcounting Mode And Center-Aligned Mode
AT32F402_405 Series Reference Manual Figure 15-98 OVFIF behavior in upcounting mode and center-aligned mode Example 1 ： up count mode,RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 2 ： two-way up count mode3, RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 3 ：...
Page 310: Figure 15-100 Example Of Encoder Interface Mode C
AT32F402_405 Series Reference Manual Encoder mode A: SMSEL=3’b001. The counter counts on the selected C1IFP1 edge (rising and falling edges), and the counting direction is dependent on the edge direction of C1IFP1 and the level of C2IFP2. Encoder mode B: SMSEL=3’b010. The counter counts on the selected C2IFP2 edge (rising and falling edges), and the counting direction is dependent on the edge direction of C2IFP2 and the level of C1IFP1.
Page 311: Tmr Input Function
AT32F402_405 Series Reference Manual 15.5.3.3 TMR input function The TMR1 has four independent channels. Each channel can be configured as input or output. As input, each channel input signal is processed as follows: − TMRx_CHx outputs the pre-processed CxIRAW. The C1INSE bit is used to select TMRx_CHx, or the XOR-ed TMRx_CH1, TMRx_CH2 and TMRx_CH3 as the source of C1IRAW.
Page 312: Figure 15-103 Pwm Input Mode Configuration Example
AT32F402_405 Series Reference Manual with the current counter value, and the CxRF is set to 1. To capture the rising edge of C1IN input, following the procedure below:  Set C1C=01 in the TMR1_CM1 register to select the C1IN as channel 1 input ...
Page 313: Tmr Output Function
AT32F402_405 Series Reference Manual Figure 15-104 PWM input mode reset counter and C1DT capture C2DT capture COUNTER STIS SMSEL C1DT C2DT 15.5.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal.
Page 314 AT32F402_405 Series Reference Manual PWM mode A: Enable PWM mode A by setting CxOCTRL=3’b110. In upcounting mode, C1ORAW outputs high when TMRx_C1DT>TMRx_CVAL, otherwise, it is low; In downcounting mode, C1ORAW outputs low when TMRx_C1DT<TMRx_CVAL, otherwise, it is high. To use PWM mode A, the following procedures are recommended: Set PWM periods through TMRx_PR register −...
Page 315: Figure 15-107 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32F402_405 Series Reference Manual Figure 15-107 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW Figure 15-108 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0] C1ORAW >32...
Page 316: Figure 15-110 One-Pulse Mode
AT32F402_405 Series Reference Manual Figure 15-110 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master mode timer event output When TMR is used as a master timer, one of the following source of signals can be selected as TRGOUT output to a slave mode timer. This is done by setting the PTOS bit in the TMRxCTRL2 register. −...
Page 317: Tmr Break Function
AT32F402_405 Series Reference Manual If the delay is greater than the width of the active output, then theC1OUT and C1COUT will not generate corresponding pulses. Therefore the dead-time should be less than the width of the active output. Figure 15-112 gives an example of dead-time insertion when CxP=0, CxCP=0, OEN=1, CxEN=1 and CxCEN=1.
Page 318: Tmr Synchronization
AT32F402_405 Series Reference Manual  If AOEN=1, the OEN bit is automatically set again at the next overflow event. Note: When the break input is active, the OEN cannot be set, nor the status flag, BRKIF can be cleared. Figure 15-113 TMR output control Clock failure event break enable From clock control CSS(Clock Security System)
Page 319: Figure 15-115 Example Of Reset Mode
AT32F402_405 Series Reference Manual Figure 15-115 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] CI1F1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low.
Page 320: Debug Mode
AT32F402_405 Series Reference Manual 15.5.3.7 Debug mode When the microcontroller enters debug mode (Cortex -M4F core halted), the TMR1 counter stops counting by setting the TMR1_PAUSE in the DEBUG module. 15.5.4 TMR1 registers These peripheral registers have to be accessed by half words (16 bits) or words (32 bits). TMR1 registers are mapped into a 16-bit addressable space.
Page 321: Tmr1 Control Register2 (Tmr1_Ctrl2)
AT32F402_405 Series Reference Manual 1: Period buffer is enabled Two-way counting mode selection 00: One-way counting mode, depending on the OWCDIR 01: Central-aligned counting mode 1, The counter counts up and down alternately, the CxIF bit is set only when the counter is counting down Bit 6: 5 TWCMSEL...
Page 322: Tmr1 Slave Timer Control Register (Tmr1_Stctrl)
AT32F402_405 Series Reference Manual 011: Compare pulse 100: C1ORAW signal 101: C2ORAW signal 110: C3ORAW signal 111: C4ORAW signal DMA request source Bit 3 0: Capture/compare event 1: Overflow event Channel control bit flash selection This bit only acts on channels that have complementary output.
Page 323: Tmr1 Dma/Interrupt Enable Register (Tmr1_Iden)
AT32F402_405 Series Reference Manual This field is used to select the subordinate TMR input. 000: Internal selection 0 (IS0) 001: Internal selection 1 (IS1) 010: Internal selection 2 (IS2) 011: Internal selection 3 (IS3) 100: C1IRAW input detector (C1INC) 101: Filtered input 1 (C1IF1) 110: Filtered input 2 (C1IF2) 111: External input (EXT) Please refer to Table 14-11 for more information on ISx...
Page 324: Tmr1 Interrupt Status Register (Tmr1_Ists)
AT32F402_405 Series Reference Manual 0: Disabled 1: Enabled Channel 3 interrupt enable Bit 3 C3IEN 0: Disabled 1: Enabled Channel 2 interrupt enable Bit 2 C2IEN 0: Disabled 1: Enabled Channel 1 interrupt enable Bit 1 C1IEN 0: Disabled 1: Enabled Overflow interrupt enable Bit 0 OVFIEN...
Page 325: Tmr1 Software Event Register (Tmr1_Swevt)
AT32F402_405 Series Reference Manual This bit is set by hardware on a compare event. It is cleared by software. 0: No compare event occurs 1: Compare event is generated Overflow interrupt flag This bit is set by hardware on an overflow event. It is cleared by software.
Page 326 AT32F402_405 Series Reference Manual This field is used to define the direction of the channel 2 (input or output), and the selection of input pin when C2EN=‘0’: 00: Output 01: Input, C2IN is mapped on C2IFP2 10: Input, C2IN is mapped on C1IFP2 11: Input, C2IN is mapped on STCI.
Page 327: Tmr1 Channel Mode Register2 (Tmr1_Cm2)
AT32F402_405 Series Reference Manual Abbr. Reset value Type Description Bit 15: 12 C2DF Channel 2 digital filter Bit 11: 10 C2IDIV Channel 2 input divider Channel 2 configuration This field is used to define the direction of the channel 2 (input or output), and the selection of input pin when C2EN=‘0’: Bit 9: 8...
Page 328: Tmr1 Channel Control Register (Tmr1_Cctrl)
AT32F402_405 Series Reference Manual Bit 10 C4OIEN Channel 4 output enable immediately Channel 4 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C4EN=‘0’: Bit 9: 8 00: Output 01: Input, C4IN is mapped on C4IFP4 10: Input, C4IN is mapped on C3IFP4...
Page 329: Table 15-16 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function
AT32F402_405 Series Reference Manual Please refer to C1EN description. Channel 2 complementary polarity Bit 7 C2CP Please refer to C1P description. Channel 2 complementary enable Bit 6 C2CEN Please refer to C1EN description. Channel 2 polarity Bit 5 Please refer to C1P description. Channel 2 enable Bit 4 C2EN...
Page 330: Tmr1 Counter Value (Tmr1_Cval)
AT32F402_405 Series Reference Manual CxCEN=1 Output disabled (corresponding IO is not driven by the timer, IO floating) Asynchronously: CxOUT=CxP, Cx_EN=0, CxCOUT=CxCP, CxCEN=0; If the clock is present: after a dead-time, CxOUT=CxIOS, CxCOUT=CxCIOS, assuming that CxIOS and CxCIOS do not correspond to CxOUT and CxCOUT active level.
Page 331: Tmr1 Channel 2 Data Register (Tmr1_C2Dt)
AT32F402_405 Series Reference Manual depends on the C1OBEN bit, and the corresponding output is generated on C1OUT as configured. 15.5.4.15 TMR1 channel 2 data register (TMR1_C2DT) Abbr. Reset value Type Description Channel 2 data register When the channel 2 is configured as input mode: The C2DT is the CVAL value stored by the last channel 2 input event (C1IN) Bit 15: 0...
Page 332: Tmr1 Dma Control Register (Tmr1_Dmactrl)
AT32F402_405 Series Reference Manual This bit acts on the channels as output. It is used to enable CxOUT and CxCOUT outputs. 0: Disabled 1: Enabled Automatic output enable OEN is set automatically at an overflow event. Bit 14 AOEN 0: Disabled 1: Enabled Break input validity This bit is used to select the active level of a break input.
Page 333: Tmr1 Dma Data Register (Tmr1_Dmadt)
AT32F402_405 Series Reference Manual This field defines the number of DMA transfers: 00000: 1 byte 00001: 2 bytes 00010: 3 bytes 00011: 4 bytes .... 10000: 17 bytes 10001: 18 bytes Bit 7:5 Reserved resd Kept at default value. DMA transfer address offset ADDR is defined as an offset starting from the address of the TMRx_CTRL1 register:...
Page 334: Window Watchdog Timer (Wwdt)
AT32F402_405 Series Reference Manual 16 Window watchdog timer (WWDT) 16.1 WWDT introduction The window watchdog downcounter must be reloaded in a limited time window to prevent the watchdog circuits from triggering a system reset. The window watch dog is used to detect the occurrence of system malfunctions.
Page 335: Debug Mode
AT32F402_405 Series Reference Manual Table 16-1 Minimum and maximum timeout value when PCLK1=72 MHz Prescaler Min. Timeout value Max. Timeout value 56.5μs 3.64ms 113.5μs 7.28ms 227.5μs 14.56ms 455μs 29.12ms Figure 16-2 Window watchdog timing diagram CNT[6：0] 55 54 52 51 50 4F 4E 4D 4C 4B 4A 41 40 3F 55...
Page 336: Configuration Register (Wwdt_Cfg)
AT32F402_405 Series Reference Manual 16.5.2 Configuration register (WWDT_CFG) Abbr. Reset value Type Description Bit 31: 10 Reserved 0x000000 resd Kept at default value. Reload counter interrupt Bit 9 RLDIEN 0: Disabled 1: Enabled Clock division value 00: PCLK1 divided by 4096 Bit 8: 7 01: PCLK1 divided by 8192 10: PCLK1 divided by 16384...
Page 337: Watchdog Timer (Wdt)
AT32F402_405 Series Reference Manual 17 Watchdog timer (WDT) 17.1 WDT introduction The WDT is driven by a dedicated low-speed clock (LICK). Due to the lower clock accuracy of LICK, the WDT is best suited to the applications that have lower timing accuracy and can run independently outside the main application.
Page 338: Debug Mode
AT32F402_405 Series Reference Manual Figure 17-1 WDT block diagram power domain 1.2 V power domain Prescaler register 8-bit SYNC WDT_DIV prescaler Reload register 12-bit reload 12-bit SYNC WDT_RLD value downcounter Compare CNT=0 reset Windows register 12-bit windows SYNC WDT_WIN value reload at CNT>WIN reset Status register...
Page 339: Command Register (Wdt_Cmd)
AT32F402_405 Series Reference Manual 17.5.1 Command register (WDT_CMD) (Reset in Standby mode) Abbr. Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at default value. Command register 0xAAAA: Reload counter 0x5555: Unlock the write-protected WDT_DIV, WDT_RLD Bit 15: 0 0x0000 and WDT_WIN 0xCCCC: Enable WDT.
Page 340: Window Register (Wdt_Win)
AT32F402_405 Series Reference Manual 17.5.5 Window register (WDT_WIN) (Not reset in Standby mode) Abbr. Reset value Type Description Bit 31: 12 Reserved 0x000000 resd Kept at default value. Window value When the counter value is greater than the window value, Bit 11: 0 0xFFF reloading the counter will trigger a reset.
Page 341: Enhanced Real-Time Clock (Ertc)
AT32F402_405 Series Reference Manual 18 Enhanced real-time clock (ERTC) 18.1 ERTC introduction The real-time clock provides a calendar clock function. The time and date can be modified by modifying the ERTC_TIME and ERTC_DATE register. The ERTC module is in the battery powered domain, which means that it keeps running and free from the influence of system reset as long as VBAT is powered (VBAT must be supplied through VDD domain).
Page 342: Ertc Function Overview
AT32F402_405 Series Reference Manual 18.3 ERTC function overview 18.3.1 ERTC clock ERTC clock source (ERTC_CLK) is selected via clock controller from a LEXT, LICK, and divided HEXT (by setting the ERTCSEL[1:0] in the CRM_BPDC register). The HEXT frequency division value is configured through the ERTC_DIV[4:0] bit in the CRM_CFG register.
Page 343 AT32F402_405 Series Reference Manual ERTC_WP ERTC_SBS Configurable ERTC_TADJ when TADJF=0 ERTC_TSTM ERTC_TSDT ERTC_TSSBS Configurable ERTC_SCAL when CALUPDF=0 ERTC_TAMP Configurable ERTC_ALASBS when ALAWF =1 Configurable ERTC_ALBSBS when ALBWF =1 ERTC_BPRx Clock and calendar initialization After the register write protection is unlocked, follow the procedure below for clock and calendar initialization: 1.
Page 344: Periodic Automatic Wakeup
AT32F402_405 Series Reference Manual read operations. If the result is not aligned, read again until that the results of two read accesses are consistent. Besides, it is also possible to compare the least significant bits of the two read operations to determine their consistency.
Page 345: Reference Clock Detection
AT32F402_405 Series Reference Manual during the 2 ERTC_CLK cycles. When DEC[8: 0] and ADD are sued together, a deviation ranging from -511 to +512 ERTC_CLK cycles can be added during the 2 ERTC_CLK cycles. The effective calibrated frequency (F SCAL) ...
Page 346: Tamper Detection
AT32F402_405 Series Reference Manual 18.3.7 Tamper detection The ERTC has two tamper detection modes: TAMP1 and TAMP2. They can be configured as a level detection with filter or edge detection. TAMP1 uses the TSPIN bit to select either ERTC_MUX1 or ERTC_MUX2 as a tamper pin, while the TAMP2 can only select ERTC_MUX2 as a tamper pin.
Page 347: Ertc Wakeup
AT32F402_405 Series Reference Manual 18.3.9 ERTC wakeup ERTC can be woken up by alarm clock, periodic auto wakeup, time stamp or tamper event. To enable an ERTC interrupt, follow the procedure below: 1. Configure the EXINT line corresponding to ERTC interrupts as an interrupt mode and enable it, and select a rising edge 2.
Page 348: Ertc Registers
AT32F402_405 Series Reference Manual 18.4 ERTC registers These peripheral registers must be accessed by half words (16 bits) or words (32 bits). ERTC registers are 16-bit addressable registers. Table 18-4 ERTC register map and reset values Register name Offset Reset value ERTC_TIME 0x00 0x0000 0000...
Page 349: Ertc Date Register (Ertc_Date)
AT32F402_405 Series Reference Manual 18.4.2 ERTC date register (ERTC_DATE) Abbr. Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at default value. Bit 23: 20 Year tens Bit 19: 16 Year units Week day 0: Forbidden 1: Monday 2: Tuesday Bit 15: 13 3: Wednesday...
Page 350: Ertc Initialization And Status Register (Ertc_Sts)
AT32F402_405 Series Reference Manual Alarm B interrupt enable Bit 13 ALBIEN 0: Alarm B interrupt disabled 1: Alarm B interrupt enabled Alarm A interrupt enable Bit 12 ALAIEN 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled Timestamp enable Bit 11 TSEN 0: Timestamp disabled...
Page 351 AT32F402_405 Series Reference Manual 0: No tamper event 1: Tamper event occurred Timestamp overflow flag 0: No timestamp overflow Bit 12 TSOF rw0c 1: Timestamp overflow occurs If a new time stamp event is detected when time stamp flag (TSF) is already set, this bit will be set by hardware. Timestamp flag 0: No timestamp event 1: Timestamp event occurs...
Page 352: Ertc Divider Register (Ertc_Div)
AT32F402_405 Series Reference Manual 0: Alarm B register write operation not allowed 1: Alarm B register write operation allowed Alarm A register allows write flag Bit 0 ALAWF 0: Alarm A register write operation not allowed 1: Alarm A register write operation allowed 18.4.5 ERTC divider register (ERTC_DIV) Abbr.
Page 353: Ertc Write Protection Register (Ertc_Wp)
AT32F402_405 Series Reference Manual Bit 29: 28 Date tens Bit 27: 24 Date/week day units Hour mask Bit 23 MASK3 0: No hour mask 1: Alarm clock doesn’t care about hours AM/PM 0: AM Bit 22 AMPM 1: PM Note: This bit is applicable for 12-hour format only. It is 0 for 24-hour format.
Page 354: Ertc Time Stamp Date Register (Ertc_Tsdt)
AT32F402_405 Series Reference Manual for 24-hour format. Bit 21: 20 HT Hour tens Bit 19: 16 HU Hour units Bit 15 Reserved resd Kept at default value Bit 14: 12 MT Minute tens Bit 11: 8 MU Minute units Bit 7 Reserved resd Kept at its default value...
Page 355: Ertc Tamper Configuration Register (Ertc_Tamp)
AT32F402_405 Series Reference Manual 18.4.16 ERTC tamper configuration register (ERTC_TAMP) Abbr. Reset value Type Description Bit 31: 19 Reserved 0x0000 resd Kept at default value Output type Bit 18 OUTTYPE 0: Open-drain output 1: Push-pull output Time stamp detection pin selection Bit 17 TSPIN 0: ERTC_MUX1...
Page 356: Ertc Alarm Clock A Subsecond Register (Ertc_Alasbs)
AT32F402_405 Series Reference Manual 1: Tamper detection interrupt enabled Tamper detection 1 valid edge If TPFLT=0: 0: Rising edge Bit 1 TP1EDG 1: Falling edge If TPFLT>0: 0: Low 1: High Tamper detection 1 enable Bit 0 TP1EN 0: Tamper detection 1 disabled 1: Tamper detection 1 enabled 18.4.17 ERTC alarm clock A subsecond register (ERTC_ALASBS) Abbr.
Page 357: Analog-To-Digital Converter (Adc)
AT32F402_405 Series Reference Manual 19 Analog-to-digital converter (ADC) 19.1 ADC introduction The ADC is a peripheral that converts an analog input signal into a 12-bit digital signal. Its sampling rate is as high as 2 MSPS. It has up to 16 channels for sampling and conversion. 19.2 ADC main features In terms of analog: ...
Page 358: Adc Structure
AT32F402_405 Series Reference Manual 19.3 ADC structure Figure 19-1 shows the block diagram of ADC. Figure 19-1 ADC block diagram ADCDIV ADC prescaler HCLK OCTESEL[2:0] ADCCLK OCTEN TMR1_TRGOUT TMR1_CH4 TMR2_TRGOUT TMR3_TRGOUT ADCx_IN0 Trigger TMR9_TRGOUT ADCx_IN1 detection TMR1_CH1 GPIO OCSWTRG Ordinary EXINT11 conversion start ADCx_IN15...
Page 359: Adc Functional Overview
AT32F402_405 Series Reference Manual 19.4 ADC functional overview 19.4.1 Channel management Analog signal channel input: There are 18 analog signal channel inputs for each of the ADCs, expressed by ADC_INx (x=0 to 17).  ADC_IN0 to ADC_IN15 are external analog inputs, ADC_IN16 represents internal temperature sensor, ADC_IN17 represents internal reference voltage.
Page 360: Power-On And Calibration
AT32F402_405 Series Reference Manual Figure 19-2 ADC basic operation process Power-on Calibration Trigger conversion Read data 19.4.2.1 Power-on and calibration Power-on Set the ADC1EN bit in the CRM_APB2EN register to enable ADC clocks: PCLK2 and ADCCLK. Program the desired ADCCLK frequency by setting the ADCDIV bit in the ADC_CCTRL register. ADCCLK is provided by a divided HICK.
Page 361: Trigger
AT32F402_405 Series Reference Manual Figure 19-3 ADC power-on and calibration The ADCEN The ADCAL bit is set by bit is set by software. software. ADCCLK ADCEN STAB RDY flag ADCAL Trigger OCCE flag Powering up Calibration Conversion status The RDY bit The ADCAL The OCCE bit is set by...
Page 362: Conversion Sequence Management
AT32F402_405 Series Reference Manual 19.4.3 Conversion sequence management Only one channel is converted at each trigger, by default, that is, OSN1-defined channel or PSN4-defined channel. The following section describes various conversion sequence modes in detail. This mode enables multiple channels to be converted in a specific sequence. 19.4.3.1 Sequence mode The sequence mode is enabled by setting the SQEN bit in the ADC_CTRL1 register.
Page 363: Repetition Mode
AT32F402_405 Series Reference Manual 19.4.3.3 Repetition mode The repetition mode is enabled by setting the RPEN bit in the ADC_CTRL2 register. When a trigger signal is detected, the ordinary channels will be converted repeatedly. This mode can work in conjunction with the ordinary channel conversion in sequence mode to enable the repeated conversion of the ordinary group.
Page 364: Oversampling
AT32F402_405 Series Reference Manual 19.4.4 Oversampling The converted data of a single oversampling are obtained by enabling multiple conversions of the same channel and then averaging the cumulative converted data.  Oversampling ratio is selected through the OSRSEL bit in the ADC_OVSP register. This bit is used to specify the oversampling multiple, which is done by converting the same channel many times ...
Page 365: Oversampling Of Preempted Group Of Channels
AT32F402_405 Series Reference Manual rdinary oversampling restart mode selection Figure 19-8 Sampling OCLEN=0, OSN1=ADC_IN0 Conversion PCLEN=1, PSN3=ADC_IN4, PSN4=ADC_IN5 Continue mode：OOSEN = 1, POSEN = 0, = 0, OOSRSEL OOSTREN Ordinary Preempted trigger trigger ADC_IN0 ADC_IN0 Ordinary ADC_IN0 ADC_IN0 ADC_IN0 Oversampling Oversampling OCCE flag set halt...
Page 366: Data Management
AT32F402_405 Series Reference Manual Figure 19-10 Oversampling of preempted group of channels Sampling OCLEN=0, OSN1=ADC_IN0 PCLEN=1, PSN3=ADC_IN4, PSN4=ADC_IN5 Conversion OOSEN = 1, POSEN = 1, OOSRSEL = 0, OOSTREN = 0, PCAUTOEN = 1, SQEN = 1 Ordinary trigger Ordinary ADC_IN0 ADC_IN0 ADC_IN0...
Page 367: Status Flag And Interrupts
AT32F402_405 Series Reference Manual 19.4.7 Status flag and interrupts Each ADC has its dedicated ADCx_STS register, namely, ordinary channel conversion start flag (OCCS), preempted channel conversion start flag (PCCS), preempted channel conversion end flag (PCCE), ordinary channel conversion end flag (CCE) and voltage monitor out of range (VMOR). PCCE, CCE and VMOR have their respective interrupt enable bits.
Page 368: Adc Status Register (Adc_Sts)
AT32F402_405 Series Reference Manual 19.5.1 ADC status register (ADC_STS) Accessed by words. Abbr. Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at default value. Ordinary channel conversion start flag This bit is set by hardware and cleared by software (writing 0).
Page 369 AT32F402_405 Series Reference Manual 0: Partitioned mode disabled on ordinary channels 1: Partitioned mode enabled on ordinary channels Preempted group automatic conversion enable after ordinary group Bit 10 PCAUTOEN 0: Preempted group automatic conversion disabled 1: Preempted group automatic conversion enabled Voltage monitoring enable on a single channel 0: Disabled (Voltage monitoring enabled on all channels) Bit 9...
Page 370: Adc Control Register2 (Adc_Ctrl2)
AT32F402_405 Series Reference Manual 19.5.3 ADC control register2 (ADC_CTRL2) Accessed by words. Abbr. Reset value Type Description Kept at default value Bit 30: 26 Reserved 0x00 resd Internal VINTRV enable ITSRVEN Bit 23 0: Internal VINTRV disabled 1: Internal VINTRV enabled Conversion of ordinary channels triggered by software 0: Conversion of ordinary channels not triggered Bit 22...
Page 371: Adc Sampling Time Register 1 (Adc_Spt1)
AT32F402_405 Series Reference Manual When SQEN=0, a single channel is converted each time when a trigger event arrives; when SQEN=1, a group of channels are converted each timer when a trigger event arrives. 1: Repetition mode enabled When SQEN =0, continuous conversion mode on a single channel is enabled at each trigger event;...
Page 372: Adc Sampling Time Register 2 (Adc_Spt2)
AT32F402_405 Series Reference Manual 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN13 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 11: 9 CSPT13 100: 41.5 cycles 101: 55.5 cycles...
Page 373 AT32F402_405 Series Reference Manual Sample time selection of channel ADC_IN9 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 29: 27 CSPT9 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN8 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles...
Page 374 AT32F402_405 Series Reference Manual Sample time selection of channel ADC_IN4 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 14: 12 CSPT4 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN3 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles...
Page 375: Adc Preempted Channel Data Offset Register X (Adc_ Pcdtox) (X=1
AT32F402_405 Series Reference Manual 19.5.6 ADC preempted channel data offset register x (ADC_ PCDTOx) (x=1..4) Accessed by words. Abbr. Reset value Type Description Kept at default value Bit 31: 12 Reserved 0x00000 resd Data offset for Preempted channel x Bit 11: 0 PCDTOx 0x000 Converted data stored in the ADC_PDTx = Raw...
Page 376: Adc Ordinary Sequence Register 3 (Adc_ Osq3)
AT32F402_405 Series Reference Manual Number of 7th conversion in ordinary sequence Note: The number can be 0~17. For example, if the Bit 4: 0 OSN7 0x00 number is set to 8, it means that the 7 conversion is ADC_IN8 channel. 19.5.11 ADC ordinary sequence register 3 (ADC_ OSQ3) Accessed by words.
Page 377: Adc Oversampling Register (Adc_Ovsp)
AT32F402_405 Series Reference Manual 19.5.15 ADC oversampling register (ADC_OVSP) Accessed by words. Abbr. Reset value Type Description Bit 31: 11 Reserved 0x0000 resd Kept at default value. Ordinary oversampling restart mode select When the ordinary oversampling is interrupted by preempted conversions, this bit can be used to select where to resume ordinary conversions.
Page 378: Controller Area Network (Can)
AT32F402_405 Series Reference Manual 20 Controller area network (CAN) 20.1 CAN introduction CAN (Controller Area Network) is a serial communication protocol for real-time and reliable data communication among nodes. It supports the CAN protocol version 2.0A and 2.0B. 20.2 CAN main features ...
Page 379 AT32F402_405 Series Reference Manual Baud rate formula: �� = Nomal Bit Timimg �� = t ��_�� 1 ��2 with = 1 x t ��_�� = (1 + BTS1[3: 0]) x t ��1 �� = (1 + BTS2[2: 0]) x t ��2 ��...
Page 380: Figure 20-2 Frame Type
AT32F402_405 Series Reference Manual Figure 20-2 Frame type Inter-frame Inter-frame space or Data frame (standard identifier) space overload frame 44 + 8* N Ack field Data field CRC field Arbitration field Control field 8* N Inter-frame Inter-frame space or Data frame ( extended identifier) space overload frame 64 + 8* N...
Page 381: Interrupt Management
AT32F402_405 Series Reference Manual 20.4 Interrupt management The CAN controller has four interrupt vectors that can be used to enable or disable interrupts by setting the CAN_INTEN register. Figure 20-3 Transmit interrupt generation TCIEN = 1 TX_INT TM0TCF = 1 TM1TCF = 1 TM2TCF = 1 Figure 20-4 Receive interrupt 0 generation...
Page 382: Design Tips
AT32F402_405 Series Reference Manual 20.5 Design tips The following information can be used as reference for CAN application development:  Debug control When the system enters the debug mode, the CAN controller stops or continues to work normally, depending on the CANx_PAUSE bit in the DEBUG_CTRL register or the PTD bit in the CAN_MCTRL register.
Page 383: Operating Modes
AT32F402_405 Series Reference Manual 20.6.2 Operating modes The CAN controller has three operating modes:  Sleep mode After a system reset, the CAN controller is in Sleep mode. In this mode, the CAN clock is stopped to reduce power consumption and an internal pull-up resistance is disabled. However, the software can still access to the mailbox registers.
Page 384: Test Modes
AT32F402_405 Series Reference Manual 20.6.3 Test modes The CAN controller defines three test modes, including Listen-only mode, Loop back mode and Listen- only combined with Loop back mode. Test mode can be selected by setting the LOEN and LBEN bits in the CAN_BTMG register.
Page 385: Figure 20-9 32-Bit Identifier List Mode
AT32F402_405 Series Reference Manual Figure 20-9 32-bit identifier list mode CAN_FiFB1 CAN_FiFB1[31:21] CAN_FiFB1[20:3] [2:0] CAN_FiFB2 CAN_FiFB2[31:21] CAN_FiFB2[20:3] [2:0] Mapping SID[10:0] EID[17:0] IDT RTR Figure 20-10 16-bit identifier mask mode CAN_FiFB1[15:5] CAN_FiFB1[4:0] Mask CAN_FiFB1[31:21] CAN_FiFB1[20:16] CAN_FiFB2[15:5] CAN_FiFB2[4:0] Mask CAN_FiFB2[31:21] CAN_FiFB2[20:16] Mapping SID[10:0] EID[17:15] Figure 20-11 16-bit identifier list mode...
Page 386 AT32F402_405 Series Reference Manual Filter Filter Filter Filter FIFO0 Active FIFO1 Active bank number bank number CAN_F0FB1[31:0]-ID CAN_F3FB1[15:0]-ID CAN_F0FB2[31:0]-ID CAN_F3FB1[31:16]-ID CAN_F1FB1[15:0]-ID CAN_F3FB2[15:0]-ID CAN_F1FB1[31:16]-ID CAN_F3FB2[31:16]-ID CAN_F1FB2[15:0]-ID CAN_F4FB1[31:0]-ID CAN_F4FB2[31:0]- CAN_F1FB2[31:16]-ID Mask CAN_F2FB1[31:0]-ID CAN_F5FB1[15:0]-ID CAN_F5FB1[31:16]- CAN_F2FB2[31:0]-Mask Mask CAN_F6FB1[15:0]-ID CAN_F5FB2[15:0]-ID CAN_F5FB2[31:16]- CAN_F6FB1[31:16]-Mask Mask CAN_F6FB2[15:0]-ID CAN_F7FB1[15:0]-ID CAN_F6FB2[31:16]-Mask CAN_F7FB1[31:16]-ID...
Page 387: Message Transmission
AT32F402_405 Series Reference Manual  Complete the CAN filter configuration by setting FCS=0 in the CAN_FCTRL register. 20.6.5 Message transmission Register configuration To transmit a message, the application must select one transmit mailbox and configure the CAN_TMIx, CAN_TMCx, CAN_TMDTLx and CAN_TMDTHx registers. Once the mailbox configuration is complete, setting the TMSR bit in the CAN_TMIx register can initiate CAN transmission.
Page 388: Message Reception
AT32F402_405 Series Reference Manual when TMxALF=1. TMxTEF bit: Transmission error flag, indicating that the data transmission failed due to bus error, and an error frame is sent when TMxTEF=1. TMxEF bit: Mailbox empty flag, indicating that the data transmission is complete and the mailbox becomes empty when TMxEF=1.
Page 389: Error Management
AT32F402_405 Series Reference Manual 20.6.7 Error management The status of the current CAN node is indicated by the receive error counter (TEC) and transmit error counter (REC) bits in the CAN_ESTS register. The ETR[6: 4] bit in the CAN_ESTS register is used to record the last error source, and the corresponding interrupts will be generated when the CAN_INTEN register is enabled.
Page 390 AT32F402_405 Series Reference Manual RFI0 1B0h 0xXXXX XXXX RFC0 1B4h 0xXXXX XXXX RFDTL0 1B8h 0xXXXX XXXX RFDTH0 1BCh 0xXXXX XXXX RFI1 1C0h 0xXXXX XXXX RFC1 1C4h 0xXXXX XXXX RFDTL1 1C8h 0xXXXX XXXX RFDTH1 1CCh 0xXXXX XXXX Reserved 1D0h~1FFh FCTRL 200h 0x2A1C 0E01 FMCFG 204h...
Page 391: Can Control And Status Registers
AT32F402_405 Series Reference Manual 20.7.1 CAN control and status registers 20.7.1.1 CAN master control register (CAN_MCTRL) Abbr. Reset value Type Description Bit 31: 17 Reserved 0x0000 resd Kept at default value. Prohibit trans when debug 0: Transmission works during debug 1: Transmission is prohibited during debug.
Page 392: Can Master Status Register (Can_Msts)
AT32F402_405 Series Reference Manual to be set by hardware, that is, the CAN will keep in sleep mode, by default. Freeze mode enable 0: Freeze mode disabled 1: Freeze mode enabled Note: The CAN leaves Freeze mode once 11 consecutive recessive bits have been detected on the RX pin.
Page 393: Can Transmit Status Register (Can_Tsts)
AT32F402_405 Series Reference Manual register is enabled. When set, this bit will generate a status change interrupt. Doze mode acknowledge 0: The CAN is not in Sleep mode. 1: CAN is in Sleep mode. Note: This bit is used to decide whether the CAN is in Sleep mode or not.
Page 394 AT32F402_405 Series Reference Manual For example, in case of free CAN, the value of these two bit becomes 01 after a message transmit request is written. If the transmit box is full, these two bits refer to the number of the transmit mailbox with the lowest priority. For example, when there are three messages are pending for transmission, the identifiers of mailbox 0, mailbox 1 and mailbox 2 are 0x400, 0x433 and 0x411...
Page 395 AT32F402_405 Series Reference Manual start of the next transmission Transmit mailbox 1 arbitration lost flag 0: No arbitration lost 1: Transmit mailbox 1 arbitration lost Note: Bit 10 TM1ALF rw1c This bit is set when the mailbox 1 transmission failed due to an arbitration lost.
Page 396: Can Receive Fifo 0 Register (Can_Rf0)
AT32F402_405 Series Reference Manual bits of mailbox 0. 20.7.1.4 CAN receive FIFO 0 register (CAN_RF0) Abbr. Reset value Type Description Bit 31: 6 Reserved 0x0000000 resd Kept at default value. Receive FIFO 0 release 0: No effect 1: Release FIFO Note: This bit is set by software to release FIFO 0.
Page 397: Can Interrupt Enable Register (Can_Inten)
AT32F402_405 Series Reference Manual It is cleared by software by writing 1. Receive FIFO 1 full flag 0: Receive FIFO 1 is not full 1: Receive FIFO 1 is full Bit 3 RF1FF rw1c Note: This bit is set by hardware when three messages are pending in the FIFO 1.
Page 398 AT32F402_405 Series Reference Manual 0: Receive FIFO 1 overflow interrupt disabled 1: Receive FIFO 1 overflow interrupt enabled Note: The flag bit of this interrupt is the RF1OF bit. An interrupt is generated when this bit and RF1OF bit are set.
Page 399: Can Error Status Register (Can_Ests)
AT32F402_405 Series Reference Manual 20.7.1.7 CAN error status register (CAN_ESTS) Abbr. Reset value Type Description Receive error counter This counter is implemented in accordance with the Bit 31: 24 0x00 receive part of the fault confinement mechanism of the CAN protocol. Transmit error counter This counter is implemented in accordance with the Bit 23: 16...
Page 400: Can Mailbox Registers
AT32F402_405 Series Reference Manual Note: This field defines the number of time unit in Bit time segment 2. Bit time segment 1 tBTS1 = tCAN x (BTS1[3: 0] + 1) Bit 19: 16 BTS1 Note: This field defines the number of time unit in Bit time segment 1.
Page 401: Transmit Mailbox Data Length And Time Stamp Register
AT32F402_405 Series Reference Manual 20.7.2.2 Transmit mailbox data length and time stamp register (CAN_TMCx) (x=0..2) All the bits in the register are write protected when the mailbox is not in empty state. Abbr. Reset value Type Description Transmit mailbox time stamp Bit 31: 16 TMTS 0xXXXX...
Page 402: Receive Fifo Mailbox Data Length And Time Stamp Register (Can_Rfcx) (X=0
AT32F402_405 Series Reference Manual 20.7.2.6 Receive FIFO mailbox data length and time stamp register (CAN_RFCx) (x=0..1) Note: All the receive mailbox registers are read only. Abbr. Reset value Type Description Receive FIFO time stamp Bit 31: 16 RFTS 0xXXXX Note: This field contains the value of the CAN timer sampled at the start of a receive frame.
Page 403: Can Filter Bit Width Configuration Register (Can_ Fbwcfg)
AT32F402_405 Series Reference Manual 20.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG) Note: This register can be written only when FCS=1 in the CAN_FCTRL register (The filter is in configuration mode) Abbr. Reset value Type Description Bit 31: 14 Reserved 0x00000 resd...
Page 404: Usb Full-Speed/High-Speed Device Interface (Otgfs/Hs)
AT32F402_405 Series Reference Manual 21 USB full-speed/high-speed device interface (OTGFS/HS) The AT32F405 series supports OTGFS/OTGHS mode, and the AT32F402 series supports OTGFS mode only. As a dual-role device, the OTGFS/OTGHS is fully compliant with the Universal Serial Bus Specification Revision 2.0.
Page 405: Otgfs/Hs Functional Description
AT32F402_405 Series Reference Manual Figure 21-2 OTGHS block diagram Memory USB 2.0 HS Periphe OTGHS UTMI I/F USB2.0 ral 1 Transceiver Periphe ral 2 GPIO Data FIFO SPRAM 21.2 OTGFS/HS functional description For OTGFS controller, in host mode, it supports full-speed (12Mb/s) and low-speed (1.5 Mb/s) transfers whereas in device mode, it supports only full-speed (12Mb/s) transfer.
Page 406: Otgfs/Hs Clock And Pin Configuration
AT32F402_405 Series Reference Manual together with data output. The OE pulse can be output to device pins. In device mode, the OTGFS/HS offers a unified FIFO buffer for all OUT endpoints, and a separate FIFO buffer for each of IN endpoints. In host mode, a unified receive FIFO is arranged for periodic and non- periodic transfers of all IN endpoints, as well as a unified transmit FIFO for non-periodic transfers of all OUT endpoints.
Page 407: Otgfs/Hs Interrupts
AT32F402_405 Series Reference Manual Table 21-2 OTGHS input/output pins GPIO Description Enable OTGHS in CRM, and configure PA4 multiplexed function OTGHS_SOF register as 0xa Enable OTGHS in CRM, and configure PB13 multiplexed function OTGHS_VBUS PB13 register as 0xa Enable OTGHS in CRM, and configure PB12 multiplexed function OTGHS_ID PB12 register as 0xa...
Page 408: Otgfs/Hs Functional Description
AT32F402_405 Series Reference Manual 21.5 OTGFS/HS functional description 21.5.1 OTGFS/HS initialization If the cable is connected during power-on, the current operation mode bit (CURMOD bit) in the controller interrupt register indicates the current operation mode. If the A-side of the USB cable is connected, the OTGFS/HS controller operates in host mode;...
Page 409: Host Mode
AT32F402_405 Series Reference Manual Table 21-3 OTGFS/HS transmit FIFO SRAM allocation FIFO name SRAM size rx_fifo_size, including setup packets, OUT endpoint control Receive FIFO information and OUT data packets. Transmit FIFO 0 tx_fifo_size[0] Transmit FIFO 1 tx_fifo_size[1] Transmit FIFO 2 tx_fifo_size[2] ……...
Page 410: Refresh Controller Transmit Fifo
AT32F402_405 Series Reference Manual USB performance, and this helps to avoid latency on the AHB line. Typically, two largest packet sizes of space is recommended so that the AHB can get the next data packet while the current packet is being transferred to the USB.
Page 411: Host Initialization
AT32F402_405 Series Reference Manual 21.5.3.1 Host initialization The following steps must be respected to initialize the controller: 1. Unmask interrupt through the PRTINTMSK bit in the OTGFS/HS_GINTMSK register 2. Program the OTGFS/HS_HCFG register to select full-speed or high-speed host mode 3.
Page 412: Queue Depth
AT32F402_405 Series Reference Manual OTGFS_HCCHARx register. When there is a transaction input in the request queue, the controller will trigger a RXFLVL interrupt. The application must generate a channel halted interrupt through the OTGFS/HS_GRXSTSP register. The application is expected to abort a channel on any of the following conditions: ...
Page 413: Special Cases
AT32F402_405 Series Reference Manual  Reading the receive FIFO Figure 21-5 shows the flow chart of reading the receive FIFO. The application must ignore all packet statuses other than IN data packet (0x0010) Figure 21-5 Reading the receive FIFO Start RXFLVL interrupt? Unmask RXFLVL...
Page 414: Host Hfir Feature
AT32F402_405 Series Reference Manual 21.5.3.6 Host HFIR feature The host frame interval register (HFIR) defines the interval between two consecutive SOFs (full-speed), micor-SOFs (HS) or Keep-Alive tokens. This field contains the number of PHY clock for the required frame interval. This is mainly used to adjust the SOF duration in accordance with PHY clock frequencies. Figure 21-6 shows the HFIR behavior when the HFIRRLDCTRL is set to 0x0 in the OTGFS/HS_HFIR register.
Page 415: Initialize Bulk And Control In Transfers
AT32F402_405 Series Reference Manual Figure 21-7 HFIR behavior when HFIRRLDCTRL=0x1 (3)SOF Lost Synchronization NOT Lost Due to HFIR Reload HFIR DN 0 400 399 0 400 ******************** 1 ******************** ******************** Counter Application Load Of HFIR HFIR (6)SOF back in (2)HFIR Reloaded Synchronization (5)New HFIR Value (1)Old HFIR Value...
Page 416 AT32F402_405 Series Reference Manual 7. The application must read the receive packet status, and ignore it when the receive packet status is not an IN data packet 8. The controller generates the XFERC interrupt as soon as the receive packet is read 9.
Page 417: Initialize Bulk And Control Out/Setup Transfers
AT32F402_405 Series Reference Manual Reset Error Count 21.5.3.8 Initialize bulk and control OUT/SETUP transfers Figure 21-8 shows a typical bulk or control transfer OUT/SETUP transfer operation. Refer to channel 1 (ch_1) for more information. It is necessary to send two bulk transfer OUT packets. The control transfer SETUP operation is the same, just the fact that it has only one packet.
Page 418: Figure 21-8 Example Of Common Bulk/Control Out/Setup And Bulk/Control In Transfer
AT32F402_405 Series Reference Manual Figure 21-8 Example of common Bulk/Control OUT/SETUP and Bulk/Control IN transfer Application Host Device init_reg(ch_1) Non-periodic Request init_reg(ch_2) Queue write_tx_fifo Assume that this queue can (ch_1) hold 4 entries. set_ch_en(ch_2) write_tx_fifo (ch_1) ch_1 set_ch_en(ch_2) ch_2 ch_1 ch_2 DATA0 set_ch_en(ch_2)
Page 419: Initialize Interrupt In Transfers
AT32F402_405 Series Reference Manual Rewind Buffer Pointers Unmask CHHLTD Disable Channel if (XactErr) Increment Error Count Unmask ACK else Reset Error Count else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (Do ping protocol for HS) else if (ACK) Reset Error Count Mask ACK...
Page 420 AT32F402_405 Series Reference Manual 3. The OTGFS/HS host writes an IN request to the periodic request queue each time the CHENA is set in the OTGFS/HS_HCCHAR2 register 4. The OTGFS/HS host attempts to send an IN token in the next frame (odd) 5.
Page 421: Initialize Interrupt Out Transfers
AT32F402_405 Series Reference Manual else if (XACTERR) Increment Error Count Unmask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) Reset Error Count Mask ACK The application can only write a request to the same channel when the remaining space in the request...
Page 422: Figure 21-9 Shows An Example Of Common Interrupt Out/In Transfers
AT32F402_405 Series Reference Manual Figure 21-9 shows an example of common interrupt OUT/IN transfers Application Host Device init_reg(ch_1) Periodic Request Queue init_reg(ch_2) Assume that this queue can hold 4 entries. write_tx_fifo (ch_1) set_ch_en(ch_2) ch_1 ch_2 Odd (micro) frame DATA0 XFERC interrupt init_reg(ch_1) write_tx_fifo...
Page 423: Initialize Synchronous In Transfers
AT32F402_405 Series Reference Manual Reset Error Count Mask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 uF/F) else if (ACK) Reset Error Count Mask ACK Before switching to other channels (if any), the application can only write packets to the transmit FIFO and request queue according to the number defined in the MC filed when the transmit FIFO has free...
Page 424 AT32F402_405 Series Reference Manual not an IN packet (GRXSTSR.PKTSTS!= 0x0010) 8. The controller generates an XFERC interrupt as soon as the receive packet is read 9. To handle the XFERC interrupt, read the PKTCN bit in the OTGFS/HS_HCTSIZ2 register. If the PKTCNT bit in the OTGFS/HS_HCTSIZ2 is not equal to 0, disable the channel before re-initializing the channel for the next transfer.
Page 425: Initialize Synchronous Out Transfers
AT32F402_405 Series Reference Manual 21.5.3.12 Initialize synchronous OUT transfers Figure 21-10 shows a typical synchronous OUT transfer operation. Refer to channel 1 (ch_1). The assumptions are as follows:  The application is attempting to send one largest-packet-size packet (transfer size is 1024 bytes) to every frame from the next odd frame ...
Page 426: Otgfs/Hs Device Mode
AT32F402_405 Series Reference Manual Unmask (FRMOVRUN/XFERC) if (XFERC) De-allocate Channel else if (FRMOVRUN) Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD De-allocate Channel 21.5.4 OTGFS/HS device mode 21.5.4.1 Device initialization The application must perform the following steps to initialize the controller at device startup time, during power-on or after switching from host mode to device mode: 1.
Page 427: Endpoint Initialization On Enumeration Completion
AT32F402_405 Series Reference Manual 3. To receive/transmit data, the device must perform Device initialization steps to initialize registers 4. Allocate SRAM for each endpoint Program the OTGFS/HS_GRXFSIZ register to be able to receive control OUT data and SETUP  data. If the allocated SRAM is equal to at least 1 largest-packet-size of control endpoint 0 + 2 WORDs (for the status of the control OUT data packet) +10 WORDs (for setup packets) ...
Page 428: Endpoint Activation
AT32F402_405 Series Reference Manual 21.5.4.6 Endpoint activation This section describes how to activate a device endpoint or configure an existing device endpoint to a new type. 1. Program the following bits in the OTGFS/HS_DIEPCTLx register (for IN or bidirectional endpoints) or the OTGFS/HS_DOEPCTLx register (for OUT or bidirectional endpoints) Largest packet size ...
Page 429: Control Read Transfers (Setup/Data In/Status Out)
AT32F402_405 Series Reference Manual generated on the endpoint, which indicates the end of control write transfers. 21.5.4.9 Control read transfers (SETUP/Data IN/Status OUT) This section describes the steps required for control read transfers. The application programming process is as follows: ...
Page 430: Figure 21-11 Read Receive Fifo
AT32F402_405 Series Reference Manual 3. If the received packet byte is not 0, the byte count amount of data is popped from the receive data FIFO and stored in memory. If the received packet byte count is 0, no data is read from the receive data FIFO 4.
Page 431: Out Data Transfers
AT32F402_405 Series Reference Manual 21.5.4.12 OUT data transfers This section describes the internal data flow during data OUT and SETUP transfers, and how the application handles SETUP transfers. (1) Setup transfers This section describes how to handle SETUP data packets and the application’s operating sequence of handling SETUP transfers.
Page 432: In Data Transfers
AT32F402_405 Series Reference Manual 2. Wait for the RXFLVL interrupt bit in the OTGFS/HS_GINTSTS register and read and empty the data packets from the receive FIFO (Refer to Read FIFO packets for details). This operation can be repeated several times. 3.
Page 433: Non-Periodic (Bulk And Control) In Data Transfers
AT32F402_405 Series Reference Manual  In interrupt mode, the application must wait for the TXFEMP interrupt bit in the OTGFS_DIEPINTx register, and then read the OTGFS/HS_DTXFSTSx register to determine whether there is enough space in the data FIFO.  To write a single non-zero-length data packet, there must be enough space to write the entire data packet in the data FIFO.
Page 434: Non-Synchronous Out Data Transfers
AT32F402_405 Series Reference Manual maintained by the controller. For an IN endpoint FIFO, the maximum number of packets maintained by the controller at any time is 8). For non-zero-length packets, a separate flag is set for each FIFO, without any data in the FIFO. 4.
Page 435 AT32F402_405 Series Reference Manual 2. Once the NAK bit is cleared, the controller starts receiving data and writes it to the receive FIFO as long as there is available space in the receive FIFO. For each data packet received on the USB line, the data packet and its status are written to the receive FIFO.
Page 436: Synchronous Out Data Transfers
AT32F402_405 Series Reference Manual Figure 21-13 BULK OUT transfer block diagram Host Device Application XFERSIZE = 512bytes int_out_ep PKTCNT = 1 wr_reg(DOEPTSIZn) EPENA = 1 CNAK = 1 wr_reg(DOEPCTLn) 512 bytes xact_1 idle until intr On new xfer or RXFIFO not rcv_out_pkt() empty idle until intr...
Page 437 AT32F402_405 Series Reference Manual 【Application requirements】 1. All the application requirements are the same as that of non-synchronous OUT data transfers. 2. For synchronous OUT data transfers, the transfer size and packet count must be set to the number of the largest-packet-size packets that can be received in a single frame and not exceed this size. Synchronous OUT data transfer cannot span more than one frame.
Page 438: Enable Synchronous Endpoints
AT32F402_405 Series Reference Manual 21.5.4.17 Enable synchronous endpoints After sending a Set interface control command to the device, a host enables the synchronous endpoints. Then the host can send the initial synchronous IN token in any frame before transmission in the sequence of BInterval.
Page 439: Incomplete Synchronous Out Data Transfers
AT32F402_405 Series Reference Manual  When an interrupt is generated (INCOMPISOIN bit in OTGFS/HS_GINTSTS register), clear the INCOMPISOIN interrupt; For any synchronous IN endpoint, when Odd/Even bits match the current frame number bit 0, and when the endpoint remains enabled, the controller generates an interrupt at the end of the frame.
Page 440: Incomplete Synchronous In Data Transfers
AT32F402_405 Series Reference Manual incomplete data transfer in the current frame. An endpoint transfer is regarded as incomplete if both of the following conditions are met:  OTGFS/HS_DOEPCTLx. Even/Odd frame bit= OTGFS_DSTS.SOFFN[0]  OTGFS/HS_DOEPCTLx. Endpoint enable = 0x1 4. The pervious step must be performed before the SOF interrupt of the GINTSTS register is detected to ensure that the current frame number is not changed.
Page 441 AT32F402_405 Series Reference Manual 【Application requirements】 1. Application requirements in “Non-periodic (bulk and control) IN data transfers” also apply to periodic IN data transfers, except for a slight difference of requirement 2.  The application can only transmit multiples of largest-packet-size data packets, and a short packet.
Page 442: Otgfs Control And Status Registers
AT32F402_405 Series Reference Manual 5. If the interrupt endpoint is already enabled while this interrupt is detected, ignore the interrupt. If it is not enabled, enable the endpoint to transmit data on the next IN token. If it is enabled while the interrupt is detected, refer to “Incomplete synchronous IN data transfers”.
Page 443: Otgfs/Hs Register Address Map
AT32F402_405 Series Reference Manual Figure 21-14 CSR memory map 0000h The overall situation of the core CSRs(1024 byte) 0400h Host mode CSRs (1024 byte) 0800h Device mode CSRs (1024 byte) 0E00h Power and clock control CSRs (512 byte) 1000h Equipment EP 0/host channel 0 FIFO (4096 byte) 2000h Equipment EP 1/host channel 1 FIFO (4096 byte) DFIFO...
Page 444: Table 21-5 Otgfs/Hs Register Map And Reset Values
AT32F402_405 Series Reference Manual Table 21-5 OTGFS/HS register map and reset values Register name Offset Reset value OTGFS/HS_GOTGCTL 0x000 0x0001 0000 OTGFS/HS_GOTGINT 0x004 0x0000 0000 OTGFS/HS_GAHBCFG 0x008 0x0000 0000 OTGFS/HS_GUSBCFG 0x00C 0x0000 1400 OTGFS/HS_GRSTCTL 0x010 0x2000 0000 OTGFS/HS_GINTSTS 0x014 0x0400 0020 OTGFS/HS_GINTMSK 0x018 0x0000 0000...
Page 445 AT32F402_405 Series Reference Manual OTGFS/HS_HCTSIZ1 0x530 0x0000 0000 OTGHS_HCDMA1 0x534 0x0000 0000 OTGFS/HS_HCCHAR2 0x540 0x0000 0000 OTGFS/HS_HCINT2 0x548 0x0000 0000 OTGFS/HS_HCINTMSK2 0x54C 0x0000 0000 OTGFS/HS_HCTSIZ2 0x550 0x0000 0000 OTGHS_HCDMA2 0x554 0x0000 0000 OTGFS/HS_HCCHAR3 0x560 0x0000 0000 OTGFS/HS_HCINT3 0x568 0x0000 0000 OTGFS/HS_HCINTMSK3 0x56C 0x0000 0000...
Page 446 AT32F402_405 Series Reference Manual OTGHS_HCDMA9 0x634 0x0000 0000 OTGFS/HS_HCCHAR10 0x640 0x0000 0000 OTGFS/HS_HCINT10 0x648 0x0000 0000 OTGFS/HS_HCINTMSK10 0x64C 0x0000 0000 OTGFS/HS_HCTSIZ10 0x650 0x0000 0000 OTGHS_HCDMA10 0x654 0x0000 0000 OTGFS/HS_HCCHAR11 0x660 0x0000 0000 OTGFS/HS_HCINT11 0x668 0x0000 0000 OTGFS/HS_HCINTMSK11 0x66C 0x0000 0000 OTGFS/HS_HCTSIZ11 0x670 0x0000 0000...
Page 447 AT32F402_405 Series Reference Manual OTGHS_DIEPEACHMSK1 0x844 0x0000 0000 OTGHS_DOEPEACHMSK1 0x884 0x0000 0000 OTGFS/HS_DIEPCTL0 0x900 0x0000 0000 OTGFS/HS_DIEPINT0 0x908 0x0000 0080 OTGFS/HS_DIEPTSIZ0 0x910 0x0000 0000 OTGHS_DIEPDMA0 0x914 0x0000 0000 OTGFS/HS_DTXFSTS0 0x918 0x0000 0200 OTGFS/HS_DIEPCTL1 0x920 0x0000 0000 OTGFS/HS_DIEPINT1 0x928 0x0000 0080 OTGFS/HS_DIEPTSIZ1 0x930 0x0000 0000...
Page 448: Otgfs/Hs Global Registers
AT32F402_405 Series Reference Manual OTGFS/HS_DTXFSTS7 0x9F8 0x0000 0200 OTGFS/HS_DOEPCTL0 0xB00 0x0000 8000 OTGFS/HS_DOEPINT0 0xB08 0x0000 0080 OTGFS/HS_DOEPTSIZ0 0xB10 0x0000 0000 OTGHS_DOEPDMA0 0xB14 0x0000 0000 OTGFS/HS_DOEPCTL1 0xB20 0x0000 0000 OTGFS/HS_DOEPINT1 0xB28 0x0000 0080 OTGFS/HS_DOEPTSIZ1 0xB30 0x0000 0000 OTGHS_DOEPDMA1 0xB34 0x0000 0000 OTGFS/HS_DOEPCTL2 0xB40 0x0000 0000...
Page 449: Otgfs/Hs Status And Control Register (Otgfs/Hs_Gotgctl)
AT32F402_405 Series Reference Manual 21.6.3.1 OTGFS/HS status and control register (OTGFS/HS_GOTGCTL) This register is used to control the OTG function and reflect its status. Abbr. Reset value Type Description Bit 31: 22 Reserved 0x0000 resd Kept at default value. Current Mode of Operation Accessible in both host and device modes Bit 21 CURMOD...
Page 450: Otgfs/Hs Usb Configuration Register (Otgfs/Hs_Gusbcfg)
AT32F402_405 Series Reference Manual In master mode and device mode Burst length/type 0000 :Single Bit 4: 1 HBstLen 0001 :INCR4 0011 :INCR8 0101 :INCR16 Others: reserved Accessible in both host mode and device modes Global interrupt mask The application uses this bit to mask or unmask the Bit 0 GLBINTMSK interrupts sent by the interrupt line to itself.
Page 451: Otgfs/Hs Reset Register (Otgfs/Hs_Grstctl)
AT32F402_405 Series Reference Manual 1: Reserved, please do not use Bit 5: 3 Reserved 0x00 resd Kept at default value. Accessible in both host mode and device mode FS/HS Timeout calibration The number of PHY clocks that the application programs in these bits is added to the full-speed/high-speed interpacket timeout duration in order to compensate for any additional latency introduced by the PHY.
Page 452 AT32F402_405 Series Reference Manual Read: NAK effective interrupt (NAK Effective Interrupt) ensures that the controller is not reading from the FIFO Write: AHBIDLE bit in GRSTCTL ensures that the controller is not writing to the FIFO. For FIFO reprogramming, it is usually recommended to carry out flushing operation.
Page 453: Otgfs/Hs Interrupt Register (Otgfs/Hs_Gintsts)
AT32F402_405 Series Reference Manual must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay). Additionally, the application must ensure that the bit 31 in this register is set (AHB master is in idle state) before performing other operations. Typically, the software set is used during software development and also when the user dynamically changes the PHY selection bits in the above-listed USB...
Page 454 AT32F402_405 Series Reference Manual status one of the ports. The application must read the Host Port Control and Status register to determine the exact event source. The application must clear the Host Port Control and Status register to clear this bit. Bit 23: 22 Reserved resd...
Page 455 AT32F402_405 Series Reference Manual enumeration is done. The application must read the Device Status register to obtain the enumeration speed. Accessible in device mode only USB Reset Bit 12 USBRST rw1c The controller sets this bit to indicate that a reset is detected on the USB bus.
Page 456: Otgfs/Hs Interrupt Mask Register (Otgfs/Hs_Gintmsk)
AT32F402_405 Series Reference Manual received (in device mode). The reading of this register is valid only when an effective connection has been established between the host and the device. If this bit is set after power-on reset, the application can clear this bit. Accessible in both host and device mode OTG interrupt The controller sets this bit to indicate that an OTG...
Page 457: Otgfs/Hs Receive Status Debug Read/Otg Status Read And Pop Registers (Otgfs/Hs_Grxstsr / Otgfs/Hs_Grxstsp)
AT32F402_405 Series Reference Manual Accessible in device mode only Bit 18 IEPTINTMSK IN endpoints interrupt mask Bit 17 Reserved Kept at default value. Bit 16 Reserved resd Kept at default value. Accessible in device mode only Bit 15 EOPFMSK End of periodic frame interrupt mask Device only isochronous OUT packet dropped interrupt Bit 14 ISOOUTDROPMSK...
Page 458: Otgfs/Hs Receive Fifo Size Register (Otgfs/Hs_Grxfsiz)
AT32F402_405 Series Reference Manual Channel number Bit 3: 0 CHNUM Indicates the channel number to which the currently received data packet belongs. Device mode: Abbr. Reset value Type Description Bit 31: 25 Reserved 0x00 resd Kept at default value. Frame number Indicates the least significant 4 bits of the frame number Bit 24: 21 of the data packet received on the USB bus.
Page 459: Otgfs/Hs Non-Periodic Tx Fifo Size/Request Queue Status Register
AT32F402_405 Series Reference Manual Device: Abbr. Reset value Type Description N Endpoint TxFIFO 0 depth This value is in terms of 32-bit words. Bit 31: 16 INEPT0TXDEP 0x0000 ro/rw Minimum value is 16 Maximum value is 256 IN Endpoint FIFO0 transmit SRAM start address Bit 15: 0 INEPT0TXSTADDR 0x0200...
Page 460: Otgfs/Hs Controller Id Register (Otgfs/Hs_Guid)
AT32F402_405 Series Reference Manual external clock VBUS ignored When this bit is set, the OTGFS controller does not monitor the Vbus pin voltage, and assumes that the Vbus Bit 21 VBUSIG is always active in both host and device modes, and leaves the Vbus pin for other purposes.
Page 461: Otgfs/Hs Device In Endpoint Tx Fifo Size Register
AT32F402_405 Series Reference Manual 21.6.3.15 OTGFS/HS device IN endpoint Tx FIFO size register (OTGFS/HS_DIEPTXFn) (x=1…15, where n is the FIFO number) This register holds the depth and memory start address of the IN endpoint transmit FIFO in device mode. Each of the FIFOs contains an IN endpoint data. This register can be used repeatedly for instantiated IN endpoint FIFO1~15.
Page 462: Otgfs/Hs Host Frame Number/Frame Time Remaining Register (Otgfs/Hs_Hfnum)
AT32F402_405 Series Reference Manual change its value at runtime. Frame interval The application uses this filed to program the interval between two consecutive SOFs (full speed) or micro- SOFs (high speed) or Keep-Alive tokens. The number of PHY locks in this field indicates the frame interval.
Page 463: Otgfs/Hs Host All Channels Interrupt Register (Otgfs/Hs_Haint)
AT32F402_405 Series Reference Manual N: n space available (0 ≤ n ≤ 8) Others: Reserved Periodic transmit data FIFO space available Indicates the number of free space available to be written in the periodic transmit FIFO, in terms of 32-bit words. 0000: Periodic transmit FIFO is full Bit 15: 0 PTXFSPCAVAIL...
Page 464 AT32F402_405 Series Reference Manual The application uses this bit to control power supply to this port (by writing 1 or 0) 0: Power off 1: Power on Note: This bit is not associated with interfaces. The application must follow the programming manual to set this bit for various interfaces.
Page 465: Otgfs/Hs Host Channelx Characteristics Register (Otgfs/Hs_Hccharx) (X = 0
AT32F402_405 Series Reference Manual Port enable/disable change The controller sets this bit when the status of the port Bit 3 PRTENCHNG rw1c enable bit 2 in this register changes. This bit can only be set by the controller. The application must write 1 to clear this bit.
Page 466: Otgfs/Hs Host Channelx Split Register (Otgfs/Hs_Hcspltx)
AT32F402_405 Series Reference Manual The application sets this bit to indicate that this channel is communicating to a low-speed device. Bit 16 Reserved resd Kept at default value. Endpoint direction Indicates whether the transfer is in IN or OUT. Bit 15 EPTDIR 0: OUT 1: IN...
Page 467: Otgfs/Hs Host Channelx Interrupt Register (Otgfs/Hs_Hcintx)
AT32F402_405 Series Reference Manual 21.6.4.10 OTGFS/HS host channelx interrupt register (OTGFS/HS_HCINTx) (x = 0...15, where x= channel number) This register contains the status of a channel related to USB and AHB events, as shown in Figure 22-2. The application must read this register when the host channels interrupt bit is set in the controller interrupt register.
Page 468: Otgfs/Hs Host Channelx Interrupt Mask Register
AT32F402_405 Series Reference Manual 21.6.4.11 OTGFS/HS host channelx interrupt mask register (OTGFS/HS_HCINTMSKx) (x = 0...15, where x= channel number) This register is used to mask the channels described in the previous section. Abbr. Reset value Type Description Bit 31: 11 Reserved 0x000000 resd...
Page 469: Device-Mode Registers
AT32F402_405 Series Reference Manual 21.6.5 Device-mode registers These registers are applicable in device mode only. They are not supported in host mode due to unknown access results. Some of the registers affect all the endpoints, while some affect only one endpoint. 21.6.5.1 OTGFS/HS device configure register (OTGFS/HS_DCFG) This register configures the controller in device mode after power-on or after certain control commands or enumeration.
Page 470: Table 21-6 Minimum Duration For Software Disconnect
AT32F402_405 Series Reference Manual NAK. Set global Non-periodic IN NAK Writing to this bit sets the global Non-periodic OUT NAK. The application uses this bit to send a NAK handshake Bit 7 SGNPINNAK on all non-periodic IN endpoints. The application must set this bit only after checking that the global IN NAK effective bit in the controller interrupt register is cleared.
Page 471: Otgfs/Hs Device Status Register (Otgfs/Hs_Dsts)
AT32F402_405 Series Reference Manual 21.6.5.3 OTGFS/HS device status register (OTGFS/HS_DSTS) This register indicates the status of the controller related to OTGFS events. It must be read on interrupt events from the device all interrupts register (OTGFS_DAINT). Abbr. Reset value Type Description Bit 31: 22 Reserved...
Page 472: Otgfs/Hs Device Out Endpoint Common Interrupt Mask Register
AT32F402_405 Series Reference Manual 0: Interrupt masked 1: Interrupt unmasked IN token received when TxFIFO empty mask Bit 4 INTKNTXFEMPMSK 0x0 0: Interrupt masked 1: Interrupt unmasked Timeout condition mask (Non-isochronous endpoints)) Bit 3 TIMEOUTMSK 0: Interrupt masked 1: Interrupt unmasked AHB Error Mask (for OTGHS mode only) Bit 2 AHBERRMSK...
Page 473: Otgfs/Hs Device All Endpoints Interrupt Mask Register (Otgfs/Hs_Daint)
AT32F402_405 Series Reference Manual 1: Interrupt unmasked 21.6.5.6 OTGFS/HS device all endpoints interrupt mask register (OTGFS/HS_DAINT) When an event occurs on an endpoint, The IN/OUT endpoint interrupt bits in the OTGS_DAINT register can be used to interrupt the application. There is one interrupt pit per endpoint, up to 8 interrupt bits for OUT endpoints and 8 bits for IN endpoints.
Page 474: Otgfs/Hs Device In Endpoint Fifo Empty Interrupt Mask Register (Otgfs/Hs_Diepempmsk)
AT32F402_405 Series Reference Manual 21.6.5.8 OTGFS/HS device IN endpoint FIFO empty interrupt mask register (OTGFS/HS_DIEPEMPMSK) This register works with the TXFE_OTGFS_DIEPINTx register to generate an interrupt. Abbr. Reset value Type Description Bit 31: 8 Reserved 0x0000 resd Kept at default value. IN endpoint Tx FIFO empty interrupt mask bits These bits serve as mask bits for the device IN endpoint interrupt register.
Page 475: Otghs Device Out Endpoint 1 Interrupt Mask Register
AT32F402_405 Series Reference Manual 0: Interrupt masked 1: Interrupt unmasked Transfer completed interrupt mask Bit 0 XFERCMSK 0: Interrupt masked 1: Interrupt unmasked 21.6.5.12 OTGHS device OUT endpoint 1 interrupt mask register (OTGHS_ DOEPEACHMSK1)) Abbr. Reset value Type Description Bit 31: 15 Reserved 0x00000 resd...
Page 476: Otgfs/Hs Device Control In Endpoint 0 Control Register
AT32F402_405 Series Reference Manual 21.6.5.13 OTGFS/HS device control IN endpoint 0 control register (OTGFS/HS_DIEPCTL0) This section describes the control IN endpoint 0 control register. Nonzero control endpoint uses registers for endpoints 1-7. Abbr. Reset value Type Description Endpoint enable – The application sets this bit to start data transmission on the endpoint 0.
Page 477: Otgfs/Hs Device In Endpoint-X Control Register
AT32F402_405 Series Reference Manual 21.6.5.14 OTGFS/HS device IN endpoint-x control register (OTGFS/HS_DIEPCTLx) (x=1…7, where x is endpoint number) The application uses this register to control the behavior of the endpoints other than endpoint 0. Abbr. Reset value Type Description Endpoint enable The application sets this bit to start transmitting data on an endpoint.
Page 478 AT32F402_405 Series Reference Manual USB host to this endpoint. If a NAK bit, global non- periodic IN NAK bit or global OUT NAK bit is set along with this bit, the STALL bit has priority. Only the application can clear this bit, but the controller never. 0: Stall all invalid tokens 1: Stall all valid tokens Bit 20...
Page 479: Otgfs/Hs Device Control Out Endpoint 0 Control Register
AT32F402_405 Series Reference Manual The application uses this field to set the maximum packet size for the current logical endpoint. The values are in bytes. 21.6.5.15 OTGFS/HS device control OUT endpoint 0 control register (OTGFS/HS_DOEPCTL0) This section describes the control OUT endpoint 0 control register. Non-zero control endpoints use registers for endpoints 1-7.
Page 480: Otgfs/Hs Device Control Out Endpoint-X Control Register
AT32F402_405 Series Reference Manual 01: 32 bytes 10: 16 bytes 11: 8 bytes 21.6.5.16 OTGFS/HS device control OUT endpoint-x control register (OTGFS/HS_DOEPCTLx) (x=1…7, where x if endpoint number) This application uses this register to control the behavior of all endpoints other than endpoint 0. Abbr.
Page 481 AT32F402_405 Series Reference Manual endpoints. The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit , global non- periodic IN NAK bit or global OUT NAK bit is set along with this bit, the STALL bit has priority.
Page 482: Otgfs/Hs Device In Endpoint-X Interrupt Register
AT32F402_405 Series Reference Manual 0: Inactive 1: Active Bit 14: 11 Reserved resd Kept at default value. Maximum packet size The application uses this field to set the maximum packet Bit 10: 0 0x000 size for the current logical endpoint. The values are in bytes.
Page 483: Otgfs/Hs Device Out Endpoint-X Interrupt Register
AT32F402_405 Series Reference Manual 21.6.5.18 OTGFS/HS device OUT endpoint-x interrupt register (OTGFS/HS_DOEPINTx) (x=0…7, where x if endpoint number) This register indicates the status of an endpoint with respect to USB and AHB-related events, as shown Figure 21-3. When the OEPINT bit of the OTGFS/HS_GINTSTS register is set, the application must first read the OTGFS_DAINT register to get the exact endpoint number in which the event occurs, before reading the endpoint interrupt registers.
Page 484: Otgfs/Hs Device In Endpoint 0 Transfer Size Register
AT32F402_405 Series Reference Manual 21.6.5.19 OTGFS/HS device IN endpoint 0 transfer size register (OTGFS/HS_DIEPTSIZ0) The application must set this register before enabling endpoint 0. Once the endpoint 0 is enabled using the endpoint enable pin in the device endpoint 0 control register, the controller modifies this register. The application can only read this register as long as the controller clears the endpoint enable bit.
Page 485: Otgfs/Hs Device In Endpoint-X Transfer Size Register
AT32F402_405 Series Reference Manual 21.6.5.21 OTGFS/HS device IN endpoint-x transfer size register (OTGFS/HS_DIEPTSIZx) (x=1…7, where x is endpoint number) The application must set this register before enabling endpoint x. Once the endpoint x is enabled using the endpoint enable pin in the device endpoint x control register, the controller modifies this register. The application can only read this register as long as the controller clears the endpoint enable bit.
Page 486: Otgfs/Hs Device Out Endpoint-X Transfer Size Register
AT32F402_405 Series Reference Manual 21.6.5.24 OTGFS/HS device OUT endpoint-x transfer size register (OTGFS/HS_DOEPTSIZx) (x=1…7, where x is endpoint number) The application must set this register before enabling endpoint x. Once the endpoint x is enabled using the endpoint enable pin in the device endpoint x control register, the controller modifies this register. The application can only read this register as long as the controller clears the endpoint enable bit.
Page 487: Power And Clock Control Registers
AT32F402_405 Series Reference Manual 21.6.6 Power and clock control registers 21.6.6.1 OTGFS/HS power and clock gating control register (OTGFS/HS_PCGCCTL) This register is available in host and device modes. Abbr. Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at its default value. PHY suspend Bit 4 SUSPENDM...
Page 488: Hick Auto Clock Calibration (Acc)
AT32F402_405 Series Reference Manual 22 HICK auto clock calibration (ACC) 22.1 ACC introduction HICK auto clock calibration (HICK ACC), which uses the SOF signal (1 ms of period) generated as a reference signal, implements the sampling and calibration for the HICK clocks. The main purpose of this module is to provide a clock of 48MHz±0.25% for the USB device.
Page 489: Figure 22-2 Acc Block Diagram
AT32F402_405 Series Reference Manual  CRM_ HICKCAL: the HICKCAL signal in the CRM control module. This signal is used to calibrate the HICK in bypass mode. Its value is defined by the HICKCAL[7:0] in the CRM_CTRL register.  CRM_HICKTRIM: the HICKTRIM signal in the CRM control module. This signal is used to calibrate the HICK in bypass mode.
Page 490: Principles
AT32F402_405 Series Reference Manual 22.5 Principles USB_SOF period signal: 1ms of period must be accurate, which is a prerequisite for the normal operation of an auto calibration module. Cross-return algorithm: This is used to calculate a calibration value closest to the theoretic value. In theory, the actual frequency after calibration can be adjusted to be within an accurate range of about 0.5 steps from the target frequency (8MHz).
Page 491: Register Description
AT32F402_405 Series Reference Manual 22.6 Register description Refer to the list of abbreviations used in register descriptions. These peripheral registers must be accessed by words (32 bits). 22.6.1 ACC register map Table 22-2 ACC register map and reset values Register name Offset Reset value ACC_STS...
Page 492: Control Register 2 (Acc_Ctrl2)
AT32F402_405 Series Reference Manual relationship. Bit 7: 6 Reserved Forced by hardware to 0 CALRDY interrupt enable This bit is set or cleared by software. Bit 5 CALRDYIEN 0: Interrupt generation disabled 1: ACC interrupt is generated when CALRDY=1 in the ACC_STS register RSLOST error interrupt enable This bit is set or cleared by software.
Page 493: Compare Value 1 (Acc_C1)
AT32F402_405 Series Reference Manual 22.6.5 Compare value 1 (ACC_C1) Abbr. Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Forced to 0 by hardware Compare 1 This value is the lower boundary for triggering calibration, and its default value is 7980. When the number of clocks sampled by ACC in 1ms period is less than or equal to Bit 15: 0 0x1F2C...
Page 494: Quad-Spi Interface (Qspi)
AT32F402_405 Series Reference Manual 23 Quad-SPI interface (QSPI) 23.1 QSPI introduction The QSPI interface consists of a command-based slave port, an XIP slave port (direct address map access) and QSPI controller dedicated to SPI Flash command execution. The command-based slave port is used to access registers and data ports, and the XIP slave port reads data from direct address mapping.
Page 495: Dma Handshake Mode
AT32F402_405 Series Reference Manual 23.3.3 DMA handshake mode The DMA mode is another option to access data ports. The DMA controller register must be programmed as DMA handshake mode. In this mode, the host controller sends a DMA request when the receive/transmit FIFO threshold is reached.
Page 496: Figure 23-3 Write Enable
AT32F402_405 Series Reference Manual Figure 23-3 Write enable Mode3 Mode3 Mode0 Mode0 Instruction (06h) High Impedance To execute page programming command, set instruction code to 02h, address register, address size, write enable and set instruction length to 1. Figure 23-4 Page programming Mode3 Mode0 Instruction (02h)
Page 497: Figure 23-7 Read Dual Command
AT32F402_405 Series Reference Manual Dual mode (1-1-2) To execute a quick read dual output command, set instruction code/length to 1, address/address size to 3 bytes, set the second dummy cycle to 8, and enable dual mode. Refer to Figure 28-7 for details Figure 23-7 read dual command Mode3 Mode0...
Page 498: Figure 23-9 Read Quad Output
AT32F402_405 Series Reference Manual Figure 23-9 Read quad output Mode3 Mode0 Instruction (6Bh) 24-Bit Address Dummy Clocks IO Switches from Input to Output Byte 4 Byte 1 Byte 2 Byte 3 Quad I/O mode (1-4-4) To execute a quick read quad I/O command, set instruction code/length, address/address size, the second dummy period, enable continuous read mode/continuous read mode code and enable quad I/O mode.
Page 499: Figure 23-11 Dual Dpi Command
AT32F402_405 Series Reference Manual Figure 23-11 Dual DPI command Mode3 Mode0 INS7-0 A23-16 A15-8 A7-0 Dummy IO Switches from Input to Output Byte 1 Byte 2 Byte 3 To execute QPI (4-4-4) mode, please set code/length, address/address length, and second dummy cycles and QPI mode operating command.
Page 500 AT32F402_405 Series Reference Manual Mode3 Mode0 A23-16 A15-8 A7-0 Byte 1 Byte 2 Byte N INS7-0 Dummy Byte 3 XIP read/write T mode To execute XIP read/write T mode, please set instruction code/length, address/address length, the second dummy cycle, select serial/dual/dual IO/quad IO or DPI/QPI mode, set read/write T mode and program T mode counter.
Page 501: Qspi Registers
AT32F402_405 Series Reference Manual 23.4 QSPI registers These registers must be accessed by bytes (8-bit), half-words (16-bit) or words (32-bit). Table 23-1 SPI register map and reset values Register Offset Reset value CMD_W0 0x0000 0000 CMD_W1 0x0100 0003 CMD_W2 0x0000 0000 CMD_W3 0x0000 0000 CTRL...
Page 502: Command Word 2 (Cmd_W2)
AT32F402_405 Series Reference Manual Instruction code length Instruction code is required for SPI Flash command execution. The instruction code length varies from SPI Flash supplier to SPI Flash supplier. Thus this register can be used to program the desired instruction code length. Typically, the instruction code is one-byte length.
Page 503: Control Register (Ctrl)
AT32F402_405 Series Reference Manual Performance enhanced mode operation code This field works with the PEMEN bit. This code can be Bit 23: 16 PEMOPC 0x00 padded to execute performance enhanced mode. Follow the corresponding Flash specification document to write the corresponding value. Bit 15: 10 Reserved resd...
Page 504: Fifo Status Register (Fifosts)
AT32F402_405 Series Reference Manual XIP port selection Read SPI Flash data from the following ports: 0: Command slave port Bit 20 XIPSEL 1: XIP port When this bit is switched, the QSPI sends automatically an Abort signal. The user can send a command only after the completion of Abort function.
Page 505: Control Register 2 (Ctrl2)
AT32F402_405 Series Reference Manual 23.4.7 Control register 2 (CTRL2) No-wait states, accessible by bytes, half-words and words. Abbr. Reset value Type Description Bit 31: 14 Reserved 0x0000 0 resd Kept at its default value. This field is used to program the level value to trigger RxFIFO threshold interrupt for DMA handshake mode.
Page 506: Flash Size Register (Fsize) (Fsize)
AT32F402_405 Series Reference Manual 23.4.10 Flash size register (FSIZE) (FSIZE) No-wait states, accessible by bytes, half-words and words. Abbr. Reset value Type Description SPI Flash Size In direct address map mode, system address is always Bit 31: 0 SPIFSIZE 0xF000 0000 greater than that of SPI Flash.
Page 507: Xip Command Word 2 (Xip Cmd_W2)
AT32F402_405 Series Reference Manual XIP write operation mode 000: Serial mode (1-1-1) 001: Dual-wire mode (1-1-2) 010: Quad mode (1-1-4) Bit 10: 8 XIPW_OPMODE 011: Dual IO mode (1-2-2) 100: Quad IO mode (1-4-4) 101: DPI mode (2-2-2) 110: QPI mode (4-4-4) 111: Reserved XIP Write second dummy cycle The second dummy state is located between the address...
Page 508: Xip Command Word 3 (Xip Cmd_W3)
AT32F402_405 Series Reference Manual This indicates the time counter that is used to judge time interval in mode T. Bit 14: 8 XIPR_TCNT 0x0F Value is in terms of sck_out period. This counter is valid when mode T is selected. Bit 7: 6 Reserved resd...
Page 509: Infrared Timer (Irtmr)
AT32F402_405 Series Reference Manual 24 Infrared timer (IRTMR) The IRTMR (Infrared Timer) is used to generate the IR_OUT signal that drives the infrared LED to achieve infrared control. The IR_OUT signals consists of a low-frequency modulation envelope and high-frequency carrier signals. The low-frequency modulation envelope signal selects from TMR10_C1OUT, USART1 and USART2 through the IR_SRC_SEL[1: 0] bit in the SCFG_CFG1 register, while the high-frequency carrier signal is provided by the TMR11_C1OUT register.
Page 510: Debug (Debug)
AT32F402_405 Series Reference Manual 25 Debug (DEBUG) 25.1 Debug introduction ® Cortex -M4F core provides powerful debugging features including halt and single step support, as well as trace function that is used for checking the details of the program execution. The debug features are implemented with a serial wire debug interface.
Page 511: Debug Device Id (Debug_Idcode)
AT32F402_405 Series Reference Manual 25.4.1 DEBUG device ID (DEBUG_IDCODE) MCU integrates an ID code that is used to identify MCU’s revision code. The DEBUG_IDCODE register is mapped on the external PPB bus at address 0xE0042000. This code is accessible by the SW debug port or by the user code.
Page 512: Debug Control Register (Debug_Ctrl)
AT32F402_405 Series Reference Manual 25.4.2 DEBUG control register (DEBUG_CTRL) This register is asynchronously reset by POREST (not reset by system reset). It can be written by the debugger under reset. Abbr. Reset value Type Description Bit 31:3 Reserved 0x0000 0000 resd Always 0.
Page 513 AT32F402_405 Series Reference Manual I2C1 pause control bit I2C1_SMBUS_TIMEO Bit 24 0: I2C1 SMBUS timeout control works normally 1: I2C1 SMBUS timeout control stops running Bit 23: 16 Reserved 0x00 resd Kept at default value. Bit 15 Reserved Kept at default value. Bit 14: 13 Reserved Kept at default value.
Page 514: Debug Apb2 Pause Register (Debug_ Apb2_Pause)
AT32F402_405 Series Reference Manual 25.4.4 DEBUG APB2 pause register (DEBUG_ APB2_PAUSE) This register is asynchronously reset by POREST (not reset by system reset). It can be written by the debugger under reset. Abbr. Reset value Type Description Bit 31: 19 Reserved 0x0000 resd...
Page 515: Revision History
AT32F402_405 Series Reference Manual 26 Revision history Document Revision History Date Version Revision Note Initial release. 2023.08.31 2.00 2023.08.31 Page 515 Rev 2.00...
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