Clocking - Texas Instruments ADS1258EVM-PDK User Manual

Evaluation module
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Analog Interface
is used as the negative channel for all single-ended measurements. In Fixed-Channel mode, short REFOUT to
whichever analog input is selected as AINN in the MUXSCH register. This short can be applied externally using
terminal block J3.
Figure 3-4
A pseudo-differential measurement only sets the voltage on the MUXOUTN pin to be within the amplifier output
voltage limits. The user must also make sure that the voltage applied to the ADCINP pin is within this same
range. To measure signals that are outside of the amplifier output voltage limitations, consider bypassing the
external multiplexer loop as described in

3.4 Clocking

The ADS1258 requires a high-frequency system clock to oversample the inputs and provide digital data at the
output data rate. By default, a 16-MHz system clock is provided by the PHI controller board. The PHI also
generates the SCLK signal from the same clock domain, which improves overall ADC performance.
An external clock can also be used with the ADS1258EVM, though this setup requires altering the EVM
components. First, install SMA connector J8, then remove termination resistor R17 and install this component
at R7.
Figure 3-5
shows the external clocking circuit. See the ADS1258 data sheet for information about the
allowable clock frequency range.
8
ADS1258EVM-PDK Evaluation Module
shows both JP2 and J3.
J3
AINCOM
JP2
R2
Short AINCOM
DNP
0
to REFOUT
Figure 3-4. Shorting AINCOM to REFOUT
Section
3.3.
J8
EXT Clock
1
DNP
GND
ADC.MCLK_OUT
Figure 3-5. ADS1258EVM Clock Circuit
Copyright © 2023 Texas Instruments Incorporated
R1
ACOM
1.00k
C1
470pF
GND
R7
DNP
0
R17
CLK
49.9
SBAU126E – MAY 2007 – REVISED JUNE 2023
www.ti.com
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