Texas Instruments ADS1258EVM-PDK User Manual page 24

Bill of Materials, Layout, and Schematics
R59
1.00k
C35
47pF
C33
470pF
C31
47pF
R46
AIN7
1.00k
AIN6
AIN5
AIN4
R39
1.00k
C29
47pF
C27
470pF
C25
47pF
R37
1.00k
J1
1 AIN7
2 AIN6
Differential-Mode Input Anti-Aliasing Filter
3 AIN5
4 AIN4
3-dB Cutoff: 168.51 kHz
5 AIN3
6 AIN2
Attenuation at Modulator Data Rate (8 MHz): 33.49 dB
7 AIN1
8 AIN0
R33
1.00k
C23
47pF
C21
470pF
C18
47pF
R28
AIN3
1.00k
AIN2
AIN1
AIN0
R26
1.00k
C15
47pF
C13
470pF
C11
47pF
R22
1.00k
24 ADS1258EVM-PDK Evaluation Module
Analog Input Channels
R60
A7
1.00k
C34
470pF
GND
R47
A6
AIN15
1.00k
AIN14
AIN13
AIN12
R40
A5
1.00k
C28
470pF
GND
R38
A4
1.00k
J2
1 AIN15
2 AIN14
3 AIN13
Common-Mode Input Anti-Aliasing Filter
4 AIN12
5 AIN11
3-dB Cutoff: 3.37 MHz
6 AIN10
7 AIN9
8 AIN8
R34
A3
1.00k
C22
470pF
GND
R29
A2
AIN11
1.00k
AIN10
AIN9
AIN8
R27
A1
1.00k
C14
470pF
GND
R23
A0
1.00k
Figure 8-3. ADS1258EVM Analog Input, Multiplexer Loop, and GPIO Circuits
Copyright © 2023 Texas Instruments Incorporated
A15
C36
47pF
C32 GND
47pF
A14
A13
C30
47pF
C26 GND
47pF
A12
A11
C24
47pF
J7
C19 GND
47pF 1
A10 2
3
GND 4
5
6
A9 7
DVDD
8
9
C16 10
47pF
C12 GND
47pF
A8
Configurable Multiplexer Loop
OPA2320 is a dual op-amp package used here in a single-supply configuration
Only one decoupling cap is needed at positive supply (pin 8) for both op-amps
OPA2320AQDGKRQ1
U4A
MUXOUTP 3
R25
1
2
47.5
R24
0
R30
DNP
0
R31
0
U4B
6
R35
7
B
MUXOUTP
5
47.5
OPA2320AQDGKRQ1
U4C
AVDD
8 4
V+ V-
OPA2320AQDGKRQ1
C17
100nF
GND GND
Digital GPIO
R41
R42
R43
R44
R45
R48
R49
R50
R51 R52 R53 R54 R55 R56 R57 R58
100k 100k 100k 100k 100k 100k 100k 100k
GND
SBAU126E – MAY 2007 – REVISED JUNE 2023
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ADCINP
C20
2200pF
ADCINP
49.9 GPIO7
49.9 GPIO6
49.9 GPIO5
49.9 GPIO4
49.9 GPIO3
49.9 GPIO2
49.9 GPIO1
49.9 GPIO0