Cgpll0Sel] (Pll Selection Register For Fsys); Cgwuphcr] (High Speed Oscillation Warming Up Register) - Toshiba TXZ+ TMPM3H Reference Manual

1.4.2.6. [CGPLL0SEL] (PLL selection register for fsys)

Bit Bit Symbol
31:8 PLL0SET[23:0]
7:3 -
2 PLL0ST
1 PLL0SEL
0 PLL0ON

1.4.2.7. [CGWUPHCR] (High speed oscillation warming up register)

Bit Bit Symbol
31:20 WUPT[15:4]
19:16 WUPT[3:0]
15:9 -
8 WUCLK
7:2 -
1 WUEF
0 WUON
Note1: Use the internal oscillator for warm up when the CPU returns from STOP1 mode. Do not use an external
oscillator when the CPU returns from STOP1 mode.
Note2: Do not modify the registers during the warm up (<WUEF> = 1). Set the registers when <WUEF> = 0.
After
Type
reset
PLL multiplication setup
0x000000 R/W
About a multiplication setup, refer to "1.2.5.2. The formula and
the example of a setting of a PLL multiplication value".
0 R Read as "0"
Indicate PLL for fsys selection status.
0 R 0: f
OSC
1: f
PLL
Select Clock selection for fsys
0 R/W 0: f
OSC
1: f
PLL
Select PLL operation for fsys
0 R/W 0: Stop
1: Oscillation
After
Type
reset
Sets the upper 12 bits of the 16 bits of calculation values of the
warm up timer.
0x800 R/W
About a setup of a warming up timer, refer to "1.2.4.1. The
warming up timer for a high speed oscillation".
Sets the lower 4 bits of the 16 bits of calculation values of the
0x0 R
warm up timer. It is fixed by 0x0.
0 R Read as "0"
Warming up clock selection (Note1)
0 R/W 0: Internal high speed oscillator (IHOSC1)
1: External high speed oscillator (EHOSC)
0 R Read as "0"
Indicates status of the Warming up timer. (Note2)
0 R 0: The end of Warming up
1: In warming up operation
Control the Warming up timer.
0 W 0: don't care
1: Warming up operation start.
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TMPM3H Group(2)
Clock Control and Operation Mode
Function
Function
TXZ+ Family
2023-04-28
Rev. 1.0