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1.2.6. System clock
An internal high speed oscillation clock or external high speed oscillation clock (connected oscillator or clock
input) can be used as a source of system clock.
Dividing is possible for a system clock at [CGSYSCR]<GEAR[2:0]> (clock gear). Although a setup can be
changed during operation, after register writing before a clock actually changes, a maximum of 16-clock time is
required of fc. Check completion of a clock change by [CGSYSCR]<GEARST[2:0]>.
Note: Do not change a clock gear during operation of peripheral functions, such as a timer counter.
Table 1.4 shows the example of operation frequency by the clock gear ratio (1/1 to 1/16) to the frequency fc set up
with oscillation frequency, a PLL multiplication value, etc.
External
Internal
External
Clock
oscillation
oscillation
input
IHOSC1
(MHz)
(MHz)
(MHz)
6
6
8
8
10
10
10
12
12
6
6
8
8
10
10
10
12
12
6
6
8
8
10
10
10
12
12
Table 1.4 The example of operation frequency (unit: MHz)
PLL
Multiplication
Maximum
value
Frequency
(After
(fc) (MHz)
dividing)
-
20
120
-
15
120
12
120
-
10
120
-
13.329
79.97
-
10
8
-
6.657
79.88
-
6.625
39.75
-
5
4
-
3.3125
39.75
Clock gear
PLL = ON
1/1
1/2
1/4
120
60
30
120
60
30
120
60
30
120
60
30
79.97
39.99
20
80
80
40
20
80
80
40
20
79.88
39.95
19.98
39.75
19.9
9.94
40
40
20
10
40
40
20
10
39.75
19.9
9.94
18 / 71
TMPM3H Group(2)
Clock Control and Operation Mode
1/8
1/16
1/1
1/2
15
7.5
6
3
15
7.5
8
4
15
7.5
10
5
15
7.5
12
6
10
5
6
3
10
5
8
4
10
5
10
5
9.99
4.99
12
6
4.97
2.48
6
3
5
2.5
8
4
5
2.5
10
5
4.97
2.48
12
6
TXZ+ Family
Clock gear
PLL = OFF
1/4
1/8
1/16
1.5
-
-
2
1
-
2.5
1.25
-
3
1.5
-
1.5
-
-
2
1
-
2.5
1.25
-
3
1.5
-
1.5
-
-
2
1
-
2.5
1.25
-
3
1.5
-
2023-04-28
Rev. 1.0
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