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2. Memory Map
2.1. Overview
The memory maps for TMPM3H Group(2) are based on the Arm Cortex-M3 processor core memory map.
The internal ROM, internal RAM and special function registers (SFR) of TMPM3H Group(2) are mapped to the
Code, SRAM and peripheral regions of the Cortex-M3 respectively. The special function register (SFR) means the
control registers of all input/output ports and peripheral functions.
The CPU register area is the processor core's internal register region.
For more information on each region, see the "Arm documentation set Cortex-M3".
Note that access to regions indicated as "Fault" causes a bus fault if bus faults are enabled, or causes a hard fault if
bus faults are disabled. Also, do not access the vendor-specific region.
Clock Control and Operation Mode
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TXZ+ Family
TMPM3H Group(2)
2023-04-28
Rev. 1.0
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