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3.2.6. About turn on power supply after turn off
When the power supply is turned off, a power supply voltage must be down gentler gradient than Max value of
"Power gradient (V
POFF
3.2.6.1. When using external reset circuit or internal LVD reset output
When the power supply is turned off and the power supply voltage drops below the operation guaranteed voltage,
reset is performed with an external reset circuit or built-in LVD (when the voltage is less than the set voltage).
After that, from the state where the reset is applied, please follow the same constraints as when turning on the
power and turned on the power supply voltage.
3.2.6.2. When not using external reset circuit and internal LVD reset output
When the power supply is turned off and the power supply voltage drops below the operation guaranteed voltage,
be sure to lower the power supply voltage below the Power On Reset detection voltage (VPDET) and hold it for
200μs or more. After that, please follow the same constraints as when turning on the power and turned on the
power supply voltage.
When the power supply voltage drops below the Power On Reset detection voltage (VPDET) and cannot be held
for 200μs or more, or when the same constraints as at power on cannot keep, the CPU may not operate properly.
3.2.7. After reset release
All of the control registers of the Cortex-M3 core and the peripheral function control register (SFR) are initialized
by reset. But depend on the reset factor, initialized range is different.
Please refer to "Table 3.1 A reset factor and the initialized range" for the initialized range by each reset factor.
The reset factor when reset occurs can be checked by a reset flag register which are [RLMRSTFLG0] and
[RLMRSTFLG1]. For detail of [RLMRSTFLG0] and [RLMRSTFLG1], please refer to the reference manual
"Exception".
After the reset is released, CPU starts operation by a clock of internal high speed oscillator1 (IHOSC1). The
external clock and PLL multiple circuit should be set if necessary.
)" specified in "Electrical Characteristics".
Clock Control and Operation Mode
68 / 71
TXZ+ Family
TMPM3H Group(2)
2023-04-28
Rev. 1.0
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