Supermicro X10DRL-LN4 User Manual page 85

Chipset Configuration

Warning! Please set the correct settings for the items below. A wrong configuration
setting may cause the system to become malfunction.
North Bridge
This feature allows the user to configure the settings for the Intel North Bridge.
IIO Configuration
EV DFX (Device Function On-Hide) Feature
When this feature is set to Enable, the EV_DFX Lock Bits that are located on a
processor will always remain clear during electric tuning. The options are Dis-
able and Enable.
Snoop Response Hold Off
Use this option to set the snoop response hold-off value. The default setting
is 9 Cycles.
IIO1 Configuration
Warning: Please note that an improper setting may cause the PC-E device to mal-
function.
IOU2 (IIO1 PCI-E Port 1)
This item configures the PCI-E setting for the device installed in a PCI-E slot
specified by the user. The options are x4x4, x8, and Auto.
CPU1 SLOT2 PCI-E 3.0 X8 Link Speed
This item configures the link speed for a PCI-E port specified by the user. The
options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
IOU0 (IIO1 PCI-E Port 2)
This item configures the PCI-E setting for the device installed in a PCI-E slot
specified by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16,
and Auto.
CPU1 SLOT3 PCI-E 3.0 X8 Link Speed
This item configures the link speed for a PCI-E port specified by the user. The
options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
4-11
Chapter 4: AMI BIOS