Supermicro X10DRL-LN4 User Manual page 13

Table of Contents

Advertisement

Jumper
Description
JBT1
Clear CMOS Configuration
JI
C1/JI
C2
SMB to PCI-E Slots
2
2
JPB1
BMC Enable/Disable
JPG1
VGA Enable/Disable
JPL1
GLAN1/2 & GLAN3/4 Enable/Disable
JPME2
ME Manufacturing Mode Select
JWD1
Watch Dog Timer Enable/Disable
Connectors
BT1
COM1
FAN 1-6, FAN A/B
J24
JD1
JF1
JIPMB1
JL1
JPI
C1
2
JPWR1/JPWR2
JSD1/JSD2
JSTBY1
JTPM1
LAN1/LAN2 (JLAN1)
LAN3/LAN4 (JLAN2)
IPMI_LAN
I-SGPIO1
I-SATA 0-3
I-SATA 4/5
S-SATA 0-3
(PCH) Slot1
(CPU1) Slot2
(CPU1) Slot3
X10DRL-LN4 Jumpers
X10DRL-LN4 Connectors
Description
Onboard CMOS battery (See Chpt. 3 for Used Battery Dis-
posal)
Front accessible COM1 header
CPU/system fan headers 1-6, A/B
24-pin ATX main power connector (See the warning on Pg.
1-6.)
Speaker/power LED
Front panel control header
4-pin external BMC I
Chassis intrusion header
Power supply SMBus I
12V 8-Pin power connectors (See Warning on Pg. 1-6.)
SATA DOM (Device on Module) power connectors 1/2
Standby power connector
TPM (Trusted Platform Module)/Port 80 header
G-bit Ethernet (GLAN) ports 1/2 on the I/O backplane
G-bit Ethernet (GLAN) ports 3/4 on the I/O backplane
IPMI_Dedicated LAN support by the Aspeed controller
Seria_Link General Purpose I/O (SGPIO) header 1 (for I-
SATA4/5)
SATA 3.0 connector w/support of I-SATA 0-3
SATA 3.0 connectors w/power-pins built-in w/support of
SuperDOMs(I-SATA4/I-SATA5)
SATA 3.0 connectors supported by Intel SCU (S-SATA 0-3)
PCI-Express 2.0 x4 in x8 slot from Intel PCH
PCI-Express 3.0 x8 slot from CPU1
PCI-Express 3.0 x8 slot from CPU1
1-5
Chapter 1: Overview
Default Setting
(See Chapter 2)
Pins 2-3 (Disabled)
Pins 1-2 (Enabled)
Pins 1-2 (Enabled)
Pins 1-2 (Enabled)
Pins 1-2 (Normal)
Pins 1-2 (Reset)
C header (for an IPMI card)
2
C header
2

Advertisement

Table of Contents
loading

Table of Contents