Intel AC450NX Product Manual page 237

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Install an equal number of DIMMs on each memory module, in the two memory module
configuration, except when only four DIMMs are used. In that case, all four DIMMs are on
the primary memory module installed in primary connector on the midplane.
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All DIMMs on a memory module are identical in size and speed.
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DIMMs may differ in size and speed between memory modules. However, the maximum data
transfer rate can only be provided when the banks of each module are configured identically
(through module-to-module interleaving as indicated in the rules below).
To take advantage of address bit permuting (ABP), which increases memory access performance
across sequential cache line accesses, the following rules must be followed:
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All banks that are used must be populated with four DIMMs.
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There must be a power of two banks populated (2, 4, 8, or 16).
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All banks in an ABP group (two banks in 2-bank permuting or four banks in 4-bank
permuting) must be the same size.
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All populated banks must be adjacent and start at bank 0.
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When it is required that both memory modules be in the server, both must be configured to
allow equivalent ABP settings. For example, the chip set cannot support 2-bank permuting on
one module and 4-bank permuting on the other.
To take advantage of module-to-module interleaving, which provides maximum performance
across sequential cache line accesses, the following rules must be followed:
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All ABP rules above must be followed.
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Two memory modules must used, and corresponding banks must be identically populated with
DIMMs of the same size and type.
Before allowing the processors to come out of reset, server management firmware scans the
presence-detect bits of all DIMMs installed on the memory modules. If they are 50-ns DIMMs,
then server management changes the value of the chipset's DRAM speed-mode bit. The default
value on this bit is a high voltage level, which corresponds to 60-ns timings; changing the value to
a low voltage level places this bit in the 50-ns mode. Changing the value of the bit can only be
effected by software, and it must be before the processors come out of reset. If the bit changes
while a memory access is in process, the results are unpredictable. After deciding the value of the
bit and making any necessary changes, server management may proceed with processor reset.
While changing this bit will not increase the theoretical maximum bandwidth, it will decrease
initial latency of DRAM reads by one clock and increase bandwidth of consecutive page misses.
When installing less than 16 DIMMs on a memory module, there is a preferred order for
populating the DIMM sockets to maintain optimal signal integrity. When installing two memory
modules on the CPU baseboard, you should always alternate DIMM installation between memory
modules. For instance, when installing 16 DIMMs in the system, the quantities should be divided
such that eight fill the first two banks of one module and eight more fill the same two banks in the
second module. See the DIMM interleave configurations in Figures 19-1 through 19-3.
Chapter 19 Memory Modules: Description/Adding Memory
235